Oxford Semiconductor Ltd.
25 ParkGate, Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900
Fax: +44(0)1235 821141
Oxford Semiconductor 2000
OXCB950 Datasheet 1.1 November 2000
Part No. OXCB950-TQFP-A
F
EATURE
Single 16C950 High performance UART channel
Cardbus/PCI compliant, single-function target
controller. Fully compliant to PC Card Standard 7.0*,
and PCI Bus Specification 2.2, Power Management
1.0.
Function access to pre-configure UART prior to
handover to generic device drivers.
UART fully software compatible with 16C550-type
devices.
Baud rates up to 15Mbps in asynchronous mode and
60Mbps in external 1x clock mode
128-byte deep FIFO per transmitter and receiver
Flexible clock prescaler from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff in both directions
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
Arbitrary trigger levels for receiver and transmitter
FIFO interrupts and automatic in-band and out-of-
band flow control
Infra-red (IrDA) receiver and transmitter operation
9-bit data framing as well as 5,6,7 and 8
Global Interrupt Status and readable FIFO levels to
facilitate implementation of efficient device drivers
Detection of bad data in the receiver FIFO
Operation via IO or memory mapping.
2 Multi-purpose I/O pins which can be configured as
interrupt input or `wake-up' pins
Auto-detection of optional Microwire
TM
based
EEPROM, to reconfigure device.
Autodetected.
3.3V operation
100 pin TQFP package
* Compliance to PC Card Standard 7.1 requires small external circuitry.
D
ESCRIPTION
The OXCB950 is a single chip UART solution for either
cardbus or PCI-based serial add-in cards. It is a single
function device, offering memory or IO mapped access to
the ultra-high performance OX16C950 UART.
This UART is the fastest available PC-compatible UART,
offering data rates up to 15Mbps and 128-deep transmitter
and receiver FIFOs. The deep FIFOs reduce CPU
overhead and allow utilisation of higher data rates. The
UART is software compatible with the widely used industry-
standard 16C550 devices and compatibles, as well as the
OX16C95x family of high performance UARTs. In addition
to increased performance and FIFO size, the UART also
provides the full set of OX16C95x enhanced features
including automated in-band flow control, readable FIFO
levels etc.
A set of local registers is available to enhance device driver
efficiency and reduce interrupt latency. The internal UART
has features such as shadowed FIFO fill levels, an interrupt
source register and Good-Data Status, readable in one
DWORD register visible to logical function0 in IO space
and memory space.
The efficient 32-bit, 33MHz target-only interface is
compliant with both the cardbus sections of the PC CARD
Standard, release 7.0*, and the PCI bus specifications
version 2.2 and version 1.0 of PCI Power Management
Specification.
For full flexibility, all the default register values can be
overwritten using an optional Microwire
TM
serial EEPROM.
This EEPROM can also be used to provide function access
to pre-configure the UART into enhanced modes prior to
any cardbus/PCI configuration accesses and before control
is handed to generic device drivers.
OXCB950
Integrated High Performance UART
Cardbus / PCI interface
Data Sheet Revision 1.1
Page 2
OXCB950
OXFORD SEMICONDUCTOR LTD.
C
ONTENTS
1 PERFORMANCE COMPARISON..................................................................................................4
1.1
IMPROVEMENTS OF THE OXCB950 OVER DISCRETE SOLUTIONS:........................................................................... 4
2 BLOCK DIAGRAM.......................................................................................................................5
3 PIN INFORMATION .....................................................................................................................6
4 PIN DESCRIPTIONS....................................................................................................................7
5 CONFIGURATION & OPERATION .............................................................................................11
6 PCI TARGET CONTROLLER .....................................................................................................12
6.1
OPERATION........................................................................................................................................................................ 12
6.2
CONFIGURATION SPACE ................................................................................................................................................. 13
6.2.1
CARDBUS / PCI CONFIGURATION SPACE REGISTER MAP..................................................................................... 13
6.3
ACCESSING THE UART FUNCTION ................................................................................................................................ 15
6.3.1
CARDBUS/PCI ACCESS TO THE INTERNAL UART.................................................................................................... 15
6.4
ACCESSING LOCAL CONFIGURATION REGISTERS .................................................................................................... 16
6.4.1
LOCAL CONFIGURATION AND CONTROL REGISTER `LCC' (OFFSET 0X00) ......................................................... 16
6.4.2
MULTI-PURPOSE I/O CONFIGURATION REGISTER `MIC' (OFFSET 0X04) ............................................................. 17
6.4.3
UART MIRROR REGISTER `UMR' (OFFSET 0X08): .................................................................................................... 18
6.4.4
GLOBAL INTERRUPT STATUS AND CONTROL REGISTER `GIS' (OFFSET 0X0C) ................................................ 19
6.5
CARDBUS/ PCI INTERRUPT ............................................................................................................................................. 20
6.6
CARDBUS/PCI POWER MANAGEMENT.......................................................................................................................... 21
6.6.1
POWER MANAGEMENT VIA UART/ MIO PINS............................................................................................................ 21
6.6.2
POWER REPORTING..................................................................................................................................................... 22
6.6.3
CARDBUS POWER MANAGEMENT ............................................................................................................................. 23
6.7
CARDBUS STATUS REGISTERS ..................................................................................................................................... 24
6.8
CARDBUS TUPLE INFORMATION ................................................................................................................................... 26
7 INTERNAL OX16C950 UART .....................................................................................................27
7.1
OPERATION MODE SELECTION ................................................................................................................................... 27
7.1.1
450 MODE ....................................................................................................................................................................... 27
7.1.2
550 MODE ....................................................................................................................................................................... 27
7.1.3
750 MODE ....................................................................................................................................................................... 27
7.1.4
650 MODE ....................................................................................................................................................................... 27
7.1.5
950 MODE ....................................................................................................................................................................... 28
7.2
REGISTER DESCRIPTION TABLES ................................................................................................................................. 29
7.3
RESET CONFIGURATION ................................................................................................................................................. 33
7.3.1
HARDWARE RESET....................................................................................................................................................... 33
7.3.2
SOFTWARE RESET ....................................................................................................................................................... 33
7.4
TRANSMITTER AND RECEIVER FIFOS........................................................................................................................... 34
7.4.1
FIFO CONTROL REGISTER `FCR'................................................................................................................................ 34
7.5
LINE CONTROL & STATUS............................................................................................................................................... 35
7.5.1
FALSE START BIT DETECTION .................................................................................................................................... 35
7.5.2
LINE CONTROL REGISTER `LCR'................................................................................................................................ 35
7.5.3
LINE STATUS REGISTER `LSR'.................................................................................................................................... 36
7.6
INTERRUPTS & SLEEP MODE ......................................................................................................................................... 37
7.6.1
INTERRUPT ENABLE REGISTER `IER' ........................................................................................................................ 37
7.6.2
INTERRUPT STATUS REGISTER `ISR' ........................................................................................................................ 38
7.6.3
INTERRUPT DESCRIPTION .......................................................................................................................................... 38
7.6.4
SLEEP MODE ................................................................................................................................................................. 39
7.7
MODEM INTERFACE ......................................................................................................................................................... 39
7.7.1
MODEM CONTROL REGISTER `MCR'.......................................................................................................................... 39
Data Sheet Revision 1.1
Page 3
OXCB950
OXFORD SEMICONDUCTOR LTD.
7.7.2
MODEM STATUS REGISTER `MSR' ............................................................................................................................. 40
7.8
OTHER STANDARD REGISTERS ..................................................................................................................................... 40
7.8.1
DIVISOR LATCH REGISTERS `DLL & DLM' ................................................................................................................. 40
7.8.2
SCRATCH PAD REGISTER `SPR'................................................................................................................................. 40
7.9
AUTOMATIC FLOW CONTROL......................................................................................................................................... 41
7.9.1
ENHANCED FEATURES REGISTER `EFR'................................................................................................................... 41
7.9.2
SPECIAL CHARACTER DETECTION ............................................................................................................................ 42
7.9.3
AUTOMATIC IN-BAND FLOW CONTROL ..................................................................................................................... 42
7.9.4
AUTOMATIC OUT-OF-BAND FLOW CONTROL........................................................................................................... 42
7.10
BAUD RATE GENERATION............................................................................................................................................... 43
7.10.1
GENERAL OPERATION ................................................................................................................................................. 43
7.10.2
CLOCK PRESCALER REGISTER `CPR' ....................................................................................................................... 43
7.10.3
TIMES CLOCK REGISTER `TCR'................................................................................................................................... 43
7.10.4
EXTERNAL 1X CLOCK MODE....................................................................................................................................... 45
7.10.5
CRYSTAL OSCILLATOR CIRCUIT ................................................................................................................................ 45
7.11
ADDITIONAL FEATURES .................................................................................................................................................. 45
7.11.1
ADDITIONAL STATUS REGISTER `ASR'...................................................................................................................... 45
7.11.2
FIFO FILL LEVELS `TFL & RFL' ..................................................................................................................................... 46
7.11.3
ADDITIONAL CONTROL REGISTER `ACR' .................................................................................................................. 46
7.11.4
TRANSMITTER TRIGGER LEVEL `TTL' ........................................................................................................................ 47
7.11.5
RECEIVER INTERRUPT. TRIGGER LEVEL `RTL' ........................................................................................................ 47
7.11.6
FLOW CONTROL LEVELS `FCL' & `FCH'...................................................................................................................... 47
7.11.7
DEVICE IDENTIFICATION REGISTERS ....................................................................................................................... 47
7.11.8
CLOCK SELECT REGISTER `CKS' ............................................................................................................................... 48
7.11.9
NINE-BIT MODE REGISTER `NMR'............................................................................................................................... 48
7.11.10
MODEM DISABLE MASK `MDM' .................................................................................................................................... 49
7.11.11
READABLE FCR `RFC'................................................................................................................................................... 49
7.11.12
GOOD-DATA STATUS REGISTER `GDS' ..................................................................................................................... 49
7.11.13
DMA STATUS REGISTER `DMS'................................................................................................................................... 50
7.11.14
PORT INDEX REGISTER `PIX'....................................................................................................................................... 50
7.11.15
CLOCK ALTERATION REGISTER `CKA'....................................................................................................................... 50
8 SERIAL EEPROM SPECIFICATION ...........................................................................................51
8.1
EEPROM DATA ORGANISATION ..................................................................................................................................... 51
8.1.1
ZONE0: HEADER............................................................................................................................................................ 51
8.1.2
ZONE1 : POWER MANAGEMENT DATA, DATA_SCALE ZONE ................................................................................. 52
8.1.3
ZONE2: LOCAL CONFIGURATION REGISTER ZONE ................................................................................................ 53
8.1.4
ZONE 3 : CARDBUS INFORMATION STRUCTURE..................................................................................................... 53
8.1.5
ZONE4: PCI CONFIGURATION REGISTERS ............................................................................................................... 54
8.1.6
ZONE5: FUNCTION ACCESS ........................................................................................................................................ 55
9 COMPLIANCE TO PC CARD STANDARDS, 7.0 AND 7.1 ............................................................57
10
OPERATING CONDITIONS.....................................................................................................60
11
DC ELECTRICAL CHARACTERISTICS ...................................................................................61
11.1
NORMAL 3.3V I/O BUFFERS............................................................................................................................................. 61
11.2
5.0V TOLERANT I/O BUFFERS........................................................................................................................................ 61
11.3
DUAL MODE (CARDBUS/PCI) I/O BUFFERS ................................................................................................................. 62
12
POWER CONSUMPTION MEASUREMENTS...........................................................................63
12.1
STATIC CURRENT CONSUMPTION ................................................................................................................................. 63
12.2
CURRENT CONSUMPTION IN APPLICATION ................................................................................................................. 63
13
TIMING WAVEFORMS............................................................................................................64
14
PHYSICAL PACKAGE DETAILS.............................................................................................66
Data Sheet Revision 1.1
Page 4
OXCB950
OXFORD SEMICONDUCTOR LTD.
1 P
ERFORMANCE
C
OMPARISON
Feature
OXCB950
16C550 +
PLX9050
16C650 +
PLX9050
Support for PCI Power Management
yes
no
No
Zero wait-state read/write operation
yes
no
No
No. of external interrupt source pins
2
2
2
DWORD access to UART Interrupt Source
Registers & FIFO Levels
yes
no
No
Good-Data status
yes
no
No
Full Plug and Play with external EEPROM
yes
yes
Yes
External 1x baud rate clock
yes
no
No
Max baud rate in normal mode
15 Mbps
115 Kbps
1.5 Mbps
Max baud rate in 1x clock mode
60 Mbps
n/a
n/a
FIFO depth
128
16
64
Sleep mode
yes
no
Yes
Auto Xon/Xoff flow
yes
no
Yes
Auto CTS#/RTS# flow
yes
no
Yes
Auto DSR#/DTR# flow
yes
no
No
No. of Rx interrupt thresholds
128
4
4
No. of Tx interrupt thresholds
128
1
4
No. of flow control thresholds
128
n/a
4
Transmitter empty interrupt
yes
no
No
Readable status of flow control
yes
no
No
Readable FIFO levels
yes
no
No
Clock prescaler options
248
n/a
2
Rx/Tx disable
yes
no
No
Software reset
yes
no
No
Device ID
yes
no
No
9-bit data frames
yes
no
No
RS485 buffer enable
yes
no
No
Infra-red (IrDA)
yes
no
Yes
Table 1: OXCB950 performance compared with PLX + generic UART combinations in PCI mode
1.1 Improvements of the OXCB950 over discrete solutions:
Improved access timing:
Access to the internal UART requires zero or one PCI wait states. A cardbus/PCI read transaction from the internal UART can
complete within five PCI clock cycles and a write transaction to the internal UART can complete within four PCI clock cycles.
Reduces interrupt latency:
The OXCB950 offers shadowed FIFO levels and Interrupt status registers of the internal UART, as well as general device
interrupt status, to reduce the device driver interrupt latency.
Power management:
The OXCB950 complies with the Cardbus Power Management Specification, given by the PC CARD standard release 7.0/7.1,
the PCI Power Management Specification 1.0 and the PC98/99 Power Management specifications, by offering the extended
capabilities for Power Management and supporting the power states D0, D2 and D3. This achieves significant power savings by
allowing device drivers to power down the cardbus/PCI function and disable the UART channel.
Data Sheet Revision 1.1
Page 5
OXCB950
OXFORD SEMICONDUCTOR LTD.
A `wake-up' event (the `power management event') is requested via the PME# (PCI) or CSYSCHG (cardbus) pins from either of
the power states D2 or D3, by the UART line RI (for power state D3), and any modem line and the Serial Data In (for power state
D2).
Optional EEPROM:
The OXCB950 can be reconfigured from an external Microwire
TM
based EEPROM. However, this is not required in many
applications as default values are provided for typical applications. Features available via the use of the EEPROM include
redefining device ID's and vendor/sub-vendor ID fields in the PCI header space, cardbus-to-pci mode change, redefining Tuple
Information (relevant to cardbus applications only), and selectively enabling/disabling interrupts, powerdown and wakeup
requests.
2 B
LOCK
D
IAGRAM
PCI
3.3V or
CardBus
Interface
AD[31:0]
C/BE[3:0]
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
RST#
IDSEL
INTA#
INTB#
PME#
Clock &
Baud rate
Generator
XTALO
XTALI
EEPROM
interface
EE_DO
EE_DI
EE_CK
EE_CS
Internal Data/Control Bus
Function 0
Interrupt logic
UART
MIO pins
SOUT
SIN
RTS
DTR
CTS
DSR
DCD
RI
MIO[1:0]
SLEW_RATE
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