Semiconductor Components Industries, LLC, 2001
August, 2001 Rev. 1
1
Publication Order Number:
74FST3125/D
74FST3125
4-Bit Bus Switch
The ON Semiconductor 74FST3125 is a quad, high performance
switch. The device is CMOS TTL compatible when operating between
4 and 5.5 Volts. The device exhibits extremely low R
ON
and adds
nearly zero propagation delay. The device adds no noise or ground
bounce to the system.
The device consists of four independent 1bit switches with
separate Output/Enable (OE) pins. Port A is connected to Port B when
OE is low. If OE is high, the switch is high Z.
R
ON
t 4 W Typical
Less Than 0.25 nsMax Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
PinForPin Compatible With QS3125, FST3125, CBT3125
All Popular Packages: QSOP16, TSSOP14, SOIC14
OE
1
OE
2
GND
2B
2A
1B
1A
V
CC
4B
3B
3A
OE
3
4A
OE
4
NC
1B
2B
2A
OE
2
1A
OE
1
V
CC
4B
3B
3A
OE
3
4A
OE
4
GND
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1
2
3
4
5
6
7
16
15
14
13
12
11
10
8
9
Figure 1. Pin Assignment for
SOIC and TSSOP
Figure 2. Pin Assignment
for QSOP
Description
PIN NAMES
OE
1
, OE
2
, OE
3
, OE
4
1A, 2A, 3A, 4A
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Device
Package
Shipping
ORDERING INFORMATION
74FST3125D
SO14
55 Units/Rail
74FST3125DR2
SO14
74FST3125DT
TSSOP14
2500 Units/Reel
96 Units/Rail
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
74FST3125DTR2
TSSOP14
2500 Units/Reel
74FST3125QS
QSOP16
98 Units/Rail
74FST3125QSR
QSOP16
2500 Units/Reel
TSSOP14
DT SUFFIX
CASE 948G
14
1
QSOP16
QS SUFFIX
CASE 492
SO14
D SUFFIX
CASE 751A
14
1
1
14
FST
3125
ALYW
FST3125
AWLYWW
14
1
MARKING
DIAGRAMS
S3125
ALYW
16
1
Pin
Bus Switch Enables
Bus A
1B, 2B, 3B, 4B
Bus B
NC
Not Connected
16
1
74FST3125
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2
2
1
5
4
9
10
12
13
3
6
8
11
1B
2B
3B
4B
1A
2A
3A
4A
OE
1
OE
2
OE
3
OE
4
Figure 3. Logic Diagram
TRUTH TABLE
Inputs
Outputs
OE
A, B
L
A = B
H
Z
74FST3125
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3
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
*
0.5 to
)
7.0
V
V
I
DC Input Voltage
*
0.5 to
)
7.0
V
V
O
DC Output Voltage
*
0.5 to
)
7.0
V
I
IK
DC Input Diode Current
V
I
t
GND
*
50
mA
I
OK
DC Output Diode Current
V
O
t
GND
*
50
mA
I
O
DC Output Sink Current
128
mA
I
CC
DC Supply Current per Supply Pin
$
100
mA
I
GND
DC Ground Current per Ground Pin
$
100
mA
T
STG
Storage Temperature Range
*
65 to
)
150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
260
_
C
T
J
Junction Temperature Under Bias
)
150
_
C
q
JA
Thermal Resistance (Note 1)
SOIC
TSSOP
QSOP
125
170
200
_
C/W
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
u
2000
u
200
V
I
LATCHUP
LatchUp Performance
Above V
CC
and Below GND at 85
_
C (Note 4)
$
500
mA
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximumrated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. Measured with minimum pad spacing on an FR4 board, using 10 mmby1 inch, 2ounce copper trace with no air flow.
2. Tested to EIA/JESD22A114A.
3. Tested to EIA/JESD22A115A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage
Operating, Data Retention Only
4.0
5.5
V
V
I
Input Voltage
(Note )
0
5.5
V
V
O
Output Voltage
(HIGH or LOW State)
0
V
CC
V
T
A
Operating FreeAir Temperature
*
40
)
85
_
C
D
t/
D
V
Input Transition Rise or Fall Rate
Switch Control Input
Switch I/O
0
0
5
DC
ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or lowlogic input voltage level.
74FST3125
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4
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
=
*
40
_
C to
)
85
_
C
Symbol
Parameter
Conditions
(V)
Min
Typ*
Max
Unit
V
IK
Clamp Diode Resistance
I
IN
=
*
18mA
4.5
*
1.2
V
V
IH
HighLevel Input Voltage
4.0 to 5.5
2.0
V
V
IL
LowLevel Input Voltage
4.0 to 5.5
0.8
V
I
I
Input Leakage Current
0
v
V
IN
v
5.5 V
5.5
$
1.0
m
A
I
OZ
OFFSTATE Leakage Current
0
v
A, B
v
V
CC
5.5
$
1.0
m
A
R
ON
Switch On Resistance (Note 6)
V
IN
= 0 V, I
IN
= 64 mA
4.5
4
7
W
V
IN
= 0 V, I
IN
= 30 mA
4.5
4
7
V
IN
= 2.4 V, I
IN
= 15 mA
4.5
8
15
V
IN
= 2.4 V, I
IN
= 15 mA
4.0
11
20
I
CC
Quiescent Supply Current
V
IN
= V
CC
or GND, I
OUT
= 0
5.5
3
m
A
D
I
CC
Increase In I
CC
per Input
One input at 3.4 V, Other inputs at V
CC
or GND
5.5
2.5
mA
*Typical values are at V
CC
= 5.0 V and T
A
= 25
_
C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch.
AC ELECTRICAL CHARACTERISTICS
Limits
T
A
=
*
40
_
C to
)
85
_
C
V
CC
= 4.5 to 5.5 V
V
CC
= 4.0 V
Symbol
Parameter
Conditions
Figures
Min
Max
Min
Max
Unit
t
PHL
,
t
PLH
Prop Delay Bus to Bus
(Note 7)
V
I
= OPEN
4 and 5
0.25
0.25
ns
t
PZH
,
t
PZL
Output Enable Time
V
I
= 7 V for t
PZL
V
I
= OPEN for t
PZH
4 and 5
1.0
5.0
5.5
ns
t
PHZ
,
t
PLZ
Output Disable Time
V
I
= 7 V for t
PLZ
V
I
= OPEN for t
PHZ
4 and 5
1.5
5.3
5.6
ns
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter
Conditions
Typ
Max
Unit
C
IN
Control Pin Input Capacitance
V
CC
= 5.0 V
3
pF
C
I/O
Input/Output Capacitance
V
CC
, OE = 5.0 V
5
pF
8. T
A
=
)
25
_
C, f = 1 MHz, Capacitance is characterized but not tested.
74FST3125
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5
V
I
V
OL
V
OL
+ 0.3 V
t
PLH
t
PLH
Vmi
V
OL
V
OH
V
OH
0.3 V
t
PHZL
t
f
= 2.5 nS
90 %
1.5 V
10 %
10 %
1.5 V
90 %
t
f
= 2.5 nS
t
PZL
t
PZL
OUTPUT
1.5 V
OUTPUT
1.5 V
GND
3.0 V
t
PZH
ENABLE
INPUT
t
f
= 2.5 nS
90 %
1.5 V
1.5 V
90 %
10 %
10 %
1.5 V
1.5 V
V
OH
GND
3.0 V
SWITCH
INPUT
t
f
= 2.5 nS
C
L
*
FROM
OUTPUT
UNDER
TEST
Figure 4. AC Test Circuit
Figure 5. Propagation Delays
AC Loading and Waveforms
NOTES:
1. Input driven by 50
W
source terminated in 50
W
.
2. CL includes load and stray capacitance.
*C
L
= 50 pF
500
W
500
W
Figure 6. Enable/Disable Delays
OUTPUT
74FST3125
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6
PACKAGE DIMENSIONS
SO14
D SUFFIX
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
B
G
P
7 PL
14
8
7
1
M
0.25 (0.010)
B
M
S
B
M
0.25 (0.010)
A
S
T
T
F
R
X 45
SEATING
PLANE
D
14 PL
K
C
J
M
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
8.55
8.75
0.337
0.344
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.228
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
TSSOP14
DT SUFFIX
CASE 948G01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
---
1.20
---
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.50
0.60
0.020
0.024
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
_
_
_
_
S
U
0.15 (0.006) T
2X
L/2
S
U
M
0.10 (0.004)
V
S
T
L
U
SEATING
PLANE
0.10 (0.004)
T
SECTION NN
DETAIL E
J J1
K
K1
DETAIL E
F
M
W
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U
0.15 (0.006) T
V
14X REF
K
N
N
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7
PACKAGE DIMENSIONS
QSOP16
QS SUFFIX
CASE 49201
ISSUE O
MIN
MILLIMETERS
G
R
B
A
L
M
0.25 (0.010)
T
U
T
SEATING
PLANE
K
D
16 PL
C
M
0.25 (0.010)
T B
A
S
S
V
N
J
M
F
8 PL
DETAIL E
DETAIL E
H x 45
_
RAD.
MOLD PIN
DIM
MAX
MIN
MAX
INCHES
A
4.80
4.98
0.189
0.196
B
3.81
3.99
0.150
0.157
C
1.55
1.73
0.061
0.068
D
0.20
0.31
0.008
0.012
F
0.41
0.89
0.016
0.035
G
0.64 BSC
0.025 BSC
H
0.20
0.46
0.008
0.018
J
0.249
0.191
0.0098 0.0075
K
0.10
0.25
0.004
0.010
L
5.84
6.20
0.230
0.244
M
0
8
0
8
N
0
7
0
7
P
0.18
0.28
0.007
0.011
Q
0.51 DIA
0.020 DIA
R
0.64
0.89
0.025
0.035
U
0.64
0.89
0.025
0.035
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER
THAN THE TOP PACKAGE BY 4 MILS (NOTE:
LEAD SIDE ONLY). BOTTOM PACKAGE
DIMENSION SHALL FOLLOW THE DIMENSION
STATED IN THIS DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE
MOLD FLASH OR PROTRUSIONS. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 6 MILS
PER SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY
I.D.
_
_
_
_
0
8
0
_
_
_
8
_
_
_
_
_
MARK
Q
P
0.013 X 0.005
DP. MAX
RAD.
0.0050.010
TYP
74FST3125
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8
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4321 NishiGotanda, Shinagawaku, Tokyo, Japan 1410031
Phone: 81357402700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
74FST3125/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
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