Semiconductor Components Industries, LLC, 2005
January, 2005 - Rev. 2
1
Publication Order Number:
74FST3253/D
74FST3253
Dual 4:1 Multiplexer/
Demultiplexer Bus Switch
The ON Semiconductor 74FST3253 is a dual 4:1, high performance
multiplexer/demultiplexer bus switch. The device is CMOS TTL
compatible when operating between 4 and 5.5 Volts. The device
exhibits extremely low R
ON
and adds nearly zero propagation delay.
The device adds no noise or ground bounce to the system.
Features
R
ON
t 4 W Typical
Less Than 0.25 ns-Max Delay Through Switch
Nearly Zero Standby Current
No Circuit Bounce
Control Inputs are TTL/CMOS Compatible
Pin-For-Pin Compatible With QS3253, FST3253, CBT3253
All Popular Packages: QSOP-16, TSSOP-16, SOIC-16
All Devices in Package TSSOP are Inherently Pb-Free*
1B
3
1A
1B
1
1B
2
1B
4
OE
1
V
CC
S
0
OE
2
GND
2A
1
2
3
4
5
6
7
16
15
14
13
12
11
10
8
9
Figure 1. 16-Lead
Pinout
Figure 2. Truth Table
S1
2B
4
2B
3
2B
2
2B
1
X
X
L
L
H
H
S
1
Function
X
X
L
H
L
H
S
0
H
X
L
L
L
L
OE
1
X
H
L
L
L
L
OE
2
Disconnect 1A
Disconnect 2A
A = B
1
A = B
2
A = B
3
A = B
4
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Description
PIN NAMES
OE
1
, OE
2
S
0
, S
1
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
TSSOP-16
DT SUFFIX
CASE 948F
16
1
QSOP-16
QS SUFFIX
CASE 492
SOIC-16
D SUFFIX
CASE 751B
16
1
1
16
FST3253
AWLYWW
MARKING
DIAGRAMS
16
1
Pin
Bus Switch Enables
Select Inputs
A
Bus A
B
1
, B
2
, B
3
, B
4
Bus B
16
1
1
16
FST
3253
ALYW
S3253
ALYW
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
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74FST3253
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2
Figure 3. Logic Diagram
1B
1
1B
2
1B
3
1B
4
2B
1
2B
2
2B
3
2B
4
1A
2A
OE
1
S
0
S
1
OE
2
FLOW CONTROL
ORDERING INFORMATION
Device Order N mber
Package
Shipping
Device Order Number
Package
Shipping
74FST3253D
SOIC-16
48 Units / Rail
74FST3253DR2
SOIC-16
2500 Units / Tape & Reel
74FST3253DT
TSSOP-16*
(Pb-Free)
96 Units / Rail
74FST3253DTR2
TSSOP-16*
(Pb-Free)
2500 Units / Tape & Reel
74FST3253QS
QSOP-16
96 Units / Rail
74FST3253QSR
QSOP-16
2500 Units / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb-Free.
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3
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
*
0.5 to
)
7.0
V
V
I
DC Input Voltage
*
0.5 to
)
7.0
V
V
O
DC Output Voltage
*
0.5 to
)
7.0
V
I
IK
DC Input Diode Current
V
I
t
GND
*
50
mA
I
OK
DC Output Diode Current
V
O
t
GND
*
50
mA
I
O
DC Output Sink Current
128
mA
I
CC
DC Supply Current per Supply Pin
$
100
mA
I
GND
DC Ground Current per Ground Pin
$
100
mA
T
STG
Storage Temperature Range
*
65 to
)
150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
260
_
C
T
J
Junction Temperature Under Bias
)
150
_
C
q
JA
Thermal Resistance
SOIC
TSSOP
QSOP
125
170
200
_
C/W
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
u
2000
u
200
N/A
V
I
Latchup
Latchup Performance
Above V
CC
and Below GND at 85
_
C (Note 4)
$
500
mA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22-A114-A.
2. Tested to EIA/JESD22-A115-A.
3. Tested to JESD22-C101-A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage
Operating, Data Retention Only
4.0
5.5
V
V
I
Input Voltage
(Note )
0
5.5
V
V
O
Output Voltage
(HIGH or LOW State)
0
5.5
V
T
A
Operating Free-Air Temperature
*
40
)
85
_
C
D
t/
D
V
Input Transition Rise or Fall Rate
Switch Control Input
Switch I/O
V
CC
= 5.0 V
$
0.5 V
0
DC
5
ns/V
5. Unused control inputs may not be left open. All control inputs must be tied to a high or low logic input voltage level.
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4
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
=
*
40
_
C to
)
85
_
C
Symbol
Parameter
Conditions
(V)
Min
Typ*
Max
Unit
V
IK
Clamp Diode Resistance
I
IN
=
*
18mA
4.5
*
1.2
V
V
IH
High-Level Input Voltage
4.0 to 5.5
2.0
V
V
IL
Low-Level Input Voltage
4.0 to 5.5
0.8
V
I
I
Input Leakage Current
0
v
V
IN
v
5.5 V
5.5
$
1.0
m
A
I
OZ
OFF-STATE Leakage Current
0
v
A, B
v
V
CC
5.5
$
1.0
m
A
R
ON
Switch On Resistance (Note 6)
V
IN
= 0 V, I
IN
= 64 mA
4.5
4
7
W
V
IN
= 0 V, I
IN
= 30 mA
4.5
4
7
V
IN
= 2.4 V, I
IN
= 15 mA
4.5
8
15
V
IN
= 2.4 V, I
IN
= 15 mA
4.0
11
20
I
CC
Quiescent Supply Current
V
IN
= V
CC
or GND, I
OUT
= 0
5.5
3
m
A
D
I
CC
Increase In I
CC
per Input
One input at 3.4 V, Other inputs at V
CC
or GND
5.5
2.5
mA
*Typical values are at V
CC
= 5.0 V and T
A
= 25
_
C.
6. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower
of the voltages on the two (A or B) pins.
AC ELECTRICAL CHARACTERISTICS
T
A
=
*
40
_
C to
)
85
_
C
C
L
= 50 pF, RU = RD = 500
W
V
CC
= 4.5-5.5 V
V
CC
= 4.0 V
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
PHL
, t
PLH
Prop Delay Bus to Bus (Note 7)
V
I
= OPEN
0.25
0.25
ns
Prop Delay, Select to Bus A
1.0
5.3
6.3
t
PZH
, t
PZL
Output Enable Time, Select to Bus B
V
I
= 7 V for t
PZL
1.0
5.3
6.0
ns
Output Enable Time, I
OE
to Bus A, B
V
I
= OPEN for t
PZH
1.0
5.3
6.2
t
PHZ
, t
PLZ
Output Disable Time, Select to Bus B
V
I
= 7 V for t
PLZ
1.0
5.8
6.2
ns
Output Disable Time, I
OE
to Bus A, B
V
I
= OPEN for t
PHZ
1.0
5.5
6.2
7. This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the
typical On resistance of the switch and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
CAPACITANCE (Note 8)
Symbol
Parameter
Conditions
Typ
Max
Unit
C
IN
Control Pin Input Capacitance
V
CC
= 5.0 V
3
pF
C
I/O
A Port Input/Output Capacitance
V
CC
, OE = 5.0 V
13
pF
C
I/O
B Port Input/Output Capacitance
V
CC
, OE = 5.0 V
5
pF
8. T
A
=
)
25
_
C, f = 1 MHz, Capacitance is characterized but not tested.
74FST3253
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5
V
I
V
OL
V
OL
+ 0.3 V
t
PLH
t
PLH
V
OL
V
OH
V
OH
- 0.3 V
t
PHZL
t
f
= 2.5 nS
90 %
1.5 V
10 %
10 %
1.5 V
90 %
t
f
= 2.5 nS
t
PZL
t
PZL
OUTPUT
1.5 V
OUTPUT
1.5 V
GND
3.0 V
t
PZH
ENABLE
INPUT
t
f
= 2.5 nS
90 %
1.5 V
1.5 V
90 %
10 %
10 %
1.5 V
1.5 V
V
OH
GND
3.0 V
SWITCH
INPUT
t
f
= 2.5 nS
C
L
*
FROM
OUTPUT
UNDER
TEST
Figure 4. AC Test Circuit
Figure 5. Propagation Delays
AC Loading and Waveforms
NOTES:
1. Input driven by 50
W
source terminated in 50
W
.
2. CL includes load and stray capacitance.
*C
L
= 50 pF
500
W
500
W
Figure 6. Enable/Disable Delays
OUTPUT
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6
PACKAGE DIMENSIONS
SOIC-16
D SUFFIX
CASE 751B-05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
-B-
-A-
M
0.25 (0.010)
B
S
-T-
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
TSSOP-16
DT SUFFIX
CASE 948F-01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
---
1.20
---
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.18
0.28
0.007
0.011
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
_
_
_
_
SECTION N-N
SEATING
PLANE
IDENT.
PIN 1
1
8
16
9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
DETAIL E
F
M
L
2X
L/2
-U-
S
U
0.15 (0.006) T
S
U
0.15 (0.006) T
S
U
M
0.10 (0.004)
V
S
T
0.10 (0.004)
-T-
-V-
-W-
0.25 (0.010)
16X REF
K
N
N
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7
PACKAGE DIMENSIONS
QSOP-16
QS SUFFIX
CASE 492-01
ISSUE O
MAX
MILLIMETERS
G
R
-B-
-A-
L
M
0.25 (0.010)
T
U
-T-
SEATING
PLANE
K
D
16 PL
C
M
0.25 (0.010)
T B
A
S
S
V
N
J
M
F
8 PL
DETAIL E
DETAIL E
H x 45
_
RAD.
MOLD PIN
DIM
MIN
MAX
MIN
INCHES
A
4.80
4.98
0.189
0.196
B
3.81
3.99
0.150
0.157
C
1.55
1.73
0.061
0.068
D
0.20
0.31
0.008
0.012
F
0.41
0.89
0.016
0.035
G
0.64 BSC
0.025 BSC
H
0.20
0.46
0.008
0.018
J
0.249
0.191
0.0098 0.0075
K
0.10
0.25
0.004
0.010
L
5.84
6.20
0.230
0.244
M
0
8
0
8
N
0
7
0
7
P
0.18
0.28
0.007
0.011
Q
0.51 DIA
0.020 DIA
R
0.64
0.89
0.025
0.035
U
0.64
0.89
0.025
0.035
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
_
_
_
_
0
8
0
_
_
_
8
_
_
_
_
_
MARK
Q
P
0.013 X 0.005
DP. MAX
RAD.
0.005-0.010
TYP
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8
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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USA/Canada
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Phone: 81-3-5773-3850
74FST3253/D
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