Semiconductor Components Industries, LLC, 1999
December, 1999 Rev. 6
1
Publication Order Number:
SN74LS175/D
SN74LS175
Quad D Flip-Flop
The LSTTL / MSI SN74LS175 is a high speed Quad D Flip-Flop.
The device is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D inputs is
stored during the LOW to HIGH clock transition. Both true and
complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when
LOW.
The LS175 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Clock to Output Delays of 30 ns
Asynchronous Common Reset
True and Complement Output
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
4.75
5.0
5.25
V
T
A
Operating Ambient
Temperature Range
0
25
70
C
I
OH
Output Current High
0.4
mA
I
OL
Output Current Low
8.0
mA
LOW
POWER
SCHOTTKY
Device
Package
Shipping
ORDERING INFORMATION
SN74LS175N
16 Pin DIP
2000 Units/Box
SN74LS175D
16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS175
http://onsemi.com
2
CONNECTION DIAGRAM DIP (TOP VIEW)
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs
Complemented Outputs
D
0
D
3
CP
MR
Q
0
Q
3
Q
0
Q
3
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA HIGH/1.6 mA LOW.
HIGH
LOW
(Note a)
LOADING
PIN NAMES
LOGIC DIAGRAM
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
LOGIC SYMBOL
V
CC
= PIN 16
GND = PIN 8
12
1
2
3
6
7
11
14 15
10
4
5
13
9
CP
D
0
D
1
D
2
D
3
MR
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
D Q
CP
C
D
Q
CP D
3
D
2
D
1
D
0
Q
3
Q
3
Q
2
Q
2
Q
1
Q
1
Q
0
Q
0
D Q
CP
C
D
Q
MR
14
1
2
6
7
3
4
5
9
11
12
10
13
15
D Q
CP
C
D
Q
D Q
CP
C
D
Q
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
V
CC
MR
Q
3
Q
3
D
3
D
2
Q
2
Q
2
CP
Q
0
Q
0
D
0
D
1
Q
1
Q
1
GND
SN74LS175
http://onsemi.com
3
FUNCTIONAL DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW to HIGH Clock
(CP) transition, causing individual Q and Q outputs to
follow. A LOW input on the Master Reset (MR) will force
all Q outputs LOW and Q outputs HIGH independent of
Clock or Data inputs.
The LS175 is useful for general logic applications where
a common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H)
Outputs (t = n+1) Note 1
D
Q
Q
L
L
H
H
H
L
Note 1: t = n + 1 indicates conditions after next clock.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
V
IH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage
0.65
1.5
V
V
CC
= MIN, I
IN
= 18 mA
V
OH
Output HIGH Voltage
2.7
3.5
V
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
V
O
Output LOW Voltage
0.25
0.4
V
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
V
OL
Output LOW Voltage
0.35
0.5
V
I
OL
= 8.0 mA
V
IN
= V
IL
or V
IH
per Truth Table
I
Input HIGH Current
20
A
V
CC
= MAX, V
IN
= 2.7 V
I
IH
Input HIGH Current
0.1
mA
V
CC
= MAX, V
IN
= 7.0 V
I
IL
Input LOW Current
0.4
mA
V
CC
= MAX, V
IN
= 0.4 V
I
OS
Short Circuit Current (Note 1)
20
100
mA
V
CC
= MAX
I
CC
Power Supply Current
18
mA
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
SN74LS175
http://onsemi.com
4
AC CHARACTERISTICS
(T
A
= 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
f
MAX
Maximum Input Clock Frequency
30
40
MHz
t
PLH
t
PHL
Propagation Delay, MR to Output
20
20
30
30
ns
V
CC
= 5.0 V
C
L
= 15 pF
t
PLH
t
PHL
Propagation Delay, Clock to Output
13
16
25
25
ns
C
L
15 F
AC SETUP REQUIREMENTS
(T
A
= 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
t
W
Clock or MR Pulse Width
20
ns
t
s
Data Setup Time
20
ns
V
CC
= 5 0 V
t
h
Data Hold Time
5.0
ns
V
CC
= 5.0 V
t
rec
Recovery Time
25
ns
AC WAVEFORMS
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
1.3 V
1.3 V
1.3 V
Q
Q
t
PLH
t
PLH
t
PHL
1.3 V
*The shaded areas indicate when the input is permitted to
*
change for predictable output performance.
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1/f
max
t
w
t
s(H)
t
h(H)
t
s(L)
t
h(L)
CP
t
PHL
t
PLH
t
W
t
PHL
CP
t
rec
Q
MR
D
Q
*
1.3 V
1.3 V
DEFINITIONS OF TERMS
SETUP TIME (t
s
) -- is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) -- is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) -- is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
SN74LS175
http://onsemi.com
5
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1
8
9
16
K
PLANE
T
M
A
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.740
0.770
18.80
19.55
B
0.250
0.270
6.35
6.85
C
0.145
0.175
3.69
4.44
D
0.015
0.021
0.39
0.53
F
0.040
0.70
1.02
1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J
0.008
0.015
0.21
0.38
K
0.110
0.130
2.80
3.30
L
0.295
0.305
7.50
7.74
M
0
10
0
10
S
0.020
0.040
0.51
1.01
_
_
_
_
SN74LS175
http://onsemi.com
6
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
B
A
M
0.25 (0.010)
B
S
T
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
SN74LS175
http://onsemi.com
7
Notes
SN74LS175
http://onsemi.com
8
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
ASIA/PACIFIC: LDC for ON Semiconductor Asia Support
Phone:
3036752121 (TueFri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong 80044223781
Email: ONlitasia@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4321 NishiGotanda, Shinagawaku, Tokyo, Japan 1418549
Phone: 81354878345
Email: r14153@onsemi.com
Fax Response Line:
3036752167
8003443810 Toll Free USA/Canada
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
SN74LS175/D
North America Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 8002829855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor European Support
German Phone: (+1) 3033087140 (MF 2:30pm to 5:00pm Munich Time)
Email: ONlitgerman@hibbertco.com
French Phone: (+1) 3033087141 (MF 2:30pm to 5:00pm Toulouse Time)
Email: ONlitfrench@hibbertco.com
English Phone: (+1) 3033087142 (MF 1:30pm to 5:00pm UK Time)
Email: ONlit@hibbertco.com
PDF 
ZIP