Semiconductor Components Industries, LLC, 1999
December, 1999 Rev. 6
1
Publication Order Number:
SN74LS195A/D
SN74LS195A
Universal 4-Bit
Shift Register
The SN74LS195A is a high speed 4-Bit Shift Register offering
typical shift frequencies of 39 MHz. It is useful for a wide variety of
register and counting applications. It utilizes the Schottky diode
clamped process to achieve high speeds and is fully compatible with
all ON Semiconductor TTL products.
Typical Shift Right Frequency of 39 MHz
Asynchronous Master Reset
J, K Inputs to First Stage
Fully Synchronous Serial or Parallel Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
4.75
5.0
5.25
V
T
A
Operating Ambient
Temperature Range
0
25
70
C
I
OH
Output Current High
0.4
mA
I
OL
Output Current Low
8.0
mA
LOW
POWER
SCHOTTKY
Device
Package
Shipping
ORDERING INFORMATION
SN74LS195AN
16 Pin DIP
2000 Units/Box
SN74LS195AD
16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS195A
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Parallel Enable (Active LOW) Input
Parallel Data Inputs
First Stage J (Active HIGH) Input
First Stage K (Active LOW) Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs
Complementary Last Stage Output
PE
P
0
P
3
J
K
CP
MR
Q
0
Q
3
Q
3
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
mA HIGH/1.6 mA LOW.
HIGH
LOW
(Note a)
LOADING
PIN NAMES
LOGIC SYMBOL
2
10
3
4
5
6
7
11
12
13
14
15
1
9
J
PE
CP
K
MR
P
0
P
1
P
2
P
3
Q
0
Q
1
Q
2
Q
3
Q
3
V
CC
= PIN 16
GND = PIN 8
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
V
CC
MR
Q
0
Q
1
Q
2
Q
3
CP
Q
3
PE
J
K
P
0
P
1
P
2
P
3
GND
SN74LS195A
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3
LOGIC DIAGRAM
J
P
0
P
1
P
2
P
3
CP
PE
K
MR
Q
0
Q
0
Q
1
Q
3
R
CP
S
C
D
Q
0
Q
2
Q
3
14
1
2
6
7
3
4
5
9
11
12
10
13
15
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
R
CP
S
C
D
Q
0
R
CP
S
C
D
Q
2
Q
3
R
CP
S
C
D
Q
3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS195A 4-Bit Shift
Register. The device is useful in a wide variety of shifting,
counting and storage applications. It performs serial,
parallel, serial to parallel, or parallel to serial data transfers
at very high speeds.
The LS195A has two primary modes of operation, shift
right (Q
0
Q
1
) and parallel load which are controlled by the
state of the Parallel Enable (PE) input. When the PE input is
HIGH, serial data enters the first flip-flop Q
0
via the J and
K inputs and is shifted one bit in the direction Q
0
Q
1
Q
2
Q
3
following each LOW to HIGH clock transition.
The JK inputs provide the flexibility of the JK type input for
special applications, and the simple D type input for general
applications by tying the two pins together. When the PE
input is LOW, the LS195A appears as four common clocked
D flip-flops. The data on the parallel inputs P
0
, P
1
, P
2
, P
3
is
transferred to the respective Q
0
, Q
1
, Q
2
, Q
3
outputs
following the LOW to HIGH clock transition. Shift left
operations (Q
3
Q
2
) can be achieved by tying the Q
n
Outputs to the P
n1
inputs and holding the PE input LOW.
All serial and parallel data transfers are synchronous,
occurring after each LOW to HIGH clock transition. Since
the LS195A utilizes edge-triggering, there is no restriction
on the activity of the J, K, P
n
and PE inputs for logic
operation -- except for the set-up and release time
requirements.
A LOW on the asynchronous Master Reset (MR) input
sets all Q outputs LOW, independent of any other input
condition.
MODE SELECT -- TRUTH TABLE
OPERATING MODES
INPUTS
OUTPUTS
OPERATING MODES
MR
PE
J
K
P
n
Q
0
Q
1
Q
2
Q
3
Q
3
Asynchronous Reset
L
X
X
X
X
L
L
L
L
H
Shift, Set First Stage
H
h
h
h
X
H
q
0
q
1
q
2
q
2
Shift, Reset First
H
h
I
I
X
L
q
0
q
1
q
2
q
2
Shift, Toggle First Stage
H
h
h
I
X
q
0
q
0
q
1
q
2
q
2
Shift, Retain First Stage
H
h
I
h
X
q
0
q
0
q
1
q
2
q
2
Parallel Load
H
I
X
X
p
n
p
0
p
1
p
2
p
3
p
3
L = LOW voltage levels
H = HIGH voltage levels
X = Don't Care
I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.
h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.
p
n
(q
n
) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to
HIGH clock transition.
SN74LS195A
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4
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
V
IH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage
0.65
1.5
V
V
CC
= MIN, I
IN
= 18 mA
V
OH
Output HIGH Voltage
2.7
3.5
V
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
V
O
Output LOW Voltage
0.25
0.4
V
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
V
OL
Output LOW Voltage
0.35
0.5
V
I
OL
= 8.0 mA
V
IN
= V
IL
or V
IH
per Truth Table
I
Input HIGH Current
20
A
V
CC
= MAX, V
IN
= 2.7 V
I
IH
Input HIGH Current
0.1
mA
V
CC
= MAX, V
IN
= 7.0 V
I
IL
Input LOW Current
0.4
mA
V
CC
= MAX, V
IN
= 0.4 V
I
OS
Short Circuit Current (Note 1)
20
100
mA
V
CC
= MAX
I
CC
Power Supply Current
21
mA
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(T
A
= 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
f
MAX
Maximum Clock Frequency
30
39
MHz
t
PLH
t
PHL
Propagation Delay,
Clock to Output
14
17
22
26
ns
V
CC
= 5.0 V
C
L
= 15 pF
t
PHL
Propagation Delay,
MR to Output
19
30
ns
C
L
15 F
AC SETUP REQUIREMENTS
(T
A
= 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
t
W
CP Clock Pulse Width
16
ns
t
W
MR Pulse Width
12
ns
t
s
PE Setup Time
25
ns
t
s
Data Setup Time
15
ns
V
CC
= 5.0 V
t
rec
Recovery Time
25
ns
t
rel
PE Release Time
10
ns
t
h
Data Hold Time
0
ns
SN74LS195A
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5
DEFINITIONS OF TERMS
SETUP TIME(t
s
) --is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) -- is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) -- is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays and
Clock Pulse Width
Figure 2. Master Reset Pulse Width, Master Reset
to Output Delay and Master Reset to Clock
Recovery Time
CONDITIONS: MR = H
*Q
0
STATE WILL BE DETERMINED BY J AND K INPUTS.
1.3 V
1.3 V
1.3 V
1.3 V
CLOCK
OUTPUT
PE
Q
n
= P
n
Q
n
* = Q
n1
t
rel
t
rel
t
s
(L)
t
s
(H)
LOAD PARALLEL DATA
LOAD SERIAL DATA
SHIFT RIGHT
1.3 V
CONDITIONS: PE = L
PO = P
1
= P
2
= P
3
= H
CONDITIONS: MR = H
*J AND K SETUP TIME AFFECTS Q
0
ONLY
PE
J & K
P
0
P
1
P
2
P
3
CLOCK
OUTPUT*
CLOCK
CLOCK
OUTPUT
OUTPUT
t
s
(H)
t
h
(L) = 0
t
h
(H) = 0
t
h
(H) = 0
t
s
(H)
t
h
(L) = 0
t
s
(L)
t
PHL
t
PLH
t
s
(L)
MR
t
rec
t
PHL
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
t
W
CONDITIONS: J = PE = MR = H
K = L
t
W
1.3 V
Figure 3. Setup (t
s
) and Hold (t
h
) Time for Serial Data
(J & K) and Parallel Data (P
0
, P
1
, P
2
, P
3
)
Figure 4. Setup (t
s
) and Hold (t
h
) Time for PE Input
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