Semiconductor Components Industries, LLC, 2001
April, 2001 Rev. 6
1
Publication Order Number:
CS1124/D
CS1124
Dual Variable-Reluctance
Sensor Interface IC
The CS1124 is a monolithic integrated circuit designed primarily to
condition signals used to monitor rotating parts.
The CS1124 is a dual channel device. Each channel interfaces to a
Variable Reluctance Sensor, and monitors the signal produced when a
metal object is moved past that sensor. An output is generated that is a
comparison of the input voltage and the voltage produced at the IN
Adj
lead. The resulting squarewave is available at the OUT pin.
When the DIAG pin is high, the reference voltage at IN
Adj
is
increased. This then requires a larger signal at the input to trip the
comparator, and provides for a procedure to test for an open sensor.
Features
Dual Channel Capability
BuiltIn Test Mode
OnChip Input Voltage Clamping
Works from 5.0 V Supply
Accurate BuiltIn Hysteresis
Figure 1. Block Diagram
OUT1
To
P
V
CC
V
CC
V
CC
V
CC
V
CC
INP1
IN
Adj
DIAG
IN1
C1
R1
R
RS
V
RS
Variable
Reluctance
Sensor
+
COMP1
Active
Clamp
V
CC
V
CC
INP2
IN2
C2
R2
R
RS
V
RS
Variable
Reluctance
Sensor
+
COMP2
Active
Clamp
OUT2
To
P
R
Adj
GND
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Device
Package
Shipping
ORDERING INFORMATION
CS1124YD8
SO8
95 Units/Rail
CS1124YDR8
SO8
2500 Tape & Reel
SO8
D SUFFIX
CASE 751
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
DIAG
GND
1
1
124
AL
YW
8
OUT2
IN2
OUT1
IN1
V
CC
IN
Adj
PIN CONNECTIONS AND
MARKING DIAGRAM
1
8
CS1124
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2
MAXIMUM RATINGS*
Rating
Value
Unit
Storage Temperature Range
65 to 150
C
Ambient Operating Temperature
40 to 125
C
Supply Voltage Range (continuous)
0.3 to 7.0
V
Input Voltage Range (at any input, R1 = R2 = 22 k)
250 to 250
V
Maximum Junction Temperature
150
C
ESD Susceptibility (Human Body Model)
2.0
kV
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
230 peak
C
1. 60 second maximum above 183
C.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS
(4.5 V < V
CC
< 5.5 V, 40
C < T
A
< 125
C, V
DIAG
= 0; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
V
CC
SUPPLY
Operating Current Supply
V
CC
= 5.0 V
5.0
mA
Sensor Inputs
Input Threshold Positive
V
DIAG
= Low
V
DIAG
= High
135
135
160
160
185
185
mV
mV
Input Threshold Negative
V
DIAG
= Low
V
DIAG
= High
185
135
160
160
135
185
mV
mV
Input Bias Current (INP1, INP2)
V
IN
= 0.336 V
16
11
6.0
A
Input Bias Current (DIAG)
V
DIAG
= 0 V
1.0
A
Input Bias Current Factor (K
I
)
(IN
Adj
= INP
K
I
)
V
IN
= 0.336 V, V
DIAG
= Low
V
IN
= 0.336 V, V
DIAG
= High
152
100
155
157
%INP
%INP
Bias Current Matching
INP1 or INP2 to IN
Adj
, V
IN
= 0.336 V
1.0
0
1.0
A
Input Clamp Negative
I
IN
= 50
A
I
IN
= 12 mA
0.5
0.5
0.25
0.30
0
0
V
V
Input Clamp Positive
I
IN
= +12 mA
5.0
7.0
9.0
V
Output Low Voltage
I
OUT
= 1.6 mA
0.2
0.4
V
Output High Voltage
I
OUT
= 1.6 mA
V
CC
0.5
V
CC
0.2
V
Mode Change Time Delay
0
20
s
Input to Output Delay
I
OUT
= 1.0 mA
1.0
20
s
Output Rise Time
C
LOAD
= 30 pF
0.5
2.0
s
Output Fall Time
C
LOAD
= 30 pF
0.05
2.0
s
OpenSensor Positive Threshold
V
DIAG
= High, R
IN(Adj)
= 40 k. Note 2
29.4
54
86.9
k
Logic Inputs
DIAG Input Low Threshold
0.2
V
CC
V
DIAG Input High Threshold
0.7
V
CC
V
DIAG Input Resistance
V
IN
= 0.3
V
CC
, V
CC
= 5.0 V
V
IN
= V
CC
, V
CC
= 5.0 V
8.0
8.0
22
22
70
70
k
k
2. This parameter is guaranteed by design, but not parametrically tested in production.
CS1124
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3
PACKAGE PIN DESCRIPTION*
PACKAGE PIN #
SO8
PIN SYMBOL
FUNCTION
1
IN
Adj
External resistor to ground that sets the trip levels of both channels.
Functions for both diagnostic and normal mode.
2
IN1
Input to channel 1.
3
IN2
Input to channel 2.
4
GND
Ground.
5
DIAG
Diagnostic mode switch. Normal mode is low.
6
OUT2
Output of channel 2.
7
OUT1
Output of channel 1.
8
V
CC
Positive 5.0 volt supply input.
OUT1
To
P
V
CC
V
CC
V
CC
V
CC
V
CC
INP1
IN
Adj
DIAG
IN1
C1
R1
R
RS
V
RS
Variable
Reluctance
Sensor
+
COMP1
Active
Clamp
R
Adj
GND
Figure 2. Application Diagram
THEORY OF OPERATION
NORMAL OPERATION
Figure 2 shows one channel of the CS1124 along with the
necessary external components. Both channels share the
IN
Adj
pin as the negative input to a comparator. A brief
description of the components is as follows:
V
RS
Ideal sinusoidal, ground referenced, sensor output
amplitude usually increases with frequency, depending on
loading.
R
RS
Source impedance of sensor.
R1/R
Adj
External resistors for current limiting and
biasing.
INP1/IN
Adj
Internal current sources that determine trip
points via R1/R
Adj
.
COMP1 Internal comparator with builtin hysteresis
set at 160 mV.
OUT1 Output 0 V 5.0 V square wave with the same
frequency as V
RS
.
By inspection, the voltage at the (+) and () terminals of
COMP1 with V
RS
= 0V are:
V+
+
INP1(R1
)
RRS)
(1)
CS1124
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4
V
+
INAdj
RAdj
(2)
As V
RS
begins to rise and fall, it will be superimposed on
the DC biased voltage at V
+
.
V+
+
INP1(R1
)
RRS)
)
VRS
(3)
To get comparator COMP1 to trip, the following
condition is needed when crossing in the positive direction,
V+
u
V
)
VHYS
(4)
(V
HYS
is the builtin hysteresis set to 160 mV), or when
crossing in the negative direction,
V+
t
V
*
VHYS
(5)
Combining equations 2, 3, and 4, we get:
INP1(R1
)
RRS)
)
VRS
u
INAdj
RAdj
)
VHYS
(6)
therefore,
VRS(+TRP)
t
INAdj
RAdj
*
INP1(R1
)
RRS)
)
VHYS
(7)
It should be evident that tripping on the negative side is:
VRS(TRP)
t
INAdj
RAdj
*
INP1(R1
)
RRS)
*
VHYS
(8)
In normal mode,
INP1
+
INAdj
(9)
We can now rewrite equation (7) as:
VRS(+TR)
u
INP1(RAdj
*
R1
*
RRS)
)
VHYS
(10)
By making
RAdj
+
R1
)
RRS
(11)
you can detect signals with as little amplitude as V
HYS
.
A design example is given in the applications section.
OPEN SENSOR PROTECTION
The CS1124 has a DIAG pin that when pulled high (5.0 V),
will increase the IN
Adj
current source by roughly 50%.
Equation (7) shows that a larger V
RS(+TRP)
voltage will be
needed to trip comparator COMP1. However, if no V
RS
signal is present, then we can use equations 1, 2, and 4
(equation 5 does not apply in this mode) to get:
INP1(R1
)
RRS)
u
INP1
KI
RAdj
)
VHYS
(12)
Since R
RS
is the only unknown variable we can solve for
R
RS
,
RRS
+
INP1
KI
RAdj
)
VHYS
INP1
*
R1
(13)
Equation (13) shows that if the output switches states
when entering the diag mode with V
RS
= 0, the sensor
impedance must be greater than the above calculated value.
This can be very useful in diagnosing intermittent sensor.
INPUT PROTECTION
As shown in Figure 2, an active clamp is provided on each
input to limit the voltage on the input pin and prevent
substrate current injection. The clamp is specified to handle
12 mA. This puts an upper limit on the amplitude of the
sensor output. For example, if R1 = 20 k, then
VRS(MAX)
+
20 k
12 mA
+
240 V
Therefore, the V
RS(pkpk)
voltage can be as high as 480 V.
The CS1124 will typically run at a frequency up to 1.8 MHz
if the input signal does not activate the positive or negative
input clamps. Frequency performance will be lower when
the positive or negative clamps are active. Typical
performance will be up to a frequency of 680 kHz with the
clamps active.
CS1124
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5
CIRCUIT DESCRIPTION
Figure 3 shows the part operating near the minimum input
thresholds. As the sin wave input threshold is increased, the
low side clamps become active (Figure 4). Increasing the
amplitude further (Figure 5), the highside clamp becomes
active. These internal clamps allow for voltages up to 250 V
and 250 V on the sensor side of the setup (with R1 = R2 =
22 k) (reference the diagram page 1).
Figure 6 shows the effect using the diagnostic (DIAG)
function has on the circuit. The input threshold (negative) is
switched from a threshold of 160 mV to +160 mV when
DIAG goes from a low to a high. There is no hysteresis when
DIAG is high.
Figure 3. Minimum Threshold Operation
IN1, 200 mV/div
OUT1, 2.0 V/div
20 ms/div
Figure 4. LowSide Clamp
IN1, 5.0 V/div
OUT1, 2.0 V/div
20 ms/div
Figure 5. Low and HighSide Clamps
IN1, 5.0 V/div
OUT1, 2.0 V/div
20 ms/div
Figure 6. Diagnostic Operation
DIAG
5.0 V/div
20 ms/div
IN1
1.0 V/div
OUT1
5.0 V/div
CS1124
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6
APPLICATION INFORMATION
Referring to Figure 2, the following will be a design
example given these system requirements:
RRS
+
1.5 k
W
(
u
12 k
W
is considered open)
VRS(MAX)
+
120 Vpk
VRS(MIN)
+
250 mVpk
FVRS
+
10 kHz @ VRS(MIN)
+
40 Vpkpk
1. Determine tradeoff between R1 value and power
rating. (use 1/2 watt package)
PD
+
120
2
2
R1
t
1 2 W
Set R1 = 15 k. (The clamp current will then be 120/15 k
= 8.0 mA, which is less than the 12 mA limit.)
2. Determine R
Adj
Set R
Adj
as close to R1 + R
RS
as possible.
Therefore, R
Adj
= 17 k.
3. Determine V
RS(+TRP)
using equation (7).
VRS(+TRP)
+
11
m
A
17k
*
11
m
A(15k
)
1.5k)
)
160 mV
VRS(+TRP)
+
166 mV typical
(easily meets 250 mV minimum)
4. Calculate worst case V
RS(+TRP)
Examination of equation (7) and the spec reveals the worst
case trip voltage will occur when:
V
HYS
= 180 mV
IN
Adj
= 16
A
INP1 = 15
A
R1 = 14.25 k (5% low)
R
Adj
= 17.85 k (5% High)
VRS(+)MAX
+
16
m
A(17.85 k)
*
15
m
A(14.25 k
)
1.5 k)
)
180 mV
+
229 mV
which is still less than the 250 mV minimum amplitude of
the input.
5. Calculate C1 for low pass filtering
Since the sensor guarantees 40 V
pkpk
@ 10 kHz, a low
pass filter using R1 and C1 can be used to eliminate high
frequency noise without affecting system performance.
Gain Reduction
+
0.29 V
20 V
+
0.0145
+ *
36.7 dB
Therefore, a cutoff frequency, f
C
, of 145 Hz could be
used.
C1
v
1
2
p
fCR1
v
0.07
m
F
Set C1 = 0.047
F.
6. Calculate the minimum R
RS
that will be indicated as
an open circuit. (DIAG = 5.0 V)
Rearranging equation (7) gives
RRS
+
VHYS
)
[INP1
KI
RAdj]
*
VRS(+TRP)
INP1
*
R1
But, V
RS
= 0 during this test, so it drops out.
Using the following as worst case Low and High:
Worst Case Low (R
RS
)
Worst Case High (R
RS
)
IN
Adj
23.6
A = 15
A
1.57
10.7
A = 7.0
A
1.53
R
Adj
16.15 k
17.85 k
V
HYS
135 mV
185 mV
INP1
16
A
6.0
A
R1
15.75 k
14.25 k
K
I
1.57
1.53
RRS
+
135 mV
)
23.6
m
A
16.15 k
16
m
A
*
15.75 k
+
16.5 k
Therefore,
RRS(MIN)
+
16.5 k (meets 12 k system spec)
and,
RRS(MAX)
+
185 mV
)
10.7
m
A
17.85 k
6.0
m
A
*
14.25 k
+
48.4 k
CS1124
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7
PACKAGE DIMENSIONS
SO8
D SUFFIX
CASE 75107
ISSUE V
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
B
S
D
H
C
0.10 (0.004)
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010)
Z
S
X
S
M
PACKAGE THERMAL DATA
Parameter
SO8
Unit
R
JC
Typical
45
C/W
R
JA
Typical
165
C/W
CS1124
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8
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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Phone: 81357402700
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For additional information, please contact your local
Sales Representative.
CS1124/D
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