Semiconductor Components Industries, LLC, 2002
December, 2001 Rev. 9
1
Publication Order Number:
CS51031/D
CS51031
Fast PFET Buck Controller
The CS51031 is a switching controller for use in DCDC
converters. It can be used in the buck topology with a minimum
number of external components. The CS51031 consists of a V
CC
monitor for controlling the state of the device, 1.0 A power driver for
controlling the gate of a discrete Pchannel transistor, fixed frequency
oscillator, short circuit protection timer, programmable soft start,
precision reference, fast output voltage monitoring comparator, and
output stage driver logic with latch.
The high frequency oscillator allows the use of small inductors and
output capacitors, minimizing PC board area and systems cost. The
programmable soft start reduces current surges at start up. The short
circuit protection timer significantly reduces the duty cycle to
approximately 1/30 of its cycle during short circuit conditions.
The CS51031 is available in an 8 Lead SO plastic package.
Features
1.0 A Totem Pole Output Driver
High Speed Oscillator (700 kHz max)
No Stability Compensation Required
Lossless Short Circuit Protection
V
CC
Monitor
2.0% Precision Reference
Programmable Soft Start
Wide Ambient Temperature Range:
Industrial Grade: 40
C to 85
C
Commercial Grade: 0
C to 70
C
V
GATE
PGND
C
OSC
GND
V
C
CS
V
CC
V
FB
CS51031
RV
CC
100
CV
CC
0.1
F
CS
0.1
F
C
OSC
470 pF
V
GATE
R
A
1.5 k
R
B
2.5 k
C
RR
0.1
F
C
O
100
F
2
V
O
3.3 V @ 3 A
L
4.7
H
MBRS360
D
1
5.0 V12 V
C
IN
47
F
MP
1
IRF7416
Figure 1. Typical Application Diagram
95 Units/Rail
PIN CONNECTIONS
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
SO8
D SUFFIX
CASE 751
1
8
1
51031
ALYW
8
MARKING
DIAGRAM
V
FB
GND
V
CC
C
OSC
CS
PGND
V
C
V
GATE
1
Device
Package
Shipping
ORDERING INFORMATION*
CS51031YD8
SO8
95 Units/Rail
CS51031YDR8
2500 Tape & Reel
CS51031GD8
CS51031GDR8
2500 Tape & Reel
SO8
SO8
SO8
*Additional ordering information can be found on
page 9 of this data sheet.
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2
MAXIMUM RATINGS*
Rating
Value
Unit
Power Supply Voltage, V
CC
20
V
Driver Supply Voltage, V
C
20
V
Driver Output Voltage, V
GATE
20
V
C
OSC
, CS, V
FB
(Logic Pins)
6.0
V
Peak Output Current
1.0
A
Steady State Output Current
200
mA
Operating Junction Temperature, T
J
150
C
Operating Temperature Range, T
A
40 to 85
C
Storage Temperature Range, T
S
65 to 150
C
ESD (Human Body Model)
2.0
kV
Lead Temperature Soldering:
Wave Solder: (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
260 peak
230 peak
C
C
1. 10 sec. maximum.
2. 60 sec. max above 183
C.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS
(Specifications apply for 4.5
V
CC
16 V, 3.0 V
V
C
16 V;
Industrial Grade: 40
C < T
A
< 85
C; 40
C < T
J
< 125
C: Commercial Grade: 0
C < T
A
< 70
C; 0
C < T
J
< 125
C, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Oscillator
V
FB
= 1.2 V
Frequency
C
OSC
= 470 pF
160
200
240
kHz
Charge Current
1.4 V < V
COSC
< 2.0 V
110
A
Discharge Current
2.7 V > V
COSC
> 2.0 V
660
A
Maximum Duty Cycle
1 (t
OFF
/t
ON
)
80.0
83.3
%
Short Circuit Timer
V
FB
= 1.0 V; CS = 0.1
m
F; V
COSC
= 2.0 V
Charge Current
1.0 V < V
CS
< 2.0 V
175
264
325
A
Fast Discharge Current
2.55 V > V
CS
> 2.4 V
40
66
80
A
Slow Discharge Current
2.4 V > V
CS
> 1.5 V
4.0
6.0
10
A
Start Fault Inhibit Time
0 V < V
CS
< 2.5 V
0.70
0.85
1.40
ms
Valid Fault Time
2.6 V > V
CS
> 2.4 V
0.2
0.3
0.45
ms
GATE Inhibit Time
2.4 V > V
CS
> 1.5 V
9.0
15
23
ms
Fault Duty Cycle
2.5
3.1
4.6
%
CS Comparator
V
FB
= 1.0 V
Fault Enable CS Voltage
2.5
V
Max. CS Voltage
V
FB
= 1.5 V
2.6
V
Fault Detect Voltage
V
CS
when GATE goes high
2.4
V
Fault Inhibit Voltage
Minimum V
CS
1.5
V
Hold Off Release Voltage
V
FB
= 0 V
0.4
0.7
1.0
V
Regulator Threshold Voltage Clamp
V
CS
= 1.5 V
0.725
0.866
1.035
V
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3
ELECTRICAL CHARACTERISTICS (continued)
(Specifications apply for 4.5
V
CC
16 V, 3.0 V
V
C
16 V;
Industrial Grade: 40
C < T
A
< 85
C; 40
C < T
J
< 125
C: Commercial Grade: 0
C < T
A
< 70
C; 0
C < T
J
< 125
C, unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
V
FB
Comparators
V
COSC
= V
CS
= 2.0 V
Regulator Threshold Voltage
T
J
= 25
C (Note 3)
T
J
= 40 to 125
C
1.225
1.210
1.250
1.250
1.275
1.290
V
V
Fault Threshold Voltage
T
J
= 25
C (Note 3)
T
J
= 40 to 125
C
1.12
1.10
1.15
1.15
1.17
1.19
V
V
Threshold Line Regulation
4.5 V
V
CC
16 V
6.0
15
mV
Input Bias Current
V
FB
= 0 V
1.0
4.0
A
Voltage Tracking
(Regulator Threshold Fault Threshold Voltage)
70
100
120
mV
Input Hysteresis Voltage
4.0
20
mV
Power Stage
V
CC
= V
C
= 10 V; V
FB
= 1.2 V
GATE DC Low Saturation Voltage
V
COSC
= 1.0 V; 200 mA Sink
1.2
1.5
V
GATE DC High Saturation Voltage
V
COSC
= 2.7 V; 200 mA Source; V
C
= V
GATE
1.5
2.1
V
Rise Time
C
GATE
= 1.0 nF; 1.5 V < V
GATE
< 9.0 V
25
60
ns
Fall Time
C
GATE
= 1.0 nF; 9.0 V > V
GATE
> 1.5 V
25
60
ns
V
CC
Monitor
Turn On Threshold
4.200
4.400
4.600
V
Turn Off Threshold
4.085
4.300
4.515
V
Hysteresis
65
130
200
mV
Current Drain
I
CC
4.5 V < V
CC
< 16 V, Gate switching
4.5
6.0
mA
I
C
3.0 V < V
C
< 16 V, Gate nonswitching
2.7
4.0
mA
Shutdown I
CC
V
CC
= 4.0
500
900
A
3. Guaranteed by design, not 100% tested in production.
PACKAGE LEAD DESCRIPTION
PACKAGE PIN
NUMBER
SO8
PIN SYMBOL
FUNCTION
1
V
GATE
Driver pin to gate of external PFET.
2
PGND
Output power stage ground connection.
3
C
OSC
Oscillator frequency programming capacitor.
4
GND
Logic ground.
5
V
FB
Feedback voltage input.
6
V
CC
Logic supply voltage.
7
CS
Soft start and fault timing capacitor.
8
V
C
Driver supply voltage.
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4
Q
Q
Q
Q
RG
V
C
V
GATE
PGND
R
S
F2
V
GATE
FlipFlop
G2
+
+
V
FB
Comparator
A6
V
FB
+
1.25 V
G1
+
+
0.7 V
Hold Off
Comp
+
Fault
Comp
+
1.15 V
+
A4
CS Charge
Sense
Comparator
R
S
F1
Slow Discharge
FlipFlop
+
GND
G4
G5
+
A3
Slow Discharge
Comparator
2.3 V
+
2.4 V
+
A2
CS
Comparator
+
+
2.5 V
1.5 V
I
T
55
I
T
5
I
T
CS
G3
V
REF
= 3.3 V
C
OSC
+
+
2.5 V
1.5 V
A1
V
REF
3.3 V
V
CC
OK
V
CC
Oscillator
Comparator
V
CC
V
REF
I
C
7I
C
Figure 2. Block Diagram
CIRCUIT DESCRIPTION
THEORY OF OPERATION
Control Scheme
The CS51031 monitors the output voltage to determine
when to turn on the PFET. If V
FB
falls below the internal
reference voltage of 1.25 V during the oscillator's charge
cycle, the PFET is turned on and remains on for the duration
of the charge time. The PFET gets turned off and remains off
during the oscillator's discharge time with the maximum
duty cycle to 80%. It requires 7.0 mV typical, and 20 mV
maximum ripple on the V
FB
pin is required to operate. This
method of control does not require any loop stability
compensation.
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5
Startup
The CS51031 has an externally programmable soft start
feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.
At startup, the voltage on all pins is zero. As V
CC
rises, the
V
C
voltage along with the internal resistor R
G
keeps the
PFET off. As V
CC
and V
C
continue to rise, the oscillator
capacitor (C
OSC
) and the Soft Start/Fault Timing capacitor
(CS) charges via internal current sources. C
OSC
gets charged
by the current source IC and CS gets charged by the I
T
source
combination described by:
ICS
+
IT
*
IT
55
)
IT
5
The internal Holdoff Comparator ensures that the external
PFET is off until V
CS
> 0.7 V, preventing the GATE flipflop
(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
start is obtained by clamping the V
FB
comparator's (A6)
reference input to approximately 1/2 of the voltage at the CS
pin during startup, permitting the control loop and the output
voltage to slowly increase. Once the CS pin charges above
the Holdoff Comparator trip point of 0.7 V, the low feedback
to the V
FB
Comparator sets the GATE flipflop during
C
OSC
's charge cycle. Once the GATE flipflop is set, V
GATE
goes low and turns on the PFET. When V
CS
exceeds 2.3 V,
the CS charge sense comparator (A4) sets the V
FB
comparator reference to 1.25 V completing the startup cycle.
Lossless Short Circuit Protection
The CS51031 has "lossless" short circuit protection since
there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage ) reaches
2.5 V during startup, the fault timing circuitry is enabled by
A2. During normal operation the CS voltage is 2.6 V. During
a short circuit or a transient condition, the output voltage
moves lower and the voltage at V
FB
drops. If V
FB
drops
below 1.15 V, the output of the fault comparator goes high
and the CS51031 goes into a fast discharge mode. The fault
timing capacitor, CS, discharges to 2.4 V. If the V
FB
voltage
is still below 1.15 V when the CS pin reaches 2.4 V, a valid
fault condition has been detected. The slow discharge
comparator output goes high and enables gate G5 which sets
the slow discharge flip flop. The V
GATE
flip flop resets and
the output switch is turned off. The fault timing capacitor is
slowly discharged to 1.5 V. The CS51031 then enters a
normal startup routine. If the fault is still present when the
fault timing capacitor voltage reaches 2.5 V, the fast and
slow discharge cycles repeat as shown in figure 3.
If the V
FB
voltage is above 1.15 V when CS reaches 2.4 V
a fault condition is not detected, normal operation resumes
and CS charges back to 2.6 V. This reduces the chance of
erroneously detecting a load transient as a fault condition.
Figure 3. Voltage on Start Capacitor (V
GS
), the Gate (V
GATE
), and in the
Feedback Loop (V
FB
), During Startup, Normal and Fault Conditions.
1.15 V
1.25 V
0 V
1.5 V
2.4 V
2.6 V
2.5 V
0 V
V
CS
V
GATE
V
FB
START
NORMAL OPERATION
FAULT
td1
T
START
t
FAULT
t
RESTART
td2
t
FAULT
S1
S2
S1
S2
S3
S3
S1
S2
S3
S3
0.7 V
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6
Buck Regulator Operation
A block diagram of a typical buck regulator is shown in
Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current I
L
is zero and the output voltage is at its
nominal value. The current drawn by the load is supplied by
the output capacitor C
O
. When the voltage across C
O
drops
below the threshold established by the feedback resistors R1
and R2 and the reference voltage V
REF
, the power transistor
Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(V
IN
V
OUT
)/L. The duty cycle (or "on" time) for the
CS51031 is limited to 80%. If output voltage remains higher
than nominal during the entire C
OSC
change time, the Q1
does not turn on, skipping the pulse.
Figure 4. Buck Regulator Block Diagram.
R
1
R
2
C
O
R
LOAD
L
D
1
Feedback
Control
Q
1
C
IN
V
IN
APPLICATIONS INFORMATION
CS51031 DESIGN EXAMPLE
Specifications 12 V to 5.0 V, 3.0 A Buck Controller
V
IN
= 12 V
20% (i.e. 14.4 V max., 12 V nom., 9.6 V
min.)
V
OUT
= 5.0 V
2%
I
OUT
= 0.3 A to 3.0 A
Output ripple voltage < 50 mV max.
Efficiency > 80%
f
SW
= 200 kHz
1) Duty Cycle Estimates
Since the maximum duty cycle D, of the CS51031 is
limited to 80% min., it is necessary to estimate the duty cycle
for the various input conditions over the complete operating
range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
D
+
VOUT
)
VF
VIN
*
VSAT
where:
V
SAT
= R
ds(on)
I
OUT
max. and R
ds(on)
is the value at T
J
100
C.
If V
F
= 0.60 V and V
SAT
= 0.60 V then the above equation
becomes:
DMAX
+
5.6
9.0
+
0.62
DMIN
+
5.6
13.8
+
0.40
2) Switching Frequency and On and Off Time
Calculations
Given that f
SW
= 200 kHz and D
MAX
= 0.80
T
+
1.0
fSW
+
5.0
m
s
TON(max)
+
T
DMAX
+
5.0
m
s
0.62
^
3.0
m
s
TON(min)
+
T
DMIN
+
5.0
m
s
0.40
^
2.0
m
s
TOFF(max)
+
TON(min)
+
5.0
m
s
*
2.0
m
s
+
3.0
m
s
3) Oscillator Capacitor Selection
The switching frequency is set by C
OSC
, whose value is
given by:
COSC in pF
+
95
10
)
6
FSW 1
)
FSW
3
106
*
30
103
FSW
2
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7
4) Inductor Selection
The inductor value is chosen for continuous mode
operation down to 0.3 Amps.
The ripple current
I = 2
I
OUT
min = 2
0.3 A = 0.6 A.
L min
+
(VOUT
)
VD)
TOFF(max)
D
I
+
5.6 V
3.0
m
s
0.6 A
+
28
m
H
This is the minimum value of inductor to keep the ripple
current < 0.6 A during normal operation.
A smaller inductor will result in larger ripple current.
Ripple current at a minimum off time is
D
I
+
(VOUT
)
VF)
TOFF(min)
LMIN
+
5.6 V
2.0
m
s
28
m
H
+
0.4 A
The core must not saturate with the maximum expected
current, here given by:
IMAX
+
IOUT
) D
I 2
+
3.0 A
)
0.4 A 2
+
3.2 A
5) Output Capacitor
The output capacitor and the inductor form a low pass
filter. The output capacitor should have a low ESL and ESR.
Low impedance aluminum electrolytic, tantalum or organic
semiconductor capacitors are a good choice for an output
capacitor. Low impedance aluminum are less expensive.
Solid tantalum chip capacitors are available from a number
of suppliers and are the best choice for surface mount
applications.
The output capacitor limits the output ripple voltage. The
CS51031 needs a maximum of 20 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak to peak is given by:
C
+
D
I
8.0
fSW
D
V
+
0.6 A
8.0
(200
103Hz)
(50
10
*
3 V)
+
7.5
m
F
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak to peak is:
ESR
+ D
V
D
I
+
50
10
*
3
0.6 A
+
83 m
W
The output capacitor should be chosen so that its ESR is
less than 83 m
.
During the minimum off time, the ripple current is 0.4 A
and the output voltage ripple will be:
D
V
+
ESR
D
I
+
83m
W
0.4
+
33 mV
6) V
FB
Divider
VOUT
+
1.25 V R1
)
R2
R2
+
1.25 V R1
R2
)
1.0
The input bias current to the comparator is 4.0
A. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this permits a divider current of 1mA and simplifies
the calculations.
5.0 V
1.0 mA
+
R1
)
R2
+
5.0 K
W
Let R2 = 1.0 K
Rearranging the divider equation gives:
R1
+
R2
VOUT
1.25
*
1.0
+
1.0 k
W
5.0 V
1.25
*
1.0
+
3.0 k
W
7) Divider Bypass Capacitor C
RR
Since the feedback resistors divide the output voltage by
a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0
15 mV) to trip the
feedback comparator. We use a capacitor C
RR
to act as an
AC short.
The ripple voltage frequency is equal to the switching
frequency so we choose C
RR
= 1.0 nF.
8) Soft Start and Fault Timing Capacitor CS
CS performs several important functions. First it provides
a delay time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
soft start by clamping the reference voltage during startup,
allowing it to rise slowly, and, finally it controls the hiccup
short circuit protection circuitry. This reduces the duty cycle
to approximately 0.035 during short circuit conditions.
An important consideration in calculating CS is that it's
voltage does not reach 2.5 V (the voltage at which the fault
detect circuitry is enabled) before V
FB
reaches 1.15 V
otherwise the power supply will never start.
If the V
FB
pin reaches 1.15 V, the fault timing comparator
will discharge CS and the supply will not start. For the V
FB
voltage to reach 1.15 V the output voltage must be at least
4
1.15 = 4.6 V.
If we choose an arbitrary startup time of 900
s, the value
of CS is:
tStartup
+
CS
2.5 V
ICharge
CS min
+
900
m
s
264
m
A
2.5 V
+
950 nF
^
0.1
m
F
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8
The fault time is the sum of the slow discharge time the
fast discharge time and the recharge time. It is dominated by
the slow discharge time.
The first parameter is the slow discharge time, it is the time
for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:
tSlowDischarge(t)
+
CS
(2.4 V
*
1.5 V)
IDischarge
where I
Discharge
is 6.0
A typical.
tSlowDischarge(t)
+
CS
1.5
105
The fast discharge time occurs when a fault is first
detected. The CS capacitor is discharged from 2.5 V to 2.4 V.
tFastDischarge(t)
+
CS
(2.5 V
*
2.4 V)
IFastDischarge
where I
FastDischarge
is 66
A typical.
tFastDischarge(t)
+
CS
1515
The recharge time is the time for CS to charge from 1.5 V
to 2.5 V.
tCharge(t)
+
CS
(2.5 V
*
1.5 V)
ICharge
where I
Charge
is 264
A typical.
tCharge(t)
+
CS
3787
The fault time is given by:
tFault
+
CS
(3787
)
1515
)
1.5
105)
tFault
+
CS
(1.55
105)
For this circuit
tFault
+
0.1
10
*
6
1.55
105
+
15.5
m
s
A larger value of CS will increase the fault time out time
but will also increase the soft start time.
9) Input Capacitor
The input capacitor reduces the peak currents drawn from
the input supply and reduces the noise and ripple voltage on
the V
CC
and V
C
pins. This capacitor must also ensure that
the V
CC
remains above the UVLO voltage in the event of an
output short circuit. A low ESR capacitor of at least 100
F
is good. A ceramic surface mount capacitor should also be
connected between V
CC
and ground to filter high frequency
noise.
10) MOSFET Selection
The CS51031 drives a Pchannel MOSFET. The V
GATE
pin swings from GND to V
C
. The type of PFET used
depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.
A PFET with a continuous drain current (I
D
) rating greater
than the maximum output current is required.
The GatetoSource voltage V
GS
and the Drainto
Source Breakdown Voltage should be chosen based on the
input supply voltage.
The power dissipation due to the conduction losses is
given by:
PD
+
IOUT2
RDS(ON)
D
where
RDS(ON) is the value at TJ
+
100
C
The power dissipation of the PFET due to the switching
losses is given by:
PD
+
0.5
VIN
IOUT
(tr)
fSW
where t
r
= Rise Time.
11) Diode Selection
The flyback or catch diode should be a Schottky diode
because of it's fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.
The diode power dissipation is given by:
PD
+
IOUT
VD
(1.0
*
D min)
CS51031
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9
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
Shipping
CS51031YD8
40
C < T
A
< 85
C
SO8
95 Units/Rail
CS51031YDR8
40
C < T
A
< 85
C
SO8
2500 Tape & Reel
CS51031GD8
0
C < T
A
< 70
C
SO8
95 Units/Rail
CS51031GDR8
0
C < T
A
< 70
C
SO8
2500 Tape & Reel
CS51031
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10
PACKAGE DIMENSIONS
SO8
D SUFFIX
CASE 75107
ISSUE V
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
PACKAGE THERMAL DATA
Parameter
SO8
Unit
R
JC
Typical
45
C/W
R
JA
Typical
165
C/W
CS51031
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11
Notes
CS51031
http://onsemi.com
12
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CS51031/D
Literature Fulfillment:
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