Semiconductor Components Industries, LLC, 2002

October, 2002 Rev. 8

Publication Order Number:

CS51033/D

CS51033

Fast PFET Buck Controller

The CS51033 is a switching controller for use in dcdc converters.

It can be used in the buck topology with a minimum number of
external components. The CS51033 consists of a 1.0 A power driver
for controlling the gate of a discrete Pchannel transistor, fixed
frequency oscillator, short circuit protection timer, programmable Soft
Start, precision reference, fast output voltage monitoring comparator,
and output stage driver logic with latch.

The high frequency oscillator allows the use of small inductors and

output capacitors, minimizing PC board area and systems cost. The
programmable Soft Start reduces current surges at start up. The short
circuit protection timer significantly reduces the PFET duty cycle to
approximately 1/30 of its normal cycle during short circuit conditions.

The CS51033 is available in an 8Lead SO package.

Features

1.0 A Totem Pole Output Driver

High Speed Oscillator (700 kHz max)

No Stability Compensation Required

Lossless Short Circuit Protection

2.0% Precision Reference

Programmable Soft Start

Wide Ambient Temperature Range:

Industrial Grade: 40

C to 85

Commercial Grade: 0

C to 70

95 Units/Rail

http://onsemi.com

PIN CONNECTIONS

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W = Work Week

SO8

D SUFFIX

CASE 751

51033
ALYW

MARKING
DIAGRAM

GND

OSC

PGND

GATE

Device

Package

Shipping

ORDERING INFORMATION*

CS51033YD8

SO8

95 Units/Rail

CS51033YDR8

2500 Tape & Reel

CS51033GD8

SO8

*Additional ordering information can be found on page

9 of this data sheet.

CS51033GDR8

2500 Tape & Reel

SO8

CS51033

http://onsemi.com

Figure 1. Typical Application Diagram

GATE

PGND

OSC

GND

CS51033

100

0.1

300

1.0

GND

100

0.1

4.7

IRF7404

100

1.5V

OUT

@ 3.0 Amp

0.1

1N5818

1N4148

100

OSC

150 pF

1.5 k

0.1

GND

3.3V

1N5821

100

0.1

Note: Capacitors C

, C

, and C

, are low

ESR tantalum caps used for noise reduction.

MAXIMUM RATINGS*

Rating

Value

Unit

Power Supply Voltage, V

5.0

Driver Supply Voltage, V

Driver Output Voltage, V

GATE

OSC

, CS, V

(Logic Pins)

5.0

Peak Output Current

1.0

Steady State Output Current

200

Operating Junction Temperature, T

150

Storage Temperature Range, T

65 to 150

ESD (Human Body Model)

2.0

Package Thermal Resistance:

JunctiontoCase, R

JunctiontoAmbient, R

165

C/W

Lead Temperature Soldering:

Reflow (SMD styles only) (Note 1)

230 peak

1. 60 sec. max above 183

*The maximum package power dissipation must be observed.

CS51033

http://onsemi.com

ELECTRICAL CHARACTERISTICS

(Specifications apply for 3.135

3.465, 3.0 V

16 V;

Industrial Grade: 40

C < T

< 85

C; 40

C < T

< 125

C: Commercial Grade: 0

C < T

< 70

C; 0

C < T

< 125

C, unless otherwise specified.)

Characteristic

Test Conditions

Min

Typ

Max

Unit

Oscillator

= 1.2 V

Frequency

OSC

= 470 pF

160

200

240

kHz

Charge Current

1.4 V < V

COSC

< 2.0 V

110

Discharge Current

2.7 V > V

COSC

> 2.0 V

660

Maximum Duty Cycle

1 (t

OFF

)

80.0

83.3

Short Circuit Timer

= 1.0 V; CS = 0.1

F; V

COSC

= 2.0 V

Charge Current

1.0 V < V

< 2.0 V

175

264

325

Fast Discharge Current

2.55 V > V

> 2.4 V

Slow Discharge Current

2.4 V > V

> 1.5 V

4.0

6.0

Start Fault Inhibit Time

0.70

0.85

1.40

Valid Fault Time

2.6 V > V

> 2.4 V

0.2

0.3

0.45

GATE Inhibit Time

2.4 V > V

> 1.5 V

9.0

Duty Cycle

2.5

3.1

4.6

CS Comparator

= 1.0 V

Fault Enable CS Voltage

2.5

Max. CS Voltage

= 1.5 V

2.6

Fault Detect Voltage

when GATE goes high

2.4

Fault Inhibit Voltage

Minimum V

1.5

Hold Off Release Voltage

= 0 V

0.4

0.7

1.0

Regulator Threshold Voltage Clamp

= 1.5 V

0.725

0.866

1.035

Comparators

COSC

= V

= 2.0 V

Regulator Threshold Voltage

= 25

C (Note 2)

= 40 to 125

1.225
1.210

1.250
1.250

1.275
1.290

V
V

Fault Threshold Voltage

= 25

C (Note 2)

= 40 to 125

1.12
1.10

1.15
1.15

1.17
1.19

V
V

Threshold Line Regulation

3.135 V

3.465

6.0

Input Bias Current

= 0 V

1.0

4.0

Voltage Tracking

(Regulator Threshold Fault Threshold Voltage)

100

120

Input Hysteresis Voltage

4.0

Power Stage

= 10 V; V

= 1.2 V

GATE DC Low Saturation Voltage

COSC

= 1.0 V; 200 mA Sink

1.2

1.5

GATE DC High Saturation Voltage

COSC

= 2.7 V; 200 mA Source; V

= V

GATE

1.5

2.1

Rise Time

GATE

= 1.0 nF; 1.5 V < V

GATE

< 9.0 V

Fall Time

GATE

= 1.0 nF; 9.0 V > V

GATE

> 1.5 V

Current Drain

3.135 V < V

< 3.465 V, Gate switching

3.5

6.0

3.0 V < V

< 16 V, Gate nonswitching

2.7

4.0

2. Guaranteed by design, not 100% tested in production.

CS51033

http://onsemi.com

PACKAGE PIN DESCRIPTION

PIN NUMBER

PIN SYMBOL

FUNCTION

GATE

Driver pin to gate of external PFET.

PGND

Output power stage ground connection.

OSC

Oscillator frequency programming capacitor.

GND

Logic ground.

Feedback voltage input.

Logic supply voltage.

Soft Start and fault timing capacitor.

Driver supply voltage.

GATE

PGND

GATE

FlipFlop

Comparator

1.25 V

0.7 V

Hold Off

Comp

Fault

Comp

1.15 V

CS Charge
Sense
Comparator

Slow Discharge

FlipFlop

GND

Slow Discharge
Comparator

2.3 V

2.4 V

CS
Comparator

2.5 V

1.5 V

OSC

2.5 V

1.5 V

Oscillator
Comparator

Figure 2. Block Diagram

CS51033

http://onsemi.com

CIRCUIT DESCRIPTION

THEORY OF OPERATION

Control Scheme

The CS51033 monitors the output voltage to determine

when to turn on the PFET. If V

falls below the internal

reference voltage of 1.25 V during the oscillator's charge
cycle, the PFET is turned on and remains on for the duration
of the charge time. The PFET gets turned off and remains off
during the oscillator's discharge cycle time with the
maximum duty cycle to 80%. It requires 7.0 mV typical, and
20 mV maximum ripple on the V

pin to operate. This

method of control does not require any loop stability
compensation.

Startup

The CS51033 has an externally programmable Soft Start

feature that allows the output voltage to come up slowly,
preventing voltage overshoot on the output.

At startup, the voltage on all pins is zero. As V

rises, the

voltage along with the internal resistor R

keeps the

PFET off. As V

and V

continue to rise, the oscillator

capacitor (C

OSC

) and the Soft Start/Fault Timing capacitor

(CS) charges via internal current sources. C

OSC

gets charged

by the current source I

and CS gets charged by the I

source

combination described by:

ICS

)

The internal Holdoff Comparator ensures that the external

PFET is off until V

> 0.7 V, preventing the GATE flipflop

(F2) from being set. This allows the oscillator to reach its
operating frequency before enabling the drive output. Soft
Start is obtained by clamping the V

comparator's (A6)

reference input to approximately 1/2 of the voltage at the CS

pin during startup, permitting the control loop and the output
voltage to slowly increase. Once the CS pin charges above
the Holdoff Comparator trip point of 0.7 V, the low feedback
to the V

Comparator sets the GATE flipflop during

OSC

's charge cycle. Once the GATE flipflop is set,

GATE

goes low and turns on the PFET. When V

exceeds

2.4 V, the CS charge sense comparator (A4) sets the V

comparator reference to 1.25 V completing the startup cycle.

Lossless Short Circuit Protection

The CS51033 has "lossless" short circuit protection since

there is no current sense resistor required. When the voltage
at the CS pin (the fault timing capacitor voltage ) reaches
2.5 V, the fault timing circuitry is enabled. During normal
operation the CS voltage is 2.6 V. During a short circuit or
a transient condition, the output voltage moves lower and the
voltage at V

drops. If V

drops below 1.15 V, the output

of the fault comparator goes high and the CS51033 goes into
a fast discharge mode. The fault timing capacitor, CS,
discharges to 2.4 V. If the V

voltage is still below 1.15 V

when the CS pin reaches 2.4 V, a valid fault condition has
been detected. The slow discharge comparator output goes
high and enables gate G5 which sets the slow discharge flip
flop. The V

GATE

flip flop resets and the output switch is

turned off. The fault timing capacitor is slowly discharged
to 1.5 V. The CS51033 then enters a normal startup routine.
If the fault is still present when the fault timing capacitor
voltage reaches 2.5 V, the fast and slow discharge cycles
repeat as shown in Figure 3.

If the V

voltage is above 1.15 V when CS reaches 2.4 V

a fault condition is not detected, normal operation resumes
and CS charges back to 2.6 V. This reduces the chance of
erroneously detecting a load transient as a fault condition.

Figure 3. Voltage on Start Capacitor (V

), the Gate (V

GATE

), and in the

Feedback Loop (V

), During Startup, Normal and Fault Conditions.

1.15 V

1.25 V

0 V

1.5 V

2.4 V

2.6 V

2.5 V

0 V

GATE

START

NORMAL OPERATION

FAULT

td1

START

FAULT

RESTART

td2

FAULT

CS51033

http://onsemi.com

Buck Regulator Operation

A block diagram of a typical buck regulator is shown in

Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current I

is zero and the output voltage is at its

nominal value. The current drawn by the load is supplied by
the output capacitor C

. When the voltage across C

drops

below the threshold established by the feedback resistors R1

and R2 and the reference voltage V

REF

, the power transistor

Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(V

OUT

)/Load. The duty cycle (or "on" time) for the

CS51033 is limited to 80%. If output voltage remains higher
than nominal during the entire C

OSC

change time, the Q1

does not turn on, skipping the pulse.

Figure 4. Buck Regulator Block Diagram.

LOAD

Feedback

Control

Charge Pump Circuit

(Refer to the CS51033 Application Diagram on page 2).
An external charge pump circuit is necessary when the V

input voltage is below 5.0 V to ensure that there is suffifient
gate drive voltage for the external FET. When V

is applied,

capacitors C1 and C2 will be charged to a diodes drop below
V

via diodes D2 and D4, respectively. When the PFET

turns on, it's drain voltage will be approximately equal to
V

. Since the voltage across C1 can not change

instantaneously, D2 is reverse biased and the anode voltage
rises to approximately 2.0

3.3 V VD2. C1 transfers some

of its stored charge C2 via D3. After several cycles there is
sufficient gate drive voltage.

APPLICATIONS INFORMATION

DESIGNING A POWER SUPPLY WITH THE CS51033

Specifications

= 3.3 V

10% (i.e. 3.63 V max., 2.97 V min.)

OUT

= 1.5 V

2.0%

OUT

= 0.3 A to 3.0 A

Output ripple voltage < 33 mV.

= 200 kHz

1) Duty Cycle Estimates

Since the maximum duty cycle D, of the CS51033 is

limited to 80% min., it is best to estimate the duty cycle for
the various input conditions to see that the design will work
over the complete operating range.

The duty cycle for a buck regulator operating in a

continuous conduction mode is given by:

VOUT

)

VIN

VSAT

where:

SAT

= R

DS(ON)

OUT

Max.

In this case we can assume that V

= 0.6 V and V

SAT

0.6 V so the equation reduces to:

VOUT

VIN

From this, the maximum duty cycle D

MAX

is 53%, this

occurs when V

is at it's minimum while the minimum duty

cycle D

MIN

is 0.35%.

2) Switching Frequency and On and Off Time
Calculations

= 200 kHz. The switching frequency is determined

by C

OSC

, whose value is determined by:

COSC

FSW

106

103

FSW

470 pF

1.0

FSW

5.0

CS51033

http://onsemi.com

TON(MAX)

5.0

0.53

2.65

TON(MIN)

5.0

0.35

1.75

TOFF(MAX)

5.0

0.7

4.3

3) Inductor Selection

Pick the inductor value to maintain continuous mode

operation down to 0.3 Amps.

The ripple current

I = 2

OUT(MIN)

= 2

0.3 A = 0.6 A.

LMIN

VOUT

)

TOFF(MAX)

2.1 V

4.3

0.6 A

The CS51033 will operate with almost any value of

inductor. With larger inductors the ripple current is reduced
and the regulator will remain in a continuous conduction
mode for lower values of load current. A smaller inductor
will result in larger ripple current. The core must not saturate
with the maximum expected current, here given by:

IMAX

IOUT

) D

2.0

3.0 A

)

0.6 A 2.0

3.3 A

4) Output Capacitor

The output capacitor limits the output ripple voltage. The

CS51033 needs a maximum of 15 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak to peak is given by:

8.0

FSW

0.6 A

8.0

(200

103 Hz)

(33

3 V)

11.4

The minimum ESR needed to limit the output voltage

ripple to 50 mV peak to peak is:

ESR

+ D

0.6 A

55 m

The output capacitor should be chosen so that its ESR is

at least half of the calculated value and the capacitance is at
least ten times the calculated value. It is often advisable to
use several capacitors in parallel to reduce ESR.

Low impedance aluminum electrolytic, tantalum or

organic semiconductor capacitors are a good choice for an
output capacitor. Low impedance aluminum are the
cheapest but are not available in surface mount at present.
Solid tantalum chip capacitors are available from a number
of suppliers and offer the best choice for surface mount
applications. The capacitor working voltage should be
greater than the output voltage in all cases.

5) V

Divider

VOUT

1.25 V R1

)

1.25 V R1

)

1.0

The input bias current to the comparator is 4.0

A. The

resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this gives a divider current of 1.0 mA and simplifies
the calculations.

1.5 V

1.0 mA

)

1.5 k

Let R2 = 1.0 k
Rearranging the divider equation gives:

VOUT

1.25

1.0

1.0 k

1.5 V

1.25

200

6) Divider Bypass Capacitor C

Since the feedback resistors divide the output voltage by

a factor of 4.0, i.e. 5.0 V/1.25 V= 4.0, it follows that the
output ripple is also divided by four. This would require that
the output ripple be at least 60 mV (4.0

15 mV) to trip the

feedback comparator. We use a capacitor C

to act as an

AC short so that the output ripple is not attenuated by the
divider network. The ripple voltage frequency is equal to the
switching frequency so we choose C

so that:

1.0

is negligible at the switching frequency.

In this case F

is 200 kHz if we allow X

= 3.0

then:

1.0

0.265

7) Soft Start and Fault Timing Capacitor CS

CS performs several important functions. First it provides

a dead time for load transients so that the IC does not enter
a fault mode every time the load changes abruptly. Secondly
it disables the fault circuitry during startup, it also provides
Soft Start by clamping the reference voltage during startup
to rise slowly and finally it controls the hiccup short circuit
protection circuitry. This function reduces the PFET's duty
cycle to 2.0% of the CS period.

The most important consideration in calculating CS is that

it's voltage does not reach 2.5 V (the voltage at which the
fault detect circuitry is enabled) before V

reaches 1.15 V

otherwise the power supply will never start.

If the V

pin reaches 1.15 V, the fault timing comparator

will discharge CS and the supply will not start. For the V

voltage to reach 1.15 V the output voltage must be at least
4

1.15 = 4.6 V.

CS51033

http://onsemi.com

If we choose an arbitrary startup time of 200

s, we

calculate the value of CS from:

2.5 V

ICHARGE

CS(MIN)

200

264

2.5 V

0.02

Use 0.1

The fault time out time is the sum of the slow discharge

time the fast discharge time and the recharge time and is
obviously dominated by the slow discharge time.

The first parameter is the slow discharge time, it is the time

for the CS capacitor to discharge from 2.4 V to 1.5 V and is
given by:

TSLOWDISCHARGE

(2.4 V

1.5 V)

IDISCHARGE

where I

DISCHARGE

is 6.0

A typical.

TSLOWDISCHARGE

1.5 V

105

The fast discharge time occurs when a fault is first

detected. The CS capacitor is discharged from 2.5 V to 2.4 V.

TFASTDISCHARGE

(2.5 V

2.4 V)

IFASTDISCHARGE

where I

FASTDISCHARGE

is 66

A typical.

TFASTDISCHARGE

1515

The recharge time is the time for CS to charge from 1.5 V

to 2.5 V.

TCHARGE

(2.5 V

1.5 V)

ICHARGE

where I

CHARGE

is 264

A typical.

TCHARGE

3787

The fault time out time is given by:

TFAULT

(3787

)

1515

)

1.5

105)

TFAULT

(1.55

105)

For this circuit

TFAULT

0.1

1.55

105

0.0155

A larger value of CS will increase the fault time out time

but will also increase the Soft Start time.

8) Input Capacitor

The input capacitor reduces the peak currents drawn from

the input supply and reduces the noise and ripple voltage on
the V

and V

pins. This capacitor must also ensure that

the V

remains above the UVLO voltage in the event of an

output short circuit. C

should be a low ESR capacitor of

at least 100

F. A ceramic surface mount capacitor should

also be connected between V

and ground to prevent

spikes.

9) MOSFET Selection

The CS51033 drives a Pchannel MOSFET. The V

GATE

pin swings from GND to V

. The type of PFET used

depends on the operating conditions but for input voltages
below 7.0 V a logic level FET should be used.

Choose a PFET with a continuous drain current (I

) rating

greater than the maximum output current. R

DS(ON)

should

be less than

RDS

0.6 V

IOUT(MAX)

167 m

The GatetoSource voltage V

and the Drainto

Source Breakdown Voltage should be chosen based on the
input supply voltage.

The power dissipation due to the conduction losses is

given by:

IOUT2

RDS(ON)

The power dissipation due to the switching losses is given

by:

0.5

VIN

IOUT

(TRr

)

TF)

FSW

where T

= Rise Time and T

= Fall Time

10) Diode Selection

The flyback or catch diode should be a Schottky diode

because of it's fast switching ability and low forward voltage
drop. The current rating must be at least equal to the
maximum output current. The breakdown voltage should be
at least 20 V for this 12 V application.

The diode power dissipation is given by:

IOUT

(1.0

DMIN)

CS51033

http://onsemi.com

PACKAGE DIMENSIONS

SO8

D SUFFIX

CASE 75107

ISSUE AA

SEATING

PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN

EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

6. 751-01 THRU 751-06 ARE OBSOLETE. NEW

STANDAARD IS 751-07

0.10 (0.004)

DIM

MIN

MAX

MIN

MAX

INCHES

4.80

5.00

0.189

0.197

MILLIMETERS

3.80

4.00

0.150

0.157

1.35

1.75

0.053

0.069

0.33

0.51

0.013

0.020

1.27 BSC

0.050 BSC

0.10

0.25

0.004

0.010

0.19

0.25

0.007

0.010

0.40

1.27

0.016

0.050

0.25

0.50

0.010

0.020

5.80

6.20

0.228

0.244

X

Y

0.25 (0.010)

Z

0.25 (0.010)

CS51033

http://onsemi.com

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

JAPAN: ON Semiconductor, Japan Customer Focus Center

291 Kamimeguro, Meguroku, Tokyo, Japan 1530051
Phone: 81357733850
Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

CS51033/D

Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: ONlit@hibbertco.com

N. American Technical Support: 8002829855 Toll Free USA/Canada

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CS51033GDR8

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CS51033GDR8