Semiconductor Components Industries, LLC, 2001

January, 2001 Rev. 2

Publication Order Number:

CS5156H/D

CS5156H

CPU 5-Bit Nonsynchronous

Buck Controller

The CS5156H is a 5bit nonsynchronous NChannel buck

controller. It is designed to provide unprecedented transient response
for today's demanding highdensity, highspeed logic. The regulator
operates using a proprietary control method, which allows a 100 ns
response time to load transients. The CS5156H is designed to operate
over a 4.2520 V range (V

) using 12 V to power the IC and 5.0 V or

12 V as the main supply for conversion.

The CS5156H is specifically designed to power Pentium

processors and other high performance core logic. It includes the
following features: on board, 5bit DAC, short circuit protection,
1.0% output tolerance, V

monitor, and programmable Soft Start

capability. The CS5156H is backwards compatible with the 4bit
CS5151, allowing the mother board designer the capability of using
either the CS5151 or the CS5156H with no change in layout. The
CS5156H is available in 16 pin surface mount packages.

Features

NChannel Design

Excess of 1.0 MHz Operation

100 ns Transient Response

5Bit DAC

Backward Compatible with 4Bit CS5150H/CS5151H

30 ns Gate Rise/Fall Times

1.0% DAC Accuracy

5.0 V & 12 V Operation

Remote Sense

Programmable Soft Start

Lossless Short Circuit Protection

Monitor

Adaptive Voltage Positioning

Control Topology

Current Sharing

Overvoltage Protection

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= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W

= Work Week

Device

Package

Shipping

ORDERING INFORMATION

CS5156HGD16

SO16

48 Units/Rail

SO16

2500 Tape & Reel

SOIC16

D SUFFIX

CASE 751B

PIN CONNECTIONS

CS5156H
AWLYWW

MARKING
DIAGRAM

CC2

FFB

GATE

OFF

PGND

ID4

CC1

ID3

LGND

ID2

COMP

ID1

ID0

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Figure 1. Application Diagram, Switching Power Supply for Core Logic Pentium

)

II Processor

COMP

FFB

GATE

CC2

CC1

ID0

ID1

ID2

ID3

PGND

OFF

CS5156H

AIEI

12 V

330 pF

0.1

LGND

1200

F/16 V

0.1

1.3 V to 3.5 V @ 13 A

ID0

ID1

ID2

ID3

AIEI

1200

F/16 V

2.0

IRL3103

0.33

5.0 V

MBR1535CT

3.3 k

100 pF

ID4

1,3

ABSOLUTE MAXIMUM RATINGS*

Rating

Value

Unit

Operating Junction Temperature, T

0 to 150

Lead Temperature Soldering:

Reflow: (SMD styles only) (Note 1.)

230 peak

Storage Temperature Range, T

65 to +150

ESD Susceptibility (Human Body Model)

2.0

1. 60 second maximum above 183

*The maximum package power dissipation must be observed.

ABSOLUTE MAXIMUM RATINGS

Pin Name

Max Operating Voltage

Max Current

CC1

16 V/0.3 V

25 mA DC/1.5 A peak

CC2

20 V/0.3 V

20 mA DC/1.5 A peak

6.0 V/0.3 V

100

COMP

6.0 V/0.3 V

200

6.0 V/0.3 V

0.2

OFF

6.0 V/0.3 V

0.2

FFB

6.0 V/0.3 V

0.2

ID0

ID4

6.0 V/0.3 V

GATE

20 V/0.3 V

100 mA DC/1.5 A peak

LGND

0 V

25 mA

PGND

0 V

100 mA DC/1.5 A peak

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ELECTRICAL CHARACTERISTICS

C < T

< +70

C; 0

C < T

< +125

C; 8.0

V < V

CC1

< 14

V; 5.0

V < V

CC2

< 20

DAC Code: V

ID4

ID2

ID1

ID0

= 1; V

ID3

= 0

;

GATE

= 1.0

nF; C

OFF

= 330 pF; C

= 0.1

F, unless otherwise specified.)

Characteristic

Test Conditions

Min

Typ

Max

Unit

Error Amplifier

Bias Current

= 0 V

0.3

1.0

Open Loop Gain

1.25 V < V

COMP

< 4.0 V; Note 2.

Unity Gain Bandwidth

Note 2.

500

3000

kHz

COMP SINK Current

COMP

= 1.5 V; V

= 3.0 V; V

> 2.0 V

0.4

2.5

8.0

COMP SOURCE Current

COMP

= 1.2 V; V

= 2.7 V; V

= 5.0 V

COMP CLAMP Current

COMP

= 0 V; V

= 2.7 V

0.4

1.0

1.6

COMP High Voltage

= 2.7 V; V

= 5.0 V

4.0

4.3

5.0

COMP Low Voltage

= 3.0 V

160

600

PSRR

8.0 V < V

CC1

< 14 V @ 1.0 kHz; Note 2.

CC1

Monitor

Start Threshold

Output switching

3.75

3.90

4.05

Stop Threshold

Output not switching

3.70

3.85

4.00

Hysteresis

StartStop

GATE

Out SOURCE Sat at 100 mA

Measure V

CC2

GATE

1.2

2.0

Out SINK Sat at 100 mA

Measure V

GATE

PGND

1.0

1.5

Out Rise Time

1.0 V < V

GATE

< 9.0 V; V

CC1

= V

CC2

= 12 V

Out Fall Time

9.0 V > V

GATE

> 1.0 V; V

CC1

= V

CC2

= 12 V

ShootThrough Current

Note 2.

GATE

Resistance

Resistor to LGND. Note 2.

100

GATE

Schottky

LGND to V

GATE

@ 10 mA

600

800

Soft Start (SS)

Charge Time

1.6

3.3

5.0

Pulse Period

100

200

Duty Cycle

(Charge Time /Pulse Period)

100

1.0

3.3

6.0

COMP Clamp Voltage

= 0 V; V

= 0

0.50

0.95

1.10

FFB

SS Fault Disable

GATE

= Low

0.9

1.0

1.1

High Threshold

2.5

3.0

PWM Comparator

Transient Response

FFB

= 0 to 5.0 V to V

GATE

= 9.0 V to 1.0 V;

CC1

= V

CC2

= 12 V

100

125

FFB

Bias Current

FFB

= 0 V

0.3

2. Guaranteed by design, not 100% tested in production.

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ELECTRICAL CHARACTERISTICS (continued)

C < T

< +70

C; 0

C < T

< +125

C; 8.0

V < V

CC1

< 14

V; 5.0

V < V

CC2

< 20

DAC Code: V

ID4

ID2

ID1

ID0

= 1; V

ID3

= 0

;

GATE

= 1.0

nF; C

OFF

= 330 pF; C

= 0.1

F, unless otherwise specified.)

Characteristic

Unit

Max

Typ

Min

Test Conditions

DAC

Input Threshold

ID0,

ID1

, V

ID2

, V

ID3

, V

ID4

1.00

1.25

2.40

Input Pull Up Resistance

ID0,

ID1

, V

ID2

, V

ID3

, V

ID4

100

Pull Up Voltage

4.85

5.00

5.15

Accuracy (all codes except 11111)

Measure V

= COMP, 25

125

1.0

ID4

ID3

ID2

ID1

ID0

1.3266

1.3400

1.3534

1.3761

1.3900

1.4039

1.4256

1.4400

1.4544

1.4751

1.4900

1.5049

1.5246

1.5400

1.5554

1.5741

1.5900

1.6059

1.6236

1.6400

1.6564

1.6731

1.6900

1.7069

1.7226

1.7400

1.7574

1.7721

1.7900

1.8079

1.8216

1.8400

1.8584

1.8711

1.8900

1.9089

1.9206

1.9400

1.9594

1.9701

1.9900

2.0099

2.0196

2.0400

2.0604

2.0691

2.0900

2.1109

1.2191

1.2440

1.2689

2.1186

2.1400

2.1614

2.2176

2.2400

2.2624

2.3166

2.3400

2.3634

2.4156

2.4400

2.4644

2.5146

2.5400

2.5654

2.6136

2.6400

2.6664

2.7126

2.7400

2.7674

2.8116

2.8400

2.8684

2.9106

2.9400

2.9694

3.0096

3.0400

3.0704

3.1086

3.1400

3.1714

3.2076

3.2400

3.2724

3.3066

3.3400

3.3734

3.4056

3.4400

3.4744

3.5046

3.5400

3.5754

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ELECTRICAL CHARACTERISTICS (continued)

C < T

< +70

C; 0

C < T

< +125

C; 8.0

V < V

CC1

< 14

V; 5.0

V < V

CC2

< 20

DAC Code: V

ID4

ID2

ID1

ID0

= 1; V

ID3

= 0

;

GATE

= 1.0

nF; C

OFF

= 330 pF; C

= 0.1

F, unless otherwise specified.)

Characteristic

Unit

Max

Typ

Min

Test Conditions

Supply Current

CC1

No Switching

8.5

13.5

CC2

No Switching

1.6

3.0

Operating I

CC1

= COMP = V

FFB

8.0

Operating I

CC2

= COMP = V

FFB

2.0

5.0

OFF

Normal Charge Time

FFB

= 1.5 V; V

= 5.0 V

1.0

1.6

2.2

Extension Charge Time

= V

FFB

= 0

5.0

8.0

11.0

Discharge Current

OFF

to 5.0 V; V

> 1.0 V

5.0

Time Out Timer

Time Out Time

= V

COMP

; V

FFB

= 2.0 V;

Record V

GATE

Pulse High Duration

Fault Mode Duty Cycle

FFB

= 0V

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

SO16

PIN SYMBOL

FUNCTION

1, 2, 3, 4, 6

ID0

ID4

Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V pro-
viding logic ones if left open. V

ID4

selects the DAC range. When V

ID4

is High

(logic one), the DAC range is 2.14 V to 3.54 V with 100 mV increments.
When V

ID4

is Low (logic zero), the DAC range is 1.34 V to 2.09 V with 50

mV increments. V

ID0

ID4

select the desired DAC output voltage. Leaving

all 5 DAC input pins open results in a DAC output voltage of 1.244 V, allow-
ing for adjustable output voltage, using a traditional resistor divider.

Soft Start Pin. A capacitor from this pin to LGND in conjunction with internal
60

A current source provides Soft Start function for the controller. This pin

disables fault detect function during Soft Start. When a fault is detected, the
Soft Start capacitor is slowly discharged by internal 2.0

A current source

setting the time out before trying to restart the IC. Charge/discharge current
ratio of 30 sets the duty cycle for the IC when the regulator output is shorted.

OFF

A capacitor from this pin to ground sets the time duration for the on board one
shot, which is used for the constant off time architecture.

FFB

Fast feedback connection to the PWM comparator. This pin is connected to
the regulator output. The inner feedback loop terminates on time.

CC2

Boosted power for the gate driver.

GATE

MOSFET driver pin capable of 1.5 A peak switching current.

PGND

High current ground for the IC. The MOSFET driver is referenced to this pin.
Input capacitor ground and the anode of the Schottky diode should be tied to
this pin.

No connection.

CC1

Input power for the IC.

LGND

Signal ground for the IC. All control circuits are referenced to this pin.

COMP

Error amplifier compensation pin. A capacitor to ground should be provided
externally to compensate the amplifier.

Error amplifier DC feedback input. This is the master voltage feedback which
sets the output voltage. This pin can be connected directly to the output or a
remote sense trace.

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CC1

ID0

ID1

ID2

ID3

FFB

Low

Comparator

FFB

Fast Feedback

LGND

Slow Feedback

PWM
Comparator

SS Low
Comparator

SS High
Comparator

5 BIT
DAC

CC1

Monitor

Comparator

Error
Amplifier

CC2

OFF

GATE

FAULT

Latch

PGND

Latch

PMW

OFF

One Shot

OffTime

Timeout

TimeOut

Timer

Edge Triggered

Extended

OffTime

Timeout

Normal

OffTime

Timeout

Maximum

OnTime

Timeout

(30

GATE = ON

GATE = OFF

2.0

5.0 V

0.7 V

2.5 V

1.0 V

3.90 V

3.85V

COMP

Figure 2. Block Diagram

PWM COMP

ID4

APPLICATIONS INFORMATION

THEORY OF OPERATION

Control Method

The V

method of control uses a ramp signal that is

generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is
generated from the output voltage itself. This control
scheme inherently compensates for variation in either line or
load conditions, since the ramp signal is generated from the
output voltage itself. This control scheme differs from
traditional techniques such as voltage mode, which
generates an artificial ramp, and current mode, which
generates a ramp from inductor current.

Figure 3. V

Control Diagram

COMP

FFB

Reference

Voltage

PWM
Comparator

Ramp

Signal

Error

Amplifier

Error

Signal

Output
Voltage
Feedback

GATE

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The V

control method is illustrated in Figure 3. The

output voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regardless
of the origin of that change. The ramp signal also contains
the DC portion of the output voltage, which allows the
control circuit to drive the main switch to 0% or 100% duty
cycle as required.

A change in line voltage changes the current ramp in the

inductor, affecting the ramp signal, which causes the V

control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V

control scheme has the same

advantages in line transient response.

A change in load current will have an affect on the output

voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined only
by the comparator response time and the transition speed of
the main switch. The reaction time to an output load step has
no relation to the crossover frequency of the error signal
loop, as in traditional control methods.

The error signal loop can have a low crossover frequency,

since transient response is handled by the ramp signal loop.
The main purpose of this `slow' feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote
sensing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered.

Line and load regulation are drastically improved because

there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains fixed error signal under
deviation in the line voltage, since the slope of the ramp
signal changes, but still relies on a change in the error signal
for a deviation in load. The V

method of control maintains

a fixed error signal for both line and load variation, since the
ramp signal is affected by both line and load.

Constant Off Time

To maximize transient response, the CS5156H uses a

constant off time method to control the rate of output pulses.
During normal operation, the off time of the high side switch
is terminated after a fixed period, set by the C

OFF

capacitor.

To maintain regulation, the V

control loop varies switch on

time. The PWM comparator monitors the output voltage
ramp, and terminates the switch on time.

Constant off time provides a number of advantages.

Switch duty cycle can be adjusted from 0 to 100% on a pulse
by pulse basis when responding to transient conditions. Both
0% and 100% duty cycle operation can be maintained for
extended periods of time in response to load or line
transients. PWM slope compensation to avoid
subharmonic oscillations at high duty cycles is avoided.

Switch on time is limited by an internal 30

s timer,

minimizing stress to the power components.

Programmable Output

The CS5156H is designed to provide two methods for

programming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges. The
first range is 2.14 V to 3.54 V in 100 mV steps, the second
is 1.34 V to 2.09 V in 50 mV steps, depending on the digital
input code. If all five bits are left open, the CS5156H enters
adjust mode. In adjust mode, the designer can choose any
output voltage by using resistor divider feedback to the V

and V

FFB

pins, as in traditional controllers. The CS5156H

is specifically designed to be backwards compatible with the
CS5151H, which uses a four bit DAC code.

Start Up

Until the voltage on the V

CC1

supply pin exceeds the 3.9 V

monitor threshold, the Soft Start and gate pins are held low.
The FAULT latch is reset (no Fault condition). The output
of the error amplifier (COMP) is pulled up to 1.0 V by the
comparator clamp. When the V

CC1

pin exceeds the monitor

threshold, the GATE output is activated, and the Soft Start
capacitor begins charging. The GATE output will remain on,
enabling the NFET switch, until terminated by either the
PWM comparator, or the maximum on time timer.

If the maximum on time is exceeded before the regulator

output voltage achieves the 1.0 V level, the pulse is
terminated. The GATE pin drives low for the duration of the
extended off time. This time is set by the time out timer and
is approximately equal to the maximum on time, resulting in
a 50% duty cycle. Then, the GATE pin will drive high, and
the cycle repeats.

When regulator output voltage achieves the 1.0 V level

present at the COMP pin, regulation has been achieved and
normal off time will ensue. The PWM comparator
terminates the switch on time, with off time set by the C

OFF

capacitor. The V

control loop will adjust switch duty cycle

as required to ensure the regulator output voltage tracks the
output of the error amplifier.

The Soft Start and COMP capacitors will charge to their

final levels, providing a controlled turn on of the regulator
output. Regulator turn on time is determined by the COMP
capacitor charging to its final value. Its voltage is limited by

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the Soft Start COMP clamp and the voltage on the Soft Start
pin (see Figures 4 and 5).

Figure 4. CS5156H Demonstration Board Startup in

Response to Increasing 12 V and 5.0 V Input Voltages.

Extended Off Time is Followed by Normal Off Time

Operation when Output Voltage Achieves Regulation to

the Error Amplifier Output.

M 250

Trace 3 12 V Input (V

CC1

and V

CC2

) (5.0 V/div.)

Trace 1 Regulator Output Voltage (1.0 V/div.)

Trace 4 5.0 V Input (1.0 V/div.)

Trace 2 Inductor Switching Node (2.0 V/div.)

Figure 5. CS5156H Demonstration Board Startup

Waveforms

M 2.50 ms

Trace 3 COMP PIn (error amplifier output) (1.0 V/div.)

Trace 1 Regulator Output Voltage (1.0 V/div.)

Trace 4 Soft Start Pin (2.0 V/div.)

If the input voltage rises quickly, or the regulator output

is enabled externally, output voltage will increase to the
level set by the error amplifier output more rapidly, usually
within a couple of cycles (see Figure 6).

Figure 6. CS5156H Demonstration Board Enable

Startup Waveforms

M 10.0

Trace 1 Regulator Output Voltage (5.0 V/div.)

Trace 2 Inductor Switching Node (5.0 V/div.)

Normal Operation

During normal operation, switch off time is constant and

set by the C

OFF

capacitor. Switch on time is adjusted by the

control loop to maintain regulation. This results in

changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
working into the ESR of the output capacitors (see Figures
7 and 8).

Figure 7. PeaktoPeak Ripple on V

OUT

= 2.8 V,

OUT

= 0.5 A (Light Load)

M 1.00

Trace 1 Regulator Output Voltage (10 mV/div.)

Trace 2 Inductor Switching Node (5.0 V/div.)

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Figure 8. PeaktoPeak Ripple on V

OUT

= 2.8 V,

OUT

= 13 A (Heavy Load)

M 1.00

Trace 1 Regulator Output Voltage (10 mV/div.)

Trace 2 Inductor Switching Node (5.0 V/div.)

Transient Response

The CS5156H V

control loop's 100 ns reaction time

provides unprecedented transient response to changes in
input voltage or output current. Pulse by pulse adjustment of
duty cycle is provided to quickly ramp the inductor current
to the required level. Since the inductor current cannot be
changed instantaneously, regulation is maintained by the
output capacitor(s) during the time required to slew the
inductor current.

Overall load transient response is further improved

through a feature called "adaptive voltage positioning". This
technique prepositions the output capacitor's voltage to
reduce total output voltage excursions during changes in
load.

Holding tolerance to 1.0% allows the error amplifier's

reference voltage to be targeted +40 mV high without
compromising DC accuracy. A "droop resistor",
implemented through a PC board trace, connects the error
amplifier's feedback pin (V

) to the output capacitors and

load and carries the output current. With no load, there is no
DC drop across this resistor, producing an output voltage
tracking the error amplifier's, including the +40 mV offset.
When the full load current is delivered, an 80 mV drop is
developed across this resistor. This results in output voltage
being offset 40 mV low.

The result of adaptive voltage positioning is that

additional margin is provided for a load transient before
reaching the output voltage specification limits. When load
current suddenly increases from its minimum level, the
output capacitor is prepositioned +40 mV. Conversely,
when load current suddenly decreases from its maximum

level, the output capacitor is prepositioned 40 mV (see
Figures 9, 10, and 11). For best transient response, a
combination of a number of high frequency and bulk output
capacitors are usually used.

If the maximum on time is exceeded while responding to

a sudden increase in load current, a normal off time occurs
to prevent saturation of the output inductor.

Figure 9. CS5156H Demonstration Board Response

to a 0.5 to 13 A Load Pulse (Output Set for 2.8 V)

Trace 2 Regulator Output Voltage (20 V/div.)

Trace 1 Regulator Output Voltage (1.0 V/div.)

Figure 10. CS5156H Demonstration Board Response to

13 A Load Turn On (Output Set for 2.8 V). Upon

Completing a Normal Off Time, The V

Control Loop

Immediately Connects the Inductor to the Input

Voltage, Providing 100% Duty Cycle. Regulation is

Achieved in Less Than 20

Trace 1 Regulator Output Voltage (1.0 V/div.)

Trace 2 Inductor Switching Node (5.0 V/div.)

Trace 3 Output Current (0.5 to 13 Amps) (20 V/div.)

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Figure 11. CS5156H Demonstration Board Response to

13 A Load Turn Off (Output Set for 2.8 V). V

Control

Topology Immediately Connects Inductor to Ground,

Providing 0% Duty Cycle. Regulation is Achieved in

Less Than 10

Trace 3 Output Current (13 to 0,5 Amps) (20 mV/div.)

Trace 2 Inductor Switching Node (5.0 V/div.)

Trace 1 Regulator Output Voltage (1.0 V/div.)

PROTECTION AND MONITORING FEATURES

CC1

Monitor

To maintain predictable startup and shutdown

characteristics an internal V

CC1

monitor circuit is used to

prevent the part from operating below 3.75 V minimum
startup. The V

CC1

monitor comparator provides hysteresis

and guarantees a 3.70 V minimum shutdown threshold.

Short Circuit Protection

A lossless hiccup mode short circuit protection feature is

provided, requiring only the Soft Start capacitor to
implement. If a short circuit condition occurs (V

FFB

< 1.0 V),

the V

FFB

low comparator sets the FAULT latch. This causes

the MOSFET to shut off, disconnecting the regulator from
it's input voltage. The Soft Start capacitor is then slowly
discharged by a 2.0

A current source until it reaches it's

lower 0.7 V threshold. The regulator will then attempt to
restart normally, operating in it's extended off time mode
with a 50% duty cycle, while the Soft Start capacitor is
charged with a 60

A charge current.

If the short circuit condition persists, the regulator output

will not achieve the 1.0 V low V

FFB

comparator threshold

before the Soft Start capacitor is charged to it's upper 2.5 V
threshold. If this happens the cycle will repeat itself until the
short is removed. The Soft Start charge/discharge current
ratio sets the duty cycle for the pulses (2.0

A/60

A =

3.3%), while actual duty cycle is half that due to the
extended off time mode (1.65%).

This protection feature results in less stress to the

regulator components, input power supply, and PC board

traces than occurs with constant current limit protection (see
Figures 12 and 13).

If the short circuit condition is removed, output voltage

will rise above the 1.0 V level, preventing the FAULT latch
from being set, allowing normal operation to resume.

Figure 12. CS5156H Demonstration Board Hiccup

Mode Short Circuit Protection. Gate Pulses are

Delivered While the Soft Start Capacitor Charges, and

Cease During Discharge

M 25.0 ms

Trace 3 Soft Start Timing Capacitor (1.0 V/div.)

Trace 4 5.0 V Supply Voltage (2.0 V/div.)

Trace 2 Inductor Switching Node (2.0 V/div.)

Figure 13. Startup with Regulator Output Shorted

M 50.0

Trace 4 5.0 V from PC Power Supply (2.0 V/div.)

Trace 2 Inductor Switching Node (2.0 V/div.)

Overvoltage Protection

Overvoltage protection (OVP) is provided as result of the

normal operation of the V

control topology and requires no

additional external components. The control loop responds
to an overvoltage condition within 100 ns, causing the top
MOSFET to shut off, disconnecting the regulator from it's
input voltage.

External Output Enable Circuit

On/off control of the regulator can be implemented

through the addition of two additional discrete components

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(see Figure 14). This circuit operates by pulling the Soft
Start pin high, and the V

FFB

pin low, emulating a short

circuit condition.

Figure 14. Implementing Shutdown with the CS5156H

Shutdown

Input

5.0 V

MMUN2111T1 (SOT23)

FFB

IN4148

CS5156H

External Power Good Circuit

An optional Power Good signal can be generated through

the use of four additional external components (see Figure
15). The threshold voltage of the Power Good signal can be
adjusted per the following equation:

VPower Good

(R1

)

R2)

0.65 V

This circuit provides an open collector output that drives

the Power Good output to ground for regulator voltages less
than V

Power Good

Figure 15. Implementing Power Good with the CS5156H

5.0 V

Power Good

10 k

OUT

PN3904

6.2 k

PN3904

10 k

CS5156H

Figure 16. CS5156H Demonstration Board During

Power Up. Power Good Signal is Activated when

Output Voltage Reaches 1.70 V.

M 2.50 ms

Trace 4 5.0 V Input (2.0 V/div.)

Trace 3 12 V Input (V

CC1

) and (V

CC2

) (10 V/div.)

Trace 1 Regulator Output Voltage (1.0 V/div.)

Trace 2 Power Good Signal (2.0 V/div.)

Selecting External Components

The CS5156H can be used with a wide range of external

power components to optimize the cost and performance of
a particular design. The following information can be used
as general guidelines to assist in their selection.

NFET Power Transistors

Both logic level and standard MOSFETs can be used. The

reference designs derive gate drive from the 12 V supply
which is generally available in most computer systems and
use logic level MOSFETs.

A charge pump may be easily

implemented to permit use of standard MOSFETs or support
5.0 V or 12 V only systems (maximum of 20 V). Multiple
MOSFETs may be paralleled to reduce losses and improve
efficiency and thermal management.

Voltage applied to the MOSFET gates depends on the

application circuit used. The gate driver output is specified
to drive to within 1.5 V of ground when in the low state and
to within 2.0 V of its bias supply when in the high state. In
practice, the MOSFET gates will be driven rail to rail due to
overshoot caused by the capacitive load they present to the
controller IC. For the typical application where V

CC1

CC2

= 12 V and 5.0 V is used as the source for the regulator

output current, the following gate drive is provided;

VGATE

12 V

5.0 V

7.0 V

(see Figure 17.)

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Figure 17. CS5156H Gate Drive Waveforms Depicting

Rail to Rail Swing

M 1.00

M1 = V

GATE

5.0 V

Channel 3 = V

GATE

Channel 2 Inductor Switching Node

The most important aspect of MOSFET performance is

RDS

, which effects regulator efficiency and MOSFET

thermal management requirements.

The power dissipated by the MOSFETs and the Schottky

diode may be estimated as follows;

Switching MOSFET:

Power

ILOAD2

RDSON

duty cycle

Schottky diode:

Power

VFORWARD

ILOAD

duty cycle)

Duty Cycle =

VOUT

)

VFORWARD

VIN

)

VFORWARD

(ILOAD

RDSON OF SYNCH FET)

Off Time Capacitor (C

OFF

)

The C

OFF

timing capacitor sets the regulator off time:

TOFF

COFF

4848.5

When the V

FFB

pin is less than 1.0 V, the current charging

the C

OFF

capacitor is reduced. The extended off time can be

calculated as follows:

TOFF

COFF

24, 242.5

Off time will be determined by either the T

OFF

time, or the

time out timer, whichever is longer.

The preceding equations for duty cycle can also be used

to calculate the regulator switching frequency and select the
C

OFF

timing capacitor:

COFF

Perioid

duty cycle)

4848.5

where:

Period

switching frequency

"Droop" Resistor for Adaptive Voltage Positioning

Adaptive voltage positioning is used to reduce output

voltage excursions during abrupt changes in load current.
Regulator output voltage is offset +40 mV when the
regulator is unloaded, and 40 mV at full load. This results
in increased margin before encountering minimum and
maximum transient voltage limits, allowing use of less
capacitance on the regulator output (see Figure 9).

To implement adaptive voltage positioning, a "droop"

resistor must be connected between the output inductor and
output capacitors and load. This is normally implemented by
a PC board trace of the following value:

RDROOP

80 mV

IMAX

Adaptive voltage positioning can be disabled for

improved DC regulation by connecting the V

pin directly

to the load using a separate, nonload current carrying
circuit trace.

Input and Output Capacitors

These components must be selected and placed carefully

to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the input supply lines and
regulator output voltage. Key specifications for input
capacitors are their ripple rating, while ESR is important for
output capacitors. For best transient response, a combination
of low value/high frequency and bulk capacitors placed
close to the load will be required.

Output Inductor

The inductor should be selected based on its inductance,

current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response.

THERMAL MANAGEMENT

Thermal Considerations for Power
MOSFETs and Diodes

In order to maintain good reliability, the junction

temperature of the semiconductor components should be
kept to a maximum of 150

C or lower. The thermal

impedance (junction to ambient) required to meet this
requirement can be calculated as follows:

Thermal Impedance

TJUNCTION(MAX)

TAMBIENT

Power

A heatsink may be added to TO220 components to

reduce their thermal impedance. A number of PC board
layout techniques such as thermal vias and additional copper
foil area can be used to improve the power handling
capability of surface mount components.

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EMI Management

As a consequence of large currents being turned on and off

at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.

Figure 18. Filter Components

1000 pF

2.0

Figure 19. Input Filter

1200 pF

3.0/16 V

2.0

Layout Guidelines

1. Place 12 V filter capacitor next to the IC and connect

capacitor ground to pin 11 (PGND).

2. Connect pin 11 (PGND) with a separate trace to the

ground terminals of the 5.0 V input capacitors.

3. Place fast feedback filter capacitor next to pin 8 (V

FFB

)

and connect it's ground terminal with a separate, wide
trace directly to pin 14 (LGND).

4. Connect the ground terminals of the Compensation

capacitor directly to the ground of the fast feedback
filter capacitor to prevent common mode noise from
effecting the PWM comparator.

5. Place the output filter capacitor(s) as close to the load

as possible and connect the ground terminal to pin 14
(LGND).

6. To implement adaptive voltage positioning, connect

both slow and fast feedback pins 16 (V

) and 8

FFB

) to the regulator output right at the inductor

terminal. Connect inductor to the output capacitors via
a trace with the following resistance:

RTRACE

80 mV

IMAX

This causes the output voltage to be +40 mV with no
load, and 40 mV with a full load, improving regulator
transient response. This trace must be wide enough to
carry the full output current. (Typical trace is 1.0 inch
long, 0.17 inch wide). Care should be taken to
minimize any additional losses after the feedback
connection point to maximize regulation.

7. If DC regulation is to be optimized (at the expense of

degraded transient regulation), adaptive voltage
positioning can be disabled by connecting to V

directly to the load with a separate trace (remote
sense).

8. Place 5.0 V input capacitors close to the switching

MOSFET.

Route gate drive signals V

GATE

(pin 10) with a trace

that is a minimum of 0.025 inches wide.

Figure 20. Layout Guidelines

To the negative terminal of the output capacitors

100 pF

0.1

SOFT START

OFF TIME

COMP

To the negative terminal

of the input capacitors

FFB

1.0

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PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

SEATING

PLANE

X 45

8 PL

B

A

0.25 (0.010)

T

16 PL

0.25 (0.010)

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

9.80

10.00

0.386

0.393

3.80

4.00

0.150

0.157

1.35

1.75

0.054

0.068

0.35

0.49

0.014

0.019

0.40

1.25

0.0160.049

1.27 BSC

0.050 BSC

0.19

0.25

0.008

0.009

0.10

0.25

0.004

0.009

5.80

6.20

0.229

0.244

0.25

0.50

0.010

0.019

SO16

D SUFFIX

CASE 751B05

ISSUE J

PACKAGE THERMAL DATA

Parameter

SO16

Unit

Typical

C/W

Typical

115

C/W

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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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