Semiconductor Components Industries, LLC, 2002
April, 2002 Rev. 11
1
Publication Order Number:
CS5161/D
CS5161, CS5161H
CPU 5-Bit Synchronous
Buck Controller
The CS5161/5161H are 5bit synchronous dual NChannel buck
controllers designed to provide unprecedented transient response for
today's demanding highdensity, highspeed logic. They operate
using a proprietary control method which allows a 100 ns response
time to load transients. The CS5161 is designed to operate over a
916 V range (V
CC
) using 12 V to power the IC and 5.0 V as the main
supply for conversion.
The CS5161H operates from a 12 V input as the main supply for
conversion using a discrete charge pump circuit to provide up to 20 V
for V
CC2
and high side gate drive.
The CS5161/5161H are specifically designed to power
Pentium
III processors and other high performance core logic. They
include the following features: on board 5bit DAC, short circuit
protection, 1.0% output tolerance, V
CC
monitor, and programmable
Soft Start capability. The CS5161/5161H are available in 16 pin
surface mount packages.
Features
Dual NChannel Design
Excess of 1.0 MHz Operation
100 ns Transient Response
5Bit DAC
Backward Compatible with CS515X Family
30 ns Gate Rise/Fall Times
1.0% DAC Accuracy
5.0 V & 12 V Operation
Remote Sense
Programmable Soft Start
Lossless Short Circuit Protection
V
CC
Monitor
50 ns FET Nonoverlap Time
V
2
Control Topology
Current Sharing
Overvoltage Protection
CS5161GDR16
MARKING
DIAGRAMS
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
Device
Package
Shipping
ORDERING INFORMATION
CS5161GD16
SO16
48 Units/Rail
SO16
2500 Tape & Reel
1
COMP
V
FFB
V
FB
C
OFF
SS
V
ID0
V
CC2
V
CC1
V
GATE(L)
V
GATE(H)
PGnd
PIN CONNECTIONS
LGnd
CS5161HGD16
CS5161HGDR16
SO16
SO16
48 Units/Rail
2500 Tape & Reel
V
ID1
V
ID2
V
ID3
V
ID4
SO16
D SUFFIX
CASE 751B
1
16
CS5161
AWLYWW
http://onsemi.com
CS5161, CS5161H
http://onsemi.com
2
COMP
V
FFB
V
FB
V
GATE(H)
V
GATE(L)
V
CC2
V
CC1
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
PGnd
SS
C
OFF
CS5161
MBRS140T3
SILICONIX
Sanyo GX
12 V
680 pF
0.1
F
LGnd
1200
F/10 V 6.0
0.1
F
V
OUT
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
SILICONIX
SUD50NO307
Sanyo GX
1200
F/10 V 8.0
1.8
H
SUD50NO310P
0.33
F
1.3 k
1.0
H
5 V
Figure 1. Application Diagram,5.0 V to 1.5 V/15 A Core Logic
Converter with 12 V Bias
MAXIMUM RATINGS*
Rating
Value
Unit
Operating Junction Temperature, T
J
0 to 150
C
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
230 peak
C
Storage Temperature Range, T
S
65 to +150
C
ESD Susceptibility (Human Body Model)
2.0
kV
1. 60 second maximum above 183
C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Name
Max Operating Voltage
Max Current
V
CC1
16 V/0.3 V
100 mA DC/1.5 A peak
V
CC2
(CS5161)
18 V/0.3 V
100 mA DC/1.5 A peak
V
CC2
(CS5161H)
20 V/0.3 V
100 mA DC/1.5 A peak
SS
6.0 V/0.3 V
100
A
CS5161, CS5161H
http://onsemi.com
3
MAXIMUM RATINGS (continued)
Pin Name
Max Current
Max Operating Voltage
COMP
6.0 V/0.3 V
200
A
V
FB
6.0 V/0.3 V
0.2
A
C
OFF
6.0 V/0.3 V
0.2
A
V
FFB
6.0 V/0.3 V
0.2
A
V
ID0
V
ID4
6.0 V/0.3 V
50
A
V
GATE(H)
(CS5161)
18 V/0.3 V
100 mA DC/1.5 A peak
V
GATE(H)
(CS5161H)
20 V/0.3 V
100 mA DC/1.5 A peak
V
GATE(L)
16 V/0.3 V
100 mA DC/1.5 A peak
LGnd
0 V
25 mA
PGnd
0 V
100 mA DC/1.5 A peak
ELECTRICAL CHARACTERISTICS
(0
C < T
A
< +70
C; CS5161: 0C < T
J
< +85
C; CS5161H: 0C < T
J
< +125
C;
9.5
V < V
CC1
< 14
V; CS5161: 5.0
V < V
CC2
< 16
V; CS5161H: 5.0
V < V
CC2
< 20
V; DAC Code: V
ID4
=
V
ID2
=
V
ID1
=
V
ID0
=1; V
ID3
=
0;
CV
GATE(L)
and
CV
GATE(H)
= 1.0
nF; C
OFF
= 330 pF; C
SS
= 0.1
F, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
V
FB
Bias Current
V
FB
= 0 V
0.3
1.0
A
Open Loop Gain
1.25 V < V
COMP
, 4.0 V; C
COMP
= 0.1
F;
Note 2
80
dB
Unity Gain Bandwidth
C
COMP
= 0.1
F; Note 2
50
kHz
COMP SINK Current
V
COMP
= 1.5 V; V
FB
= 3.0 V; V
SS
> 2.0 V
30
60
120
A
COMP SOURCE Current
V
COMP
= 1.2 V; V
FB
= 2.7 V; V
SS
= 5.0 V
15
30
60
A
COMP CLAMP Current
V
COMP
= 0 V; V
FB
= 2.7 V
0.4
1.0
1.6
mA
COMP High Voltage
V
FB
= 2.7 V; V
SS
= 5.0 V
4.0
4.3
5.0
V
COMP Low Voltage
V
FB
= 3.0 V
1.0
1.15
V
PSRR
8.0 V < V
CC1
< 14 V @ 1.0 kHz;
C
COMP
= 0.1
F; Note 2
70
dB
Transconductance
33
mmho
V
CC1
Monitor
Start Threshold
Output switching
8.70
9.05
9.40
V
Stop Threshold
Output not switching
8.55
8.90
9.25
V
Hysteresis
StartStop
150
mV
Soft Start (SS)
Charge Time
1.6
3.3
5.0
ms
Pulse Period
25
100
200
ms
Duty Cycle
(Charge Time /Pulse Period)
100
1.0
3.3
6.0
%
COMP Clamp Voltage
V
FB
= 0 V; V
SS
= 0
0.50
0.95
1.10
V
V
FFB
SS Fault Disable
V
GATE(H)
= Low; V
GATE(L)
= Low
0.9
1.0
1.1
V
High Threshold
2.5
3.0
V
2. Guaranteed by design, not 100% tested in production.
CS5161, CS5161H
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS (continued)
(0
C < T
A
< +70
C; CS5161: 0C < T
J
< +85
C; CS5161H: 0C < T
J
< +125
C;
9.5
V < V
CC1
< 14
V; CS5161: 5.0
V < V
CC2
< 16
V; CS5161H: 5.0
V < V
CC2
< 20
V; DAC Code: V
ID4
=
V
ID2
=
V
ID1
=
V
ID0
=1; V
ID3
=
0;
CV
GATE(L)
and
CV
GATE(H)
= 1.0
nF; C
OFF
= 330 pF; C
SS
= 0.1
F, unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
PWM Comparator
Transient Response
V
FFB
= 0 to 5.0 V to V
GATE(H)
= 9.0 V to 1.0 V;
V
CC1
= V
CC2
= 12 V
100
125
ns
V
FFB
Bias Current
V
FFB
= 0 V
0.3
A
DAC
Input Threshold
V
ID0,
V
ID1
, V
ID2
, V
ID3
, V
ID4
1.00
1.25
2.40
V
Input Pull Up Resistance
V
ID0,
V
ID1
, V
ID2
, V
ID3
, V
ID4
25
50
110
k
Pull Up Voltage
4.85
5.00
5.15
V
Accuracy (all codes except 11111,
10110, 10101, 10100, 10011,
10010, 10001, 10000)
Measure V
FB
= COMP,
CS5161: 25
C T
J
85C
CS5161H: 25
C T
J
125C
1.0
%
V
ID4
V
ID3
V
ID2
V
ID1
V
ID0
0
1
1
1
1
1.2870
1.3000
1.3130
V
0
1
1
1
0
1.3365
1.3500
1.3635
V
0
1
1
0
1
1.3860
1.4000
1.4140
V
0
1
1
0
0
1.4355
1.4500
1.4645
V
0
1
0
1
1
1.4850
1.5000
1.5150
V
0
1
0
1
0
1.5345
1.5500
1.5655
V
0
1
0
0
1
1.5840
1.6000
1.6160
V
0
1
0
0
0
1.6335
1.6500
1.6665
V
0
0
1
1
1
1.6830
1.7000
1.7170
V
0
0
1
1
0
1.7325
1.7500
1.7675
V
0
0
1
0
1
1.7820
1.8000
1.8180
V
0
0
1
0
0
1.8315
1.8500
1.8685
V
0
0
0
1
1
1.8810
1.9000
1.9190
V
0
0
0
1
0
1.9305
1.9500
1.9695
V
0
0
0
0
1
1.9800
2.0000
2.0200
V
0
0
0
0
0
2.0295
2.0500
2.0705
V
1
1
1
1
1
1.2191
1.2440
1.2689
V
1
1
1
1
0
2.0790
2.1000
2.1210
V
1
1
1
0
1
2.1780
2.2000
2.2220
V
1
1
1
0
0
2.2770
2.3000
2.3230
V
1
1
0
1
1
2.3760
2.4000
2.4240
V
1
1
0
1
0
2.4750
2.5000
2.5250
V
1
1
0
0
1
2.5740
2.6000
2.6260
V
1
1
0
0
0
2.6730
2.7000
2.7270
V
1
0
1
1
1
2.7720
2.8000
2.8280
V
1
0
1
1
0
2.8420
2.9000
2.9580
V
1
0
1
0
1
2.9400
3.0000
3.0600
V
CS5161, CS5161H
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS (continued)
(0
C < T
A
< +70
C; CS5161: 0C < T
J
< +85
C; CS5161H: 0C < T
J
< +125
C;
9.5
V < V
CC1
< 14
V; CS5161: 5.0
V < V
CC2
< 16
V; CS5161H: 5.0
V < V
CC2
< 20
V; DAC Code: V
ID4
=
V
ID2
=
V
ID1
=
V
ID0
=1; V
ID3
=
0;
CV
GATE(L)
and
CV
GATE(H)
= 1.0
nF; C
OFF
= 330 pF; C
SS
= 0.1
F, unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
DAC
1
0
1
0
0
3.0380
3.1000
3.1620
V
1
0
0
1
1
3.1360
3.2000
3.2640
V
1
0
0
1
0
3.2340
3.3000
3.3660
V
1
0
0
0
1
3.3320
3.4000
3.4680
V
1
0
0
0
0
3.4300
3.5000
3.5700
V
V
GATE(H)
and V
GATE(L)
Out SOURCE Sat at 100 mA
Measure V
CC1
V
GATE(L)
; V
CC2
V
GATE(H)
1.2
2.0
V
Out SINK Sat at 100 mA
Measure V
GATE(H)
V
PGnd
; V
GATE(L)
V
PGnd
1.0
1.5
V
Out Rise Time
1.0 V < V
GATE(H)
< 9.0 V; 1.0 V < V
GATE(L)
< 9.0 V; V
CC1
= V
CC2
= 12 V
30
50
ns
Out Fall Time
9.0 V < V
GATE(H)
> 1.0 V; 9.0 V > V
GATE(L)
> 1.0 V; V
CC1
= V
CC2
= 12 V
30
50
ns
Delay V
GATE(H)
to V
GATE(L)
V
GATE(H)
falling to 2.0 V
;
V
CC1
= V
CC2
= 8.0 V
V
GATE(L)
rising to 2.0 V
20
50
90
ns
Delay V
GATE(L)
to V
GATE(H)
V
GATE(L)
falling to 2.0 V; V
CC1
= V
CC2
= 8.0 V
V
GATE(H)
rising to 2.0 V
20
50
90
ns
V
GATE(H),
V
GATE(L)
Resistance
Resistor to LGnd. Note 3
20
50
100
k
V
GATE(H),
V
GATE(L)
Schottky
LGnd to V
GATE(H)
@ 10 mA;
LGnd to V
GATE(L)
@ 10 mA
600
800
mV
Supply Current
I
CC1
No Switching
9.5
14.5
mA
I
CC2
No Switching
2.0
3.5
mA
Operating I
CC1
V
FB
= COMP = V
FFB
9.0
14
mA
Operating I
CC2
V
FB
= COMP = V
FFB
2.5
5.5
mA
C
OFF
Normal Charge Time
V
FFB
= 1.5 V; V
SS
= 5.0 V
1.0
1.6
2.2
s
Discharge Current
C
OFF
to 5.0 V; V
FB
> 1.0 V
5.0
mA
Time Out Timer
Time Out Time
V
FB
= V
COMP
; V
FFB
= 2.0 V;
Record V
GATE(H)
Pulse High Duration
10
30
65
s
Fault Mode Duty Cycle
V
FFB
= 0V
35
50
70
%
3. Guaranteed by design, not 100% tested in production.
CS5161, CS5161H
http://onsemi.com
6
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
1, 2, 3, 4, 6
V
ID0
V
ID4
Voltage ID DAC input pins. These pins are internally pulled
up to 5.0 V providing logic ones if left open. V
ID4
selects the
DAC range. When V
ID4
is High (logic one), the DAC range
is 2.10 V to 3.50 V with 100 mV increments. When V
ID4
is
Low (logic zero), the DAC range is 1.30 V to 2.05 V with
50 mV increments. V
ID0
V
ID4
select the desired DAC out-
put voltage. Leaving all 5 DAC input pins open results in a
DAC output voltage of 1.2440 V, allowing for adjustable
output voltage, using a traditional resistor divider.
5
SS
Soft Start Pin. A capacitor from this pin to LGnd in conjunc-
tion with internal 60
A current source provides Soft Start
function for the controller. This pin disables fault detect func-
tion during Soft Start. When a fault is detected, the Soft Start
capacitor is slowly discharged by internal 2.0
A current
source setting the time out before trying to restart the IC.
Charge/discharge current ratio of 30 sets the duty cycle for
the IC when the regulator output is shorted.
7
C
OFF
A capacitor from this pin to ground sets the time duration for
the on board one shot, which is used for the constant off time
architecture.
8
V
FFB
Fast feedback connection to the PWM comparator. This pin
is connected to the regulator output. The inner feedback loop
terminates on time.
9
V
CC2
Boosted power for the high side gate driver.
10
V
GATE(H)
High FET driver pin capable of 1.5 A peak switching current.
Internal circuit prevents V
GATE(H)
and V
GATE(L)
from being in
high state simultaneously.
11
PGnd
High current ground for the IC. The MOSFET drivers are
referenced to this pin. Input capacitor ground and the source
of lower FET should be tied to this pin.
12
V
GATE(L)
Low FET driver pin capable of 1.5 A peak switching current.
13
V
CC1
Input power for the IC and low side gate driver.
14
LGnd
Signal ground for the IC. All control circuits are referenced to
this pin.
15
COMP
Error amplifier compensation pin. A capacitor to ground
should be provided externally to compensate the amplifier.
16
V
FB
Error amplifier DC feedback input. This is the master voltage
feedback which sets the output voltage. This pin can be con-
nected directly to the output or a remote sense trace.
CS5161, CS5161H
http://onsemi.com
7
+
+
+
V
CC1
SS
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
V
FFB
Low
Comparator
V
FFB
Fast Feedback
LGnd
Slow Feedback
PWM
Comparator
SS Low
Comparator
SS High
Comparator
5 BIT
DAC
V
CC1
Monitor
Comparator
Error
Amplifier
V
CC1
V
CC2
C
OFF
V
GATE(H)
V
GATE(L)
PGnd
FAULT
FAULT
FAULT
Latch
PGnd
R
S
Q
Q
R
S
Q
Q
R
S
Q
Latch
PMW
C
OFF
One Shot
OffTime
Timeout
TimeOut
Timer
Edge Triggered
Extended
OffTime
Timeout
Normal
OffTime
Timeout
Maximum
OnTime
Timeout
(30
s)
GATE(H) = ON
GATE(H) = OFF
2.0
A
60
A
5.0 V
0.7 V
2.5 V
1.0 V
+
+
+
9.05 V
8.90V
V
FB
COMP
Figure 2. Block Diagram
APPLICATIONS INFORMATION
THEORY OF OPERATION
V
2
Control Method
The V
2
method of control uses a ramp signal that is
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is
generated from the output voltage itself. This control
scheme differs from traditional techniques such as voltage
mode, which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
Figure 3. V
2
Control Diagram
COMP
V
FFB
Reference
Voltage
+
+
PWM
Comparator
Ramp
Signal
Error
Amplifier
Error
Signal
Output
Voltage
Feedback
V
FB
V
GATE(H)
V
GATE(L)
E
C
CS5161, CS5161H
http://onsemi.com
8
The V
2
control method is illustrated in Figure 3. The
output voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regardless
of the origin of that change. The ramp signal also contains
the DC portion of the output voltage, which allows the
control circuit to drive the main switch to 0% or 100% duty
cycle as required.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V
2
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V
2
control scheme has the same
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined only
by the comparator response time and the transition speed of
the main switch. The reaction time to an output load step has
no relation to the crossover frequency of the error signal
loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
The main purpose of this `slow' feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote
sensing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains fixed error signal under
deviation in the line voltage, since the slope of the ramp
signal changes, but still relies on a change in the error signal
for a deviation in load. The V
2
method of control maintains
a fixed error signal for both line and load variation, since the
ramp signal is affected by both line and load.
Constant Off Time
To maximize transient response, the CS5161/5161H uses
a constant off time method to control the rate of output
pulses. During normal operation, the off time of the high side
switch is terminated after a fixed period, set by the C
OFF
capacitor. To maintain regulation, the V
2
control loop varies
switch on time. The PWM comparator monitors the output
voltage ramp, and terminates the switch on time.
Constant off time provides a number of advantages.
Switch duty cycle can be adjusted from 0 to 100% on a pulse
by pulse basis when responding to transient conditions. Both
0% and 100% duty cycle operation can be maintained for
extended periods of time in response to load or line
transients. PWM slope compensation to avoid
subharmonic oscillations at high duty cycles is avoided.
Switch on time is limited by an internal 30
s timer,
minimizing stress to the power components.
Programmable Output
The CS5161/5161H is designed to provide two methods
for programming the output voltage of the power supply. A
five bit on board digital to analog converter (DAC) is used
to program the output voltage within two different ranges.
The first range is 2.10 V to 3.50 V in 100 mV steps, the
second is 1.30 V to 2.05 V in 50 mV steps, depending on the
digital input code. If all five bits are left open, the
CS5161/5161H enters adjust mode. In adjust mode, the
designer can choose any output voltage by using resistor
divider feedback to the V
FB
and V
FFB
pins, as in traditional
controllers.
Start Up
Until the voltage on the V
CC1
supply pin exceeds the
9.05 V monitor threshold, the Soft Start and gate pins are
held low. The FAULT latch is reset (no Fault condition). The
output of the error amplifier (COMP) is pulled up to 1.0 V
by the comparator clamp. When the V
CC1
pin exceeds the
monitor threshold, the GATE(H) output is activated, and the
Soft Start capacitor begins charging. The GATE(H) output
will remain on, enabling the NFET switch, until terminated
by either the PWM comparator, or the maximum on time
timer.
If the maximum on time is exceeded before the regulator
output voltage achieves the 1.0 V level, the pulse is
terminated. The GATE(H) pin drives low, and the GATE(L)
pin drives high for the duration of the extended off time. This
time is set by the time out timer and is approximately equal
to the maximum on time, resulting in a 50% duty cycle. The
GATE(L) pin will then drive low, the GATE(H) pin will
drive high, and the cycle repeats.
When regulator output voltage achieves the 1.0 V level
present at the COMP pin, regulation has been achieved and
normal off time will ensue. The PWM comparator
terminates the switch on time, with off time set by the C
OFF
capacitor. The V
2
control loop will adjust switch duty cycle
as required to ensure the regulator output voltage tracks the
output of the error amplifier.
The Soft Start and COMP capacitors will charge to their
final levels, providing a controlled turn on of the regulator
output. Regulator turn on time is determined by the COMP
CS5161, CS5161H
http://onsemi.com
9
capacitor charging to its final value. Its voltage is limited by
the Soft Start COMP clamp and the voltage on the Soft Start
pin (see Figures 4 and 5).
Figure 4. CS5161/5161H Startup in Response to
Increasing 12 V and 5.0 V Input Voltages. Extended Off
Time is Followed by Normal Off Time Operation when
Output Voltage Achieves Regulation to the Error
Amplifier Output.
M 250
s
Trace 3 12 V Input (VCC1 and VCC2) (5.0 V/div.)
Trace 1 Regulator Output Voltage (1.0 V/div.)
Trace 4 5.0 V Input (1.0 V/div.)
Trace 2 Inductor Switching Node (2.0 V/div.)
Figure 5. CS5161/5161H Startup Waveforms
M 2.50 ms
Trace 3 COMP PIn (error amplifier output) (1.0 V/div.)
Trace 1 Regulator Output Voltage (1.0 V/div.)
Trace 4 Soft Start Pin (2.0 V/div.)
If the input voltage rises quickly, or the regulator output
is enabled externally, output voltage will increase to the
level set by the error amplifier output more rapidly, usually
within a couple of cycles (see Figure 6).
Figure 6. CS5161/5161H Enable Startup Waveforms
M 10.0
s
Trace 1 Regulator Output Voltage (5.0 V/div.)
Trace 2 Inductor Switching Node (5.0 V/div.)
Normal Operation
During normal operation, switch off time is constant and
set by the C
OFF
capacitor. Switch on time is adjusted by the
V
2
control loop to maintain regulation. This results in
changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
working into the ESR of the output capacitors (see Figures
7 and 8).
Figure 7. CS5161/5161H PeaktoPeak Ripple on
V
OUT
= 2.8 V, I
OUT
= 0.5 A (Light Load)
M 1.00
s
Trace 1 Regulator Output Voltage (10 mV/div.)
Trace 2 Inductor Switching Node (5.0 V/div.)
CS5161, CS5161H
http://onsemi.com
10
Figure 8. CS5161/5161H PeaktoPeak Ripple on
V
OUT
= 2.8 V, I
OUT
= 13 A (Heavy Load)
M 1.00
s
Trace 1 Regulator Output Voltage (10 mV/div.)
Trace 2 Inductor Switching Node (5.0 V/div.)
Transient Response
The CS5161/5161H V
2
control loop's 100 ns reaction
time provides unprecedented transient response to changes
in input voltage or output current. Pulse by pulse adjustment
of duty cycle is provided to quickly ramp the inductor
current to the required level. Since the inductor current
cannot be changed instantaneously, regulation is maintained
by the output capacitor(s) during the time required to slew
the inductor current.
For best transient response, a combination of a number of
high frequency and bulk output capacitors are usually used.
If the maximum on time is exceeded while responding to
a sudden increase in load current, a normal off time occurs
to prevent saturation of the output inductor.
Figure 9. CS5161/5161H Pentium
III Converter
Output
Voltage Response to a 12 A Load Pulse.
100
s/div.
Trace 2 Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Figure 10. CS5161/5161H Pentium
III Converter
Output
Voltage Response to a 0 to 12 A Load Increase
10
s/div.
Trace 2 Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Trace 1 Inductor Switching Node (5.0 V/div.)
Figure 11. CS5161/5161H Pentium
III Converter Output
Voltage Response to a 12 to 0 A Load Decrease
10
s/div.
Trace 2 Regulator Output Voltage (output set for 1.55 V, 20 mV/div.)
Trace 1 Inductor Switching Node (5 V/div.)
PROTECTION AND MONITORING FEATURES
V
CC1
Monitor
To maintain predictable startup and shutdown
characteristics an internal V
CC1
monitor circuit is used to
prevent the part from operating below 8.70 V minimum
startup. The V
CC1
monitor comparator provides hysteresis
and guarantees a 8.55 V minimum shutdown threshold.
Short Circuit Protection
A lossless hiccup mode short circuit protection feature is
provided, requiring only the Soft Start capacitor to
implement. If a short circuit condition occurs
(V
FFB
< 1.0 V), the V
FFB
low comparator sets the FAULT
CS5161, CS5161H
http://onsemi.com
11
latch. This causes the top MOSFET to shut off,
disconnecting the regulator from it's input voltage. The Soft
Start capacitor is then slowly discharged by a 2.0
A current
source until it reaches it's lower 0.7 V threshold. The
regulator will then attempt to restart normally, operating in
it's extended off time mode with a 50% duty cycle, while the
Soft Start capacitor is charged with a 60
A charge current.
If the short circuit condition persists, the regulator output
will not achieve the 1.0 V low V
FFB
comparator threshold
before the Soft Start capacitor is charged to it's upper 2.5 V
threshold. If this happens the cycle will repeat itself until the
short is removed. The Soft Start charge/discharge current
ratio sets the duty cycle for the pulses
(2.0
A/60 A = 3.3%), while actual duty cycle is half that
due to the extended off time mode (1.65%).
This protection feature results in less stress to the
regulator components, input power supply, and PC board
traces than occurs with constant current limit protection (see
Figures 12 and 13).
If the short circuit condition is removed, output voltage
will rise above the 1.0 V level, preventing the FAULT latch
from being set, allowing normal operation to resume.
Figure 12. CS5161/5161H Hiccup Mode Short Circuit
Protection. Gate Pulses are Delivered While the Soft
Start Capacitor Charges, and Cease During Discharge
M 25.0 ms
Trace 3 Soft Start Timing Capacitor (1.0 V/div.)
Trace 4 5.0 V Supply Voltage (2.0 V/div.)
Trace 2 Inductor Switching Node (2.0 V/div.)
Figure 13. CS5161/5161H Startup with Regulator
Output Shorted
M 50.0
s
Trace 4 5.0 V from PC Power Supply (2.0 V/div.)
Trace 2 Inductor Switching Node (2.0 V/div.)
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V
2
control topology and requires no
additional external components. The control loop responds
to an overvoltage condition within 100 ns, causing the top
MOSFET to shut off, disconnecting the regulator from it's
input voltage. The bottom MOSFET is then activated,
resulting in a "crowbar" action to clamp the output voltage
and prevent damage to the load (see Figures 14 and 15). The
regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low. The
bottom FET and board trace must be properly designed to
implement the OVP function.
Figure 14. CS5161/5161H OVP Response to an
InputtoOutput Short Circuit by Immediately
Providing 0% Duty Cycle, CrowBarring the Input
Voltage to Ground
M 10.0
s
Trace 1 Regulator Output Voltage (1.0 V/div.)
Trace 2 Inductor Switching Node 5.0 V/div.)
Trace 4 5.0 V from PC Power Supply (5.0 V/div.)
CS5161, CS5161H
http://onsemi.com
12
Figure 15. CS5161/5161H OVP Response to an
InputtoOutput Short Circuit by Pulling the Input
Voltage to Ground
M 5.00 ms
Trace 1 Regulator Output Voltage (1.0 V/div.)
Trace 4 5.0 V from PC Power Supply (5.0 V/div.)
External Output Enable Circuit
On/off control of the regulator can be implemented
through the addition of two additional discrete components
(see Figure 16). This circuit operates by pulling the Soft
Start pin high, and the V
FFB
pin low, emulating a short
circuit condition.
Figure 16. Implementing Shutdown
with the CS5161/5161H
Shutdown
Input
5.0 V
MMUN2111T1 (SOT23)
5
8
V
FFB
SS
IN4148
CS5161
External Power Good Circuit
An optional Power Good signal can be generated through
the use of four additional external components (see Figure
17). The threshold voltage of the Power Good signal can be
adjusted per the following equation:
VPower Good +
(R1
) R2) 0.65 V
R2
This circuit provides an open collector output that drives
the Power Good output to ground for regulator voltages less
than V
Power Good
.
Figure 17. Implementing Power Good
with the CS5161/5161H
5.0 V
Power Good
10 k
V
OUT
PN3904
6.2 k
R1
R2
PN3904
10 k
R3
CS5161
Figure 18. CS5161/5161H During Power Up. Power
Good Signal is Activated when Output Voltage
Reaches 1.70 V.
M 2.50 ms
Trace 4 5.0 V Input (2.0 V/div.)
Trace 3 12 V Input (V
CC1
) and (V
CC2
) (10 V/div.)
Trace 1 Regulator Output Voltage (1.0 V/div.)
Trace 2 Power Good Signal (2.0 V/div.)
Slope Compensation
The V
2
control method uses a ramp signal, generated by
the ESR of the output capacitors, that is proportional to the
ripple current through the inductor. To maintain regulation,
the V
2
control loop monitors this ramp signal, through the
PWM comparator, and terminates the switch ontime.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope presented to the PWM
comparator, due to the very low ESR, can lead to pulse width
jitter and variation caused by both random or synchronous
noise.
Adding slope compensation to the control loop, avoids
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switchpoint.
The scheme that prevents that switching noise
prematurely triggers the PWM circuit consists of adding a
positive voltage slope to the output of the Error Amplifier
(COMP pin) during an offtime cycle.
CS5161, CS5161H
http://onsemi.com
13
The circuit that implements this function is shown in
Figure 19.
Figure 19. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
each OnTime Cycle
To Synchronous
FET
16
V
OUT
12
C1
R2
R1
CS5161
GATE(L)
COMP
C
COMP
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each ontime cycle. The resistors R1 and R2 in the circuit of
Figure 14 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier. It is important that the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) pin.
Selecting External Components
The CS5161/5161H can be used with a wide range of
external power components to optimize the cost and
performance of a particular design. The following
information can be used as general guidelines to assist in
their selection.
NFET Power Transistors
Both logic level and standard MOSFETs can be used. The
reference designs derive gate drive from the 12 V supply
which is generally available in most computer systems and
utilize logic level MOSFETs. Multiple MOSFETs may be
paralleled to reduce losses and improve efficiency and
thermal management.
Voltage applied to the MOSFET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the MOSFET
gates will be driven rail to rail due to overshoot caused by the
capacitive load they present to the controller IC. For the
typical application where V
CC1
= V
CC2
= 12 V and 5.0 V is
used as the source for the regulator output current, the
following gate drive is provided;
VGATE(H) + 12 V * 5.0 V + 7.0 V, VGATE(L) + 12 V
(see Figure 20.)
Figure 20. CS5161/5161H Gate Drive Waveforms
Depicting Rail to Rail Swing
M 1.00
s
Math 1 = V
GATE(H)
5.0 V
IN
Trace 3 = V
GATE(H)
(10 V/div.)
Trace 4 = V
GATE(L)
(10 V/div.)
Trace 2 Inductor Switching Nodes (5.0 V/div.)
The most important aspect of MOSFET performance is
RDS
ON
, which effects regulator efficiency and MOSFET
thermal management requirements.
The power dissipated by the MOSFETs may be estimated
as follows;
Switching MOSFET:
Power
+ ILOAD2 RDSON duty cycle
Synchronous MOSFET:
Power
+ ILOAD2 RDSON (1 * duty cycle)
Duty Cycle =
VOUT ) (ILOAD RDSON OF SYNCH FET)
VIN)(ILOAD RDSON OF SYNCH FET)
* (ILOAD RDSON OF SWITCH FET)
Off Time Capacitor (C
OFF
)
The C
OFF
timing capacitor sets the regulator off time:
TOFF + COFF 4848.5
The preceding equations for duty cycle can also be used
to calculate the regulator switching frequency and select the
C
OFF
timing capacitor:
COFF +
Perioid
(1 * duty cycle)
4848.5
where:
Period
+
1
switching frequency
CS5161, CS5161H
http://onsemi.com
14
Schottky Diode for Synchronous MOSFET
A Schottky diode may be placed in parallel with the
synchronous MOSFET to conduct the inductor current upon
turn off of the switching MOSFET to improve efficiency.
For a design operating at 200 kHz or so, the low nonoverlap
time combined with Schottky forward recovery time may
make the benefits of this device not worth the additional
expense (see Figure 8, channel 2). The power dissipation in
the synchronous MOSFET due to body diode conduction
can be estimated by the following equation:
Power
+ VBD ILOAD conduction time switching frequency
Where V
BD
= the forward drop of the MOSFET body
diode. For the CS5161/5161H demonstration board as
shown in Figure 8;
Power
+ 1.6 V 13 A 100 ns 233 kHz + 0.48 W
This is only 1.3% of the 36.4 W being delivered to the
load.
Input and Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the input supply lines and
regulator output voltage. Key specifications for input
capacitors are their ripple rating, while ESR is important for
output capacitors. For best transient response, a combination
of low value/high frequency and bulk capacitors placed
close to the load will be required.
Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response.
THERMAL MANAGEMENT
Thermal Considerations for Power
MOSFETs and Diodes
In order to maintain good reliability, the junction
temperature of the semiconductor components should be
kept to a maximum of 150
C or lower. The thermal
impedance (junction to ambient) required to meet this
requirement can be calculated as follows:
Thermal Impedance
+
TJUNCTION(MAX) * TAMBIENT
Power
A heatsink may be added to TO220 components to
reduce their thermal impedance. A number of PC board
layout techniques such as thermal vias and additional copper
foil area can be used to improve the power handling
capability of surface mount components.
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
Figure 21. Filter Components
1000 pF
33
2.0
H
Figure 22. Input Filter
1200 pF
3.0/16 V
2.0
H
+
CS5161, CS5161H
http://onsemi.com
15
Layout Guidelines
1. Place 12 V filter capacitor next to the IC and connect
capacitor ground to pin 11 (PGnd).
2. Connect pin 11 (PGnd) with a separate trace to the
ground terminals of the 5.0 V input capacitors.
3. Place fast feedback filter capacitor next to pin 8 (V
FFB
)
and connect it's ground terminal with a separate, wide
trace directly to pin 14 (LGnd).
4. Connect the ground terminals of the Compensation
capacitor directly to the ground of the fast feedback
filter capacitor to prevent common mode noise from
effecting the PWM comparator.
5. Place the output filter capacitor(s) as close to the load
as possible and connect the ground terminal to pin 14
(LGnd).
6. Connect the V
FB
pin directly to the load with a separate
trace (remote sense).
7. Place 5.0 V input capacitors close to the switching
MOSFET and synchronous MOSFET.
Route gate drive signals V
GATE(H)
(pin 10) and
V
GATE(L)
(pin 12 when used) with traces that are a
minimum of 0.025 inches wide.
Figure 23. Layout Guidelines
To the negative terminal of the output capacitors
V
CC
100 pF
0.1
F
SOFT START
OFF TIME
V
COMP
To the negative terminal
of the input capacitors
15
11
5
8
V
FFB
1.0
F
CS5161, CS5161H
http://onsemi.com
16
ADDITIONAL APPLICATION DIAGRAMS
Figure 24. 12 V to 3.3 V/10 A Converter with Remote Sense and Current Sharing
COMP
V
FFB
V
FB
V
GATE(H)
V
GATE(L)
V
CC2
V
CC1
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
PGnd
SS
C
OFF
CS5161
MBRS140T3
Si4410
Si9410
Tantalum
Tantalum
3.3 V/10 A
10
12 V
0.1
F
300 pF
0.1
F
033
F
LGnd
100 pF
3.3 k
100
F/10 V 3.0
Connect to other
circuits for current
sharing
1.0
F
1.0
F
MBRS120
MBRS120
100
F/10 V 3.0
1.0
F
Remote
Sense
MBRS
120
3.0
H
+
+
COMP
V
FFB
PGnd
V
GATE(H)
V
FB
V
CC2
V
CC1
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
V
GATE(L)
SS
C
OFF
CS5161
MBRS140T3
3.3 V
330 pF
0.33
F
LGnd
33
F/25 V 3.0
5.0
H
Si9410
1.0
F
3.3 k
0.1
F
100 pF
12 V
2.5 V/7.0 A
100
F/10 V 2.0
Tantalum
Si9410
Tantalum
Figure 25. 3.3 V to 2.5 V/7.0 A Converter with 12 V Bias.
CS5161, CS5161H
http://onsemi.com
17
ADDITIONAL APPLICATION DIAGRAMS
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
COMP
V
FFB
V
FB
V
GATE(H)
V
GATE(L)
V
CC2
V
CC1
V
ID0
V
ID1
V
ID2
V
ID3
V
ID4
PGnd
SS
C
OFF
CS5161
MBRS140T3
5.0 V
680 pF
0.1
F
LGnd
1200
F/10 V 6.0
1.0
H
SILICONIX
1.0
F
00.1
F
100
10 k
500 k
SILICONIX
SUD50NO310P
SUD50NO307
0.1
F
0.1
F
12 V
1.8
H
V
OUT
Sanyo GX
1200
F/10 V 8.0
Sanyo GX
Figure 26. Pentium
III Converter with Slope Compensation and Adaptive Voltage Positioning
10 k
30 nF
CS5161, CS5161H
http://onsemi.com
18
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
B
A
M
0.25 (0.010)
B
S
T
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.0160.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
SO16
D SUFFIX
CASE 751B05
ISSUE J
PACKAGE THERMAL DATA
Parameter
16 Lead SO Narrow
Unit
R
JC
Typical
28
C/W
R
JA
Typical
115
C/W
CS5161, CS5161H
http://onsemi.com
19
Notes
CS5161, CS5161H
http://onsemi.com
20
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4321 NishiGotanda, Shinagawaku, Tokyo, Japan 1410031
Phone: 81357402700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
CS5161/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 8002829855 Toll Free USA/Canada
V
2
is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
PDF 
ZIP