Semiconductor Components Industries, LLC, 2004
January, 2004 - Rev. 6
1
Publication Order Number:
CS5233-3/D
CS5233-3
500 mA and 1.5 A, 3.3 V
Dual Input Linear Regulator
with Auxiliary Control
The CS5233-3 provides a glitch-free 3.3 V output from one of three
possible supplies, (V
IN
, V
SB
and 3.3 V
AUX
). An on-chip linear
regulator powers the output when either V
IN
or V
SB
is available.
Otherwise AuxDrv turns on an external PFET, which connects the
3.3 V
AUX
supply to the output. The CS5233-3 is intended to provide
power to an ASIC on a PCI Network Interface Card (NIC), and meets
Intel's "Instantly Available" power requirements which follow from
the Advanced Configuration and Power Interface (ACPI) standards.
Other applications include desktop computers, power supplies with
multiple input sources, and PCMCIA interface cards.
The CS5233-3 linear regulator provides a fixed 3.3 V output at up
to 1.5 A with an overall accuracy of
2%. The internal NPN - PNP
composite pass transistor provides a low dropout voltage and requires
less supply current than a straight PNP design. Full protection with
both current limit and thermal shutdown is provided. Designed for low
reverse current, the IC prevents excessive current from flowing from
V
OUT
to either V
IN
or ground when the regulator input voltage is
lower than the output. The auxiliary drive control feature allows the
use of an external PFET to supply power to the output when the
regulator supplies are off.
The CS5233-3 regulator is available in two package types: the 5
Lead D
2
PAK package (TO-263) and SOIC-8 with 4 Lead Fused
(DF8) package. When powered from the V
IN
source, the D
2
PAK-5 is
rated for 1.5 A and the SOIC-8 is rated for 500 mA. Both packages are
rated for 500 mA when only powered from the V
SB
source.
Features
Linear Regulator
-
3.3 V
2% Output Voltage
-
Current Limit
-
Thermal Shutdown with Hysteresis
-
400
mA Reverse Current
-
ESD Protected
System Power Management
-
Auxiliary Supply Control
-
"Glitch Free" Transition Between 3 Sources
-
Similar to CS5231-3
High Output Current Capability
-
1.5 A D
2
PAK-5
-
500 mA SOIC-8 DF8
Internally Fused Leads in SOIC-8 Package
http://onsemi.com
PIN CONNECTIONS AND
MARKING DIAGRAMS
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
Device
Package
Shipping
ORDERING INFORMATION
CS5233-3GDP5
D
2
PAK-5
50 Units/Rail
CS5233-3GDPR5
D
2
PAK-5
750 Tape & Reel
CS5233-3GDF8
SOIC-8
95 Units/Rail
CS5233-3GDFR8
SOIC-8
2500 Tape & Reel
SOIC-8
D SUFFIX
CASE 751
Pin 1. V
SB
2. V
IN
3. GND
4. V
OUT
5. AuxDrv
D
2
PAK-5
DP SUFFIX
CASE 936AC
CS5233-3
AWLYWW
1
1
5
GND
AuxDrv
1
5233-
AL
YW3
8
GND
V
OUT
GND
V
IN
GND
V
SB
1
8
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
CS5233-3
http://onsemi.com
2
+
+
+
+3.3 V
AUX
V
SB
V
IN
GND
10
m
F min
ESR < 1.0
W
10
m
F min
ESR < 1.0
W
10
m
F min
ESR < 1.0
W
V
SB
V
IN
GND
AuxDrv
V
OUT
CS5233-3
ASIC
V
DD
D
S
G
Figure 1. Application Diagram, 5.0 V to 3.3 V Dual Input Regulator with Auxiliary PFET Power Switch
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
Operating Junction Temperature
150
C
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
230 peak
C
Storage Temperature Range
-65 to +150
C
ESD Susceptibility (Human Body Model)
2.0
kV
1. 60 second maximum above 183
C.
*The maximum package power dissipation must be observed.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Pin Symbol
V
MAX
V
MIN
I
SOURCE
I
SINK
IC Power Input (Main)
V
IN
6.0 V
-0.3 V
100 mA
Internally Limited
IC Power Input (Standby)
V
SB
6.0 V
-0.3 V
100 mA
Internally Limited
Output Voltage
V
OUT
6.0 V
-0.3 V
Internally Limited
100 mA
Auxiliary Drive Output
AuxDrv
6.0 V
-0.3 V
10 mA
50 mA
IC Ground
GND
N/A
N/A
N/A
N/A
ELECTRICAL CHARACTERISTICS
(0
C < T
A
< 70
C; 0
C < T
J
< 150
C; 4.75
V < V
IN
; V
SB
< 6.0 V; C
OUT
10
m
F
with ESR < 1.0
W
, I
OUT
= 10 mA; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Linear Regulator
Output Voltage
10 mA < I
OUT
< I
MAX
. (Note 2)
3.234 - 2%
3.3
3.366 + 2%
V
Line Regulation
I
OUT
= 10mA; V
SOURCE
= 4.75 V to 6.0 V.
(Note 3)
-
1.0
5.0
mV
Load Regulation
V
SOURCE
= 5.0 V; I
OUT
= 10 mA to I
MAX
.
(Notes 2, 3)
-
5.0
15
mV
2. I
MAX
= 1.5 A for D
2
PAK-5 only and with V
IN
> 4.75 V, otherwise I
MAX
= 500 mA.
3. Applies to either V
IN
or V
SB
.
CS5233-3
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (continued)
(0
C < T
A
< 70
C; 0
C < T
J
< 150
C; 4.75
V < V
IN
; V
SB
< 6.0 V; C
OUT
10
m
F
with ESR < 1.0
W
, I
OUT
= 10 mA; unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
Linear Regulator
Ground Current
I
OUT
= 10 mA
I
OUT
= 500 mA
I
OUT
= 1.5 A (Note 4)
-
-
-
2.0
3.0
9.0
3.0
6.0
20
mA
mA
mA
Reverse Current
V
SOURCE
= 0 V; V
OUT
= 3.3 V (Note 4)
-
0.4
1.0
mA
Current Limit V
IN
Input
SOIC-8
D
2
PAK-5
0 V < V
OUT
< 3.2 V
V
IN
> 4.25 V
0.55
1.6
0.8
2.4
1.3
4.5
A
A
Current Limit V
SB
Input Either
Package
0 V < V
OUT
< 3.2 V; V
IN
< 4.25 V; V
SB
> 4.25 V
0.55
0.8
1.3
A
Thermal Shutdown
(Note 5)
150
180
210
C
Thermal Shutdown Hysteresis
(Note 5)
-
25
-
C
Auxiliary Drive
V
IN
Turn-On Threshold
V
SB
= 0 V; Ramp V
IN
up until AuxDrv goes high
and regulator turns on
4.35
4.5
4.65
V
V
IN
Turn-Off Threshold
V
SB
= 0 V; Ramp V
IN
down until AuxDrv goes
low and regulator turns off
4.25
4.4
4.55
V
V
SB
Turn-On Threshold
V
SB
= 0 V; Ramp V
SB
up until AuxDrv goes high
and regulator turns on
4.35
4.5
4.65
V
V
SB
Turn-Off Threshold
V
SB
= 0 V; Ramp V
SV
down until AuxDrv goes
low and regulator turns off
4.25
4.4
4.55
V
Threshold Hysteresis
-
75
100
125
mV
AuxDrv Peak Voltage
V
OUT
= 0 V; 0 V < V
SOURCE
< 2.0 V (Note 4)
V
OUT
= 0 V; I
AuxDrv
= 100
m
A;
2.0 V < V
IN
< 4.25 V; 2.0 V < V
SB
< 4.25 V
V
OUT
= 3.0 V; I
AuxDrv
= 100
m
A;
0 V < V
IN
< 4.25 V; 0 V < V
SB
< 4.25 V
-
-
-
0.4
0.1
0.1
1.8
0.4
0.4
V
V
V
AuxDrv High Voltage
V
IN
or V
SB
> 4.65 V
3.75
4.0
-
V
AuxDrv Pin Current Limit
V
AuxDrv
= 1.0 V; V
SOURCE
= 4.0 (Note 4)
0.5
6.0
25
mA
V
AuxDrv
Turn-Off Response Time
Step V
SOURCE
from 4.0 V to 5.0 V (Notes 4, 5)
-
20
40
m
s
V
AuxDrv
Turn-On Response Time
Step V
SOURCE
from 5.0 V to 4.0 V (Notes 4, 5)
-
1.0
10
m
s
Pull-Up Resistance
V
IN
= 0 V and V
IN
> 4.7 V (Notes 4, 5)
5.0
10
25
k
W
4. Applies to either V
IN
or V
SB
.
5. Guaranteed by design, not 100% production tested.
CS5233-3
http://onsemi.com
4
PACKAGE PIN DESCRIPTION
Package Lead #
D
2
PAK-5
SOIC-8 Narrow
Lead Symbol
Function
1
1
V
SB
Standby 5.0 V input voltage.
2
2
V
IN
5.0 V Main input voltage.
3, Tab
5, 6, 7, 8
GND
Ground and IC substrate connection.
4
3
V
OUT
Regulated output voltage.
5
4
AuxDrv
Control voltage for the external PFET switched auxiliary supply. This
pin drives low if V
IN
and V
SB
are less than 4.4 V (typical), otherwise
it is pulled up to the greater of V
IN
or V
SB
through an internal diode
and 10 k
W
resistor.
V
IN
UV
Comparator
V
IN
V
SB
AuxDrv
V
SB
UV
Comparator
Internal
BIAS
Bandgap
Reference
Thermal
Shutdown
Error
Amplifier
ENABLE
ENABLE
Current
Limit
V
OUT
GND
-
+
+
-
+
-
Figure 2. Block Diagram
CS5233-3
http://onsemi.com
5
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Output Voltage vs. Junction
Temperature, Output Voltage when Powered
by V
IN
or V
SB
Junction Temperature (
C)
3.310
3.305
3.300
3.295
120
0
3.290
Output V
oltage (V)
100
80
60
40
20
I
OUT
(A)
3.5
0
V
OUT
(V)
0.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Figure 4. Output Voltage vs. Load Current, V
SB
Values Taken with V
IN
= 0 V
Load Current (A)
3.5
0
Ground Current (mA)
0.25
3.0
2.5
2.0
1.5
0.50
0.75
1.00
1.25
1.50
V
SB
= 5.0 V
V
IN
= 5.0 V
Figure 5. Ground Pin Current vs. Output
Current, V
SB
Data with V
IN
= 0 V
V
IN
= 5.0 V
V
SB
= 5.0 V
Junction Temperature (
C)
460
0
Reverse Current (
m
A)
20
440
420
40
60
80
100
120
Figure 6. Reverse Current vs. Junction
Temperature
V
OUT
Output
Current
Figure 7. Transient Load Response, Transient
Response for 1.5 A Step Load, V
IN
= 5.0 V,
C
OUT
= 33
m
F @ 0.4
W
ESR
V
IN
AuxDrv
5.0
4.0
Figure 8. AuxDrv Response Time
CS5233-3
http://onsemi.com
6
Junction Temperature (
C)
4.52
4.50
4.48
4.46
120
0
4.38
V
IN
Threshold V
oltage (V)
100
80
60
40
20
4.44
4.42
4.40
V
IN
Turn-On
Threshold
V
IN
Turn-Off
Threshold
Figure 9. V
IN
Threshold vs. Junction
Temperature, Typical Minimum and Maximum
Threshold Voltages to Switch AuxDrv Control
Junction Temperature (
C)
4.5
120
0
4.3
AuxDrv High V
oltage (V)
100
80
60
40
20
4.4
V
IN
= 4.65 V
Figure 10. AuxDrv High Voltage vs. Junction
Temperature
Input Voltage (V)
4.0
0
0
AuxDrv V
oltage (V)
4.0
2.0
2.0
125
C
4.5
27
C
0
C
Figure 11. AuxDrv Voltage vs. Input Voltage
(V
SB
or V
IN
) at Three Temperatures
CS5233-3
http://onsemi.com
7
APPLICATIONS INFORMATION
INPUT AND OUTPUT VOLTAGE MATRIX
Input
Outputs
V
IN
V
SB
3.3 V
AUX
AuxDrv/5.0 V Detect
V
OUT
, D
2
PAK-5
V
OUT
, SOIC-8
0 V
0 V
0 V
On (low)
0 V
0 V
0 V
0 V
3.3 V
On (low)
3.3 V
AUX
3.3 V
AUX
0 V
5.0 V
0 V
Off (high)
3.3 V
REG
@ 500 mA
3.3 V
REG
@ 500 mA
0 V
5.0 V
3.3 V
Off (high)
3.3 V
REG
@ 500 mA
3.3 V
REG
@ 500 mA
5.0 V
0 V
0 V
Off (high)
3.3 V
REG
@ 1.5 A
3.3 V
REG
@ 500 mA
5.0 V
0 V
3.3 V
Off (high)
3.3 V
REG
@ 1.5 A
3.3 V
REG
@ 500 mA
5.0 V
5.0 V
0 V
Off (high)
3.3 V
REG
@ 1.5 A
3.3 V
REG
@ 500 mA
5.0 V
5.0 V
3.3 V
Off (high)
3.3 V
REG
@ 1.5 A
3.3 V
REG
@ 500 mA
THEORY OF OPERATION
Linear Regulator
The CS5233-3 is a dual input fixed 3.3 V linear regulator
that contains an auxiliary drive control feature. When V
IN
alone is present, or V
IN
and V
SB
are simultaneously present,
the CS5233-3 uses the V
IN
supply to generate the 3.3 V
output at currents of up to 1.5 A. When V
SB
alone is present,
the CS5233-3 uses the V
SB
supply to generate the 3.3 V
output at currents of up to 500 mA. The linear regulator is
composed of a composite PNP-NPN pass transistor to
provide low-voltage dropout capability. An output capacitor
greater than 10
mF with equivalent series resistance (ESR)
less than 1.0
W is required for compensation. More
information is provided in the Stability Considerations
section.
Auxiliary Drive Feature
The CS5233-3 provides an auxiliary drive feature that
allows a load to remain powered even if both supplies to the
IC are absent. An external p-channel FET is the only
additional component required to implement this function
when the auxiliary power supply is available. The PFET gate
is connected to the IC's AuxDrv output, the PFET drain is
connected to the auxiliary power supply, and the PFET
source is connected to the load. The polarity of this
connection is very important, since the PFET body diode
will be connected between the load and the auxiliary supply.
If the PFET is connected with its drain to the load and its
source to the supply, the body diode could be
forward-biased if the auxiliary supply is not present. This
would result in the linear regulator providing current to
everything on the auxiliary supply rail.
The AuxDrv (5.0 V detect) output is pulled up to the input
voltage through an internal resistor when V
IN
or V
SB
are
available. If V
IN
and V
SB
are not available or both drop
below 4.4 V, the AuxDrv output goes low, turning on an
external PFET that connects the 3.3 V auxiliary supply to the
load. The AuxDrv is low only when neither V
IN
nor V
SB
are
available.
There is 100 mV of hysteresis (typical) in the circuitry that
determines if V
IN
or V
SB
are present.
STABILITY CONSIDERATIONS
The output capacitor helps determine three main
characteristics of a linear regulator: loop stability, load
transient response, and start-up delay. The CS5233-3 is
designed to be stable with an output capacitor that has a
minimum value of 10
mF and an equivalent series resistance
less than 1.0
W. To guarantee loop stability, the output
capacitor should be located close to the regulator output and
ground pins. The load transient response, during the time it
takes the regulator to respond, is also determined by the
output capacitor. For large changes in load current, the ESR
of the output capacitor causes an immediate drop in output
voltage given by:
D
V
+ D
I
ESR
There is then an additional drop in output voltage given
by:
D
V
+ D
I
T C
where T is the time for the regulation loop to begin to
respond, (typically 4.0
ms for the CS5233-3). If tight output
regulation is required with fast changing loads, a capacitor
network of tantalum and low ESR ceramic capacitors can be
added as close to the load as possible, with enough
capacitance and a reduced ESR to minimize the voltage
change, as determined by the formulas above.
Input Capacitors and the Vin Thresholds
A capacitor placed on the V
IN
pin will help to improve
transient response. During a load transient, the input
capacitor serves as a charge "reservoir," providing the
needed extra current until the external power supply can
CS5233-3
http://onsemi.com
8
respond. One of the consequences of providing this current
is an instantaneous voltage drop at V
IN
due to capacitor
ESR. The magnitude of the voltage change is again the
product of the current change and the capacitor ESR.
It is very important to consider the maximum current step
that can exist in the system. If the change in current is large
enough, it is possible that the instantaneous voltage drop on
V
IN
will exceed the V
IN
threshold hysteresis, and the IC will
enter a mode of operation resembling an oscillation. As the
part turns on, the output current I
OUT
will increase, reaching
current limit during initial charging. Increasing I
OUT
results
in a drop at V
IN
such that the shutdown threshold is reached.
The part will turn off, and the load current will decrease. As
I
OUT
decreases, V
IN
will rise and the part will turn on,
starting the cycle all over again. This oscillatory operation
is most likely at initial start-up when the output capacitance
is not charged, and in cases where the ramp-up of the V
IN
supply is slow. It may also occur during the power transition
when the linear regulator turns on and the PFET turns off. A
20
ms delay exists between turn-on of the regulator and the
AuxDrv pin pulling the gate of the PFET high. This delay
prevents "chatter" during the power transitions.
If required, using a few capacitors in parallel to increase
the bulk charge storage and reduce the ESR should give
better performance than using a single input capacitor.
Short, straight connections between the power supply and
V
IN
lead along with careful layout of the PC board ground
plane will reduce parasitic inductance effects. Wide V
IN
and
V
OUT
traces will reduce resistive voltage drops.
Choosing the PFET Switch
The choice of the external PFET switch is based on two
main considerations. First, the PFET should have a very low
turn-on threshold. Choosing a switch transistor with
V
GS(ON)
1.0 V will ensure the PFET will be fully enhanced
with only 3.3 V of gate drive voltage. Second, the switch
transistor should be chosen to have a low R
DS(ON)
to
minimize the voltage drop due to current flow in the switch.
The formula for calculating the maximum allowable
on-resistance is
RDS(ON)MAX
+
VAUX(MIN)
*
VOUT(MIN)
1.5
IOUT(MAX)
V
AUX(MIN)
is the minimum value of the auxiliary supply
voltage, V
OUT(MIN)
is the minimum allowable output
voltage, I
OUT(MAX)
is the maximum output current and 1.5
is a "fudge factor" to account for increases in R
DS(ON)
due
to temperature.
Output Voltage Sensing
It is not possible to remotely sense the output voltage of
the C5233-3 since the feedback path to the error amplifier
is not externally available. It is important to minimize
voltage drops due to metal resistance of high current PC
board traces. Such voltage drops can occur in both the
supply traces and the return traces.
The following board layout practices will help to
minimize output voltage errors:
Always place the linear regulator as close to both load
and output capacitors as possible.
Always use the widest possible traces to connect the
linear regulator to the capacitor network and to the
load.
Connect the load to ground through the widest possible
traces.
Connect the IC ground to the load ground trace at the
point where it connects to the load.
Current Limit
The CS5233-3 has internal current limit protection.
Output current is limited to a typical value of 3.0 A for the
D
2
PAK using V
IN
and 800 mA using V
SB
, even under output
short circuit conditions. If the load current drain exceeds the
current limit value, the output voltage will be pulled down
and will result in an out of regulation condition.
Thermal Shutdown
The CS5233-3 has internal temperature monitoring
circuitry. The output is disabled if junction temperature of
the IC reaches 180
C. Thermal hysteresis is typically 25
C
and allows the IC to recover from a thermal fault without the
need for an external reset signal. The monitoring circuitry is
located near the composite PNP-NPN output transistor,
since this transistor is responsible for most of the on-chip
power dissipation. The combination of current limit and
thermal shutdown will protect the IC from nearly any fault
condition.
Reverse Current Protection
During normal system operation, the auxiliary drive
circuitry will maintain voltage on the V
OUT
pin. IC
reliability and system efficiency are improved by limiting
the amount of reverse current that flows from V
OUT
to
ground and from V
OUT
to V
IN
. Current flows from V
OUT
to
ground through the feedback resistor divider that sets up the
output voltage, typically 400
mA. Current flow from V
OUT
to V
IN
will be limited to leakage current after the IC shuts
down. On-chip RC time constants are such that the output
transistor should be turned off well before V
IN
drops below
the V
OUT
voltage.
Calculating Power Dissipation and
Heatsink Requirements
Most linear regulators operate under conditions that result
in high on-chip power dissipation. This results in high
junction temperatures. Since the IC has a thermal shutdown
feature, ensuring the regulator will operate correctly under
normal conditions is an important design consideration.
Some heatsinking will usually be required.
Thermal characteristics of an IC depend on four
parameters: ambient temperature (T
A
in
C), power
dissipation (P
D
in watts), thermal resistance from the die to
CS5233-3
http://onsemi.com
9
the ambient air (
q
JA
in
C per watt) and junction temperature
(T
J
in
C). The maximum junction temperature is calculated
from the formula below:
TJ(MAX)
+
TA(MAX)
) q
JA
PD(MAX)
Maximum ambient temperature and power dissipation are
determined by the design, while
q
JA
is dependent on the
package manufacturer. The maximum junction temperature
for operation of the CS5233-3 within specification is
150
C. The maximum power dissipation of a linear
regulator is given as
PD(MAX)
+
(VIN(MAX)
*
VOUT(MIN))
ILOAD(MAX)
)
VIN(MAX)
IGND(MAX)
where I
GND(MAX)
is the IC bias current.
It is possible to change the effective value of
q
JA
by adding
a heatsink to the design. A heatsink serves in some manner
to raise the effective area of the package, thus improving the
flow of heat from the package into the surrounding air. Each
material in the path of heat flow has its own characteristic
thermal resistance, all measured in
C per watt. The thermal
resistances are summed to determine the total thermal
resistance between the die junction and air. There are three
components of interest: junction-to-case thermal resistance
(
q
JC
), case-to-heatsink thermal resistance (
q
CS
) and
heatsink-to-air thermal resistance (
q
SA
). The resulting
equation for junction-to-air thermal resistance is
q
JA
+ q
JC
) q
CS
) q
SA, or
q
JA
+ q
JC
) q
SA for
q
CS
+
0
The value of
q
JC
for the CS5233-3 is provided in the
Packaging Information section of this data sheet.
q
CS
can be
considered zero, since heat is conducted out of the package
by the IC leads and the tab of the D
2
PAK package, and since
the IC leads and tab are soldered directly to the PC board.
Modification of
q
SA
is the primary means of thermal
management. For surface mount components, this means
modifying the amount of trace metal that connects to the IC.
The thermal capacity of PC board traces is dependent on
how much copper area is used, if the IC is in direct contact
with the metal, whether the metal surface is coated with
some type of sealant, and whether there is airflow across the
PC board. The chart provided below shows heatsinking
capability of a square, single sided copper PC board trace.
The area is given in square millimeters, and it is assumed
there is no airflow across the PC board.
Figure 12. Thermal Resistance Capability of
Copper PC Board Metal Traces
PC Board Trace Area (mm
2
)
70
0
Thermal Resistance,
CW
2000
50
60
40
30
20
10
0
4000
6000
CS5233-3
http://onsemi.com
10
PACKAGE DIMENSIONS
D
2
PAK-5
DP SUFFIX
CASE 936AC-01
ISSUE O
For D
2
PAK Outline and
Dimensions - Contact Factory
CS5233-3
http://onsemi.com
11
PACKAGE DIMENSIONS
SOIC-8
DF SUFFIX
CASE 751-07
ISSUE AA
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
Figure 13. SOIC-8
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
SOLDERING FOOTPRINT
PACKAGE THERMAL DATA
Parameter
D
2
PAK-5
SOIC-8
Unit
R
q
JC
Typical
1.0-4.0
25
C/W
R
q
JA
Typical
10-50*
110
C/W
*Depending on thermal properties of substrate. R
q
JA
= R
q
JC
+ R
q
CA
.
CS5233-3
http://onsemi.com
12
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
CIS5233-3/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
PDF 
ZIP