Semiconductor Components Industries, LLC, 2001
October, 2001 Rev. 13
1
Publication Order Number:
CS8126/D
CS8126
5.0 V, 750 mA Low
Dropout Linear Regulator
with Delayed RESET
The CS8126 is a low dropout, high current 5.0 V linear regulator. It
is an improved replacement for the CS8156. Improvements include
higher accuracy, tighter saturation control, better supply rejection, and
enhanced RESET circuitry. Familiar PNP regulator features such as
reverse battery protection, overvoltage shutdown, thermal shutdown,
and current limit make the CS8126 suitable for use in automotive and
battery operated equipment. Additional onchip filtering has been
included to enhance rejection of high frequency transients on all
external leads.
An active microprocessor RESET function is included onchip with
externally programmable delay time. During powerup, or after
detection of any error in the regulated output, the RESET lead will
remain in the low state for the duration of the delay. Types of errors
include short circuit, low input voltage, overvoltage shutdown,
thermal shutdown, or others that cause the output to become
unregulated. This function is independent of the input voltage and will
function correctly with an output voltage as low as 1.0 V. Hysteresis is
included in both the reset and Delay comparators for enhanced noise
immunity. A latching discharge circuit is used to discharge the Delay
capacitor, even when triggered by a relatively short fault condition.
This circuit improves upon the commonly used SCR structure by
providing full capacitor discharge (0.2 V type).
Note: The CS8126 is lead compatible with the LM2927 and
LM2926.
Features
Low Dropout Voltage (0.6 V at 0.5 A)
3.0% Output Accuracy
Active RESET
External RESET Delay for Reset
Protection Circuitry
Reverse Battery Protection
+60 V, 50 V Peak Transient Voltage
Short Circuit Protection
Internal Thermal Overload Protection
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TO220
FIVE LEAD
T SUFFIX
CASE 314D
1
5
TO220
FIVE LEAD
TVA SUFFIX
CASE 314K
TO220
FIVE LEAD
THA SUFFIX
CASE 314A
1
5
1
Pin 1. V
IN
2. V
OUT
3. GND
4. Delay
5. RESET
TO220
FIVE LEAD
THE SUFFIX
CASE 314J
1
7
D
2
PAK
7PIN
DPS SUFFIX
CASE 936H
Pin 1. V
IN
2. V
OUT
3. V
OUT(SENSE)
4. GND
5. Delay
6. RESET
7. NC
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 9 of this data sheet.
DEVICE MARKING INFORMATION
1
5
CS8126
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2
Delay
Q
S
R
Latching
Discharge
+
V
Discharge
Charge
Current
Generator
+
Thermal
Shutdown
Bandgap
Reference
+
AntiSaturation
and
Current Limit
+
GND
RESET
PreRegulator
Regulated Supply
for Circuit Bias
V
OUT
Over Voltage
Shutdown
V
IN
Error
Amp
Delay
Comparator
Reset
Comparator
Figure 1. Block Diagram
V
OUT(SENSE)
Internally
connected
on 5 Lead
TO220
CS8126
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3
MAXIMUM RATINGS*
Rating
Value
Unit
Power Dissipation
Internally Limited
Peak Transient Voltage (46 V Load Dump)
50, 60
V
Output Current
Internally Limited
ESD Susceptibility (Human Body Model)
4.0
kV
Package Thermal Resistance, TO220 5Lead:
JunctiontoCase, R
JC
JunctiontoAmbient, R
JA
2.1
50
C/W
C/W
Package Thermal Resistance, D
2
PAK, 7Pin:
JunctiontoCase, R
JC
JunctiontoAmbient, R
JA
2.1
1050**
C/W
C/W
Junction Temperature Range
40 to +150
C
Storage Temperature Range
55 to +150
C
Lead Temperature Soldering:
Wave Solder (through hole styles only) (Note 1)
Reflow (SMD styles only) (Note 2)
260 peak
230 peak
C
C
1. 10 second maximum.
2. 60 second maximum above 183
C.
*The maximum package power dissipation must be observed.
**Depending on thermal properties of substrate. R
JA
= R
JC
+ R
CA
.
ELECTRICAL CHARACTERISTICS
(T
A
= 40
C to +125
C, T
J
= 40
C to +150
C, V
IN
= 6.0 to 26 V,
I
O
= 5.0 to 500 mA, R
RESET
= 4.7 k
to V
CC
, unless otherwise noted.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage (V
OUT
)
Output Voltage
4.85
5.00
5.15
V
Dropout Voltage
I
OUT1
= 500 mA
0.35
0.60
V
Supply Current
I
OUT
10 mA
I
OUT
100 mA
I
OUT
500 mA
2.0
6.0
55
7.0
12
100
mA
mA
mA
Line Regulation
V
IN
= 6.0 to 26 V, I
OUT
= 50 mA
5.0
50
mV
Load Regulation
I
OUT
= 50 to 500 mA, V
IN
= 14 V
10
50
mV
Ripple Rejection
f = 120 Hz, V
IN
= 7.0 to 17 V, I
OUT
= 250 mA
54
75
dB
Current Limit
0.75
1.20
A
Overvoltage Shutdown
32
40
V
Maximum Line Transient
V
OUT
5.5 V
95
V
Reverse Polarity Input Voltage DC
V
OUT
0.6 V, 10
Load
15
30
V
Reverse Polarity Input Voltage Transient
1.0% Duty Cycle, T < 100 ms, 10
Load
80
V
Thermal Shutdown
Note 3
150
180
210
C
3. Guaranteed By Design
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4
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= 40
C to +125
C, T
J
= 40
C to +150
C, V
IN
= 6.0 to 26 V,
I
O
= 5.0 to 500 mA, R
RESET
= 4.7 k
to V
CC
, unless otherwise noted.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
RESET and Delay Functions
Delay Charge Current
V
Delay
= 2.0 V
5.0
10
15
A
RESET Threshold
V
OUT
Increasing, V
RT(ON)
V
OUT
Decreasing, V
RT(OFF)
4.65
4.50
4.90
4.70
V
OUT
0.01
V
OUT
0.15
V
V
RESET Hysteresis
V
RH
= V
RT(ON)
V
RT(OFF)
150
200
250
mV
Delay Threshold
Charge, V
DC(HI)
Discharge, V
DC(LO)
3.25
2.85
3.50
3.10
3.75
3.35
V
V
Delay Hysteresis
200
400
800
mV
RESET Output Voltage Low
1.0 V < V
OUT
< V
RTL
, 3.0 k
to V
OUT
0.1
0.4
V
RESET Output Leakage Current
V
OUT
> V
RT(ON)
0
10
A
Delay Capacitor Discharge Voltage
Discharge Latched "ON", V
OUT
> V
RT
0.2
0.5
V
Delay Time
C
Delay
= 0.1
F*. Note 4
16
32
48
ms
* Delay Time
+
CDelay
VDelayThreshold Charge
ICharge
+
CDelay
3.2
4. Assumes Ideal Capacitor
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD #
TO220
5 LEAD
D
2
PAK
7PIN
LEAD SYMBOL
FUNCTION
1
1
V
IN
Unregulated supply voltage to IC.
2
2
V
OUT
Regulated 5.0 V output.
3
4
GND
Ground connection.
4
5
Delay
Timing capacitor for RESET function.
5
6
RESET
CMOS/TTL compatible output lead. RESET goes low after detection of any error in
the regulated output or during power up.
3
V
OUT(SENSE)
Remote sensing of output voltage.
7
NC
No Connection.
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5
TYPICAL PERFORMANCE CHARACTERISTICS
0
V
IN
(V)
V
IN
(V)
I
CQ
(
m
A)
Figure 2. I
CQ
vs. V
IN
Over Temperature
Figure 3. I
CQ
vs. V
IN
Over R
LOAD
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
0
55
50
45
40
35
30
25
20
15
10
5.0
120
110
100
90
80
70
60
50
40
30
20
10
V
IN
(V)
V
OUT
(V)
Figure 4. V
OUT
vs. V
IN
Over Temperature
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
IN
(V)
V
OUT
(V)
Figure 5. V
OUT
vs. V
IN
Over R
LOAD
I
CQ
(mA)
Room Temp.
R
LOAD
= 25
R
LOAD
= 25
Room Temp.
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
25
C
125
C
40
C
R
LOAD
= 6.67
R
LOAD
= 10
R
LOAD
= 25
R
LOAD
= NO LOAD
25
C
125
C
40
C
R
LOAD
= 10
R
LOAD
= 6.67
R
LOAD
= NO LOAD
Output Current (mA)
0
100
200
300
400
500
600
700
800
100
80
60
40
20
0
20
40
60
80
100
Output Current (mA)
0
100
200
300
400
500
600
700
800
6.0
4.0
2.0
0
2.0
4.0
6.0
8.0
10
12
14
Figure 6. Line Regulation vs. Output
Current Over Temperature
Figure 7. Load Regulation vs. Output
Current Over Temperature
Li
ne
R
egu
l
at
i
on
(
m
V)
Load Regulation (mV)
TEMP = 25
C
TEMP = 40
C
TEMP = 125
C
V
IN
6.026 V
TEMP = 40
C
TEMP = 25
C
TEMP = 125
C
V
IN
= 14 V
CS8126
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6
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Current (mA)
0
100
200
300
400
500
600
700
800
Figure 8. Dropout Voltage vs. Output
Current Over Temperature
Output Current (mA)
0
100
200
300
400
500
600
700
800
100
90
80
70
60
50
40
30
20
10
0
Figure 9. Quiescent Current vs. Output
Current Over Temperature
Quiescent
Current (mA)
900
800
700
600
500
400
300
200
100
0
Dropout V
oltage (mV)
90
80
70
60
50
40
30
20
10
0
Rejection (dB)
Freq. (Hz)
10
0
Figure 10. Ripple Rejection
10
1
10
2
10
3
10
4
10
5
10
6
10
7
10
8
Output Current (mA)
Figure 11. Output Capacitor ESR
10
3
10
2
10
1
10
0
10
4
ESR (
)
10
3
10
2
10
1
10
0
10
1
10
2
10
3
125
C
40
C
25
C
25
C
125
C
40
C
COUT = 10 mF,
ESR = 1 & 0.1 mF, ESR = 0
C
OUT
= 10
F, ESR = 1
& 0.1
F, ESR = 0
C
OUT
= 10
F, ESR = 1.0
C
OUT
= 10
F, ESR = 10
C
OUT
= 47/68
F
C
OUT
= 47
F
C
OUT
= 68
F
Stable Region
VIN = 14 V
V
DC(LO)
V
DC(HI)
V
DH
V
RL
Delay
(3)
RESET
V
RT(OFF)
V
RT(ON)
V
RH
(1)
(2)
(2)
t
Delay
V
DIS
V
OUT
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max:RESET Voltage (1.0 V)
Figure 12. RESET Circuit Waveform
RESET CIRCUIT WAVEFORM
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7
CIRCUIT DESCRIPTION
The CS8126 RESET function, has hysteresis on both the
Reset and Delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1.0 V.
The RESET circuit output is an open collector type with
ON and OFF parameters as specified. The RESET output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
Low Voltage Inhibit Circuit
This circuit monitors output voltage, and when the output
voltage falls below V
RT(OFF)
, causes the RESET output
transistor to be in the ON (saturation) state. When the output
voltage rises above V
RT(ON)
, this circuit permits the RESET
output transistor to go into the OFF state if allowed by the
RESET Delay circuit.
RESET Delay Circuit
This circuit provides a programmable (by external
capacitor) delay on the RESET output lead. The Delay lead
provides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that output
voltage is above V
RT(ON)
. Otherwise, the Delay lead sinks
current to ground (used to discharge the delay capacitor).
The discharge current is latched ON when the output voltage
falls below V
RT(OFF)
. The Delay capacitor is fully
discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled RESET pulse is generated following
detection of an error condition. The circuit allows the
RESET output transistor to go to the OFF (open) state only
when the voltage on the Delay lead is higher than V
DC(H1)
.
The Delay time for the RESET function is calculated from
the formula:
Delay time
+
CDelay
VDelayThreshold
ICharge
Delay time
+
CDelay
3.2
105
If C
Delay
= 0.1
F, Delay time (ms) = 32 ms
50%: i.e.
16 ms to 48 ms. The tolerance of the capacitor must be taken
into account to calculate the total variation in the delay time.
Figure 13. Application Diagram
GND
V
IN
V
OUT
CS8126
C
1
*
100 nF
C
2
**
10
F to 100
F
* C
1
is required if the regulator is far from the power source filter.
** C
2
is required for stability.
RESET
Delay
R
RST
4.7 k
Delay
0.1
F
APPLICATION NOTES
Stability Considerations
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: startup
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR, can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (25
C to 40
C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor C
2
shown in the test and
applications circuit should work for most applications,
however it is not necessarily the optimized solution.
To determine an acceptable value for C
2
for a particular
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
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8
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using the
decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in step
3 and vary the input voltage until the oscillations increase.
This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4 with
the next smaller valued capacitor. A smaller capacitor will
usually cost less and occupy less board space. If the output
oscillates within the range of expected operating conditions,
repeat steps 3 and 4 with the next larger standard capacitor
value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of
20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
Calculating Power Dissipation in a Single Output
Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 14) is:
PD(max)
+
VIN(max)
*
VOUT(min) IOUT(max)
)
VIN(max)IQ
(1)
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current, for the
application, and
I
Q
is the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
JA
can be calculated:
R
Q
JA
+
150
C
*
TA
PD
(2)
The value of R
JA
can then be compared with those in the
package section of the data sheet. Those packages with
R
JA
's less than the calculated value in equation 2 will keep
the die temperature below 150
C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Figure 14. Single Output Regulator With Key
Performance Parameters Labeled
SMART
REGULATOR
Control
Features
I
OUT
I
IN
I
Q
V
IN
V
OUT
Heat Sinks
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
JA
.
R
Q
JA
+
R
Q
JC
)
R
Q
CS
)
R
Q
SA
(3)
where:
R
JC
= the junctiontocase thermal resistance,
R
CS
= the casetoheatsink thermal resistance, and
R
SA
= the heatsinktoambient thermal resistance.
R
JC
appears in the package section of the data sheet. Like
R
JA
, it is a function of package type. R
CS
and R
SA
are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
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9
ORDERING INFORMATION
Device
Description
Shipping
CS81261YT5
TO220 FIVE LEAD STRAIGHT
50 Units/Rail
CS81261YTVA5
TO220 FIVE LEAD VERTICAL
50 Units/Rail
CS81261YTHA5
TO220 FIVE LEAD HORIZONTAL
50 Units/Rail
CS81261YTHE5
TO220 FIVE LEAD SURFACE MOUNT
50 Units/Rail
CS81261YTHER5
TO220 FIVE LEAD SURFACE MOUNT
750 Tape & Reel
CS81261YDPS7
D
2
PAK, 7PIN
50 Units/Rail
CS81261YDPSR7
D
2
PAK, 7PIN
750 Tape & Reel
MARKING DIAGRAMS
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
TO220
FIVE LEAD
T SUFFIX
CASE 314D
CS8126
AWLYWW
1
TO220
FIVE LEAD
TVA SUFFIX
CASE 314K
CS8126
AWLYWW
1
TO220
FIVE LEAD
THA SUFFIX
CASE 314A
CS8126
AWLYWW
1
TO220
FIVE LEAD
THE SUFFIX
CASE 314J
CS8126
AWLYWW
1
D
2
PAK
7PIN
DPS SUFFIX
CASE 936H
CS8126
AWLYWW
1
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10
PACKAGE DIMENSIONS
TO220
FIVE LEAD
T SUFFIX
CASE 314D04
ISSUE E
Q
1 2 3 4 5
U
K
D
G
A
B
5 PL
J
H
L
E
C
M
Q
M
0.356 (0.014)
T
SEATING
PLANE
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.572
0.613 14.529 15.570
B
0.390
0.415
9.906 10.541
C
0.170
0.180
4.318
4.572
D
0.025
0.038
0.635
0.965
E
0.048
0.055
1.219
1.397
G
0.067 BSC
1.702 BSC
H
0.087
0.112
2.210
2.845
J
0.015
0.025
0.381
0.635
K
0.990
1.045 25.146 26.543
L
0.320
0.365
8.128
9.271
Q
0.140
0.153
3.556
3.886
U
0.105
0.117
2.667
2.972
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
TO220
FIVE LEAD
TVA SUFFIX
CASE 314K01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.560
0.590
14.22
14.99
B
0.385
0.415
9.78
10.54
C
0.160
0.190
4.06
4.83
D
0.027
0.037
0.69
0.94
E
0.045
0.055
1.14
1.40
F
0.530
0.545
13.46
13.84
G
0.067 BSC
1.70 BSC
J
0.014
0.022
0.36
0.56
K
0.785
0.800
19.94
20.32
L
0.321
0.337
8.15
8.56
M
0.063
0.078
1.60
1.98
Q
0.146
0.156
3.71
3.96
S
0.146
0.196
3.71
4.98
U
0.460
0.475
11.68
12.07
W
5
5
R
0.271
0.321
6.88
8.15
A
U
D
G
B
T
M
0.356 (0.014)
M
Q
5 PL
Q
K
F
J
C
E
T
S
L
1
2
3
4
5
SEATING
PLANE
R
M
W
CS8126
http://onsemi.com
11
TO220
FIVE LEAD
THA SUFFIX
CASE 314A03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
DIM
A
MIN
MAX
MIN
MAX
MILLIMETERS
0.572
0.613 14.529 15.570
INCHES
B
0.390
0.415
9.906 10.541
C
0.170
0.180
4.318
4.572
D
0.025
0.038
0.635
0.965
E
0.048
0.055
1.219
1.397
F
0.570
0.585 14.478 14.859
G
0.067 BSC
1.702 BSC
J
0.015
0.025
0.381
0.635
K
0.730
0.745 18.542 18.923
L
0.320
0.365
8.128
9.271
Q
0.140
0.153
3.556
3.886
S
0.210
0.260
5.334
6.604
U
0.468
0.505 11.888 12.827
T
SEATING
PLANE
L
S
E
C
F
K
J
OPTIONAL
CHAMFER
5X
D
5X
M
P
M
0.014 (0.356)
T
G
A
U
B
Q
P
TO220
FIVE LEAD
THE SUFFIX
CASE 314J01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
4. DIMENSIONS EXCLUSIVE OF MOLD FLASH
AND METAL BURRS.
5. FOOTPAD LENGTH MEASURED FROM LEAD
TIP WITH REFERENCE TO DATUM -M-.
6. COPLANARITY 0.004" MAX. REFERENCE TO
DATUM -N- STANDOFF HEIGHT 0.00 - 0.010".
A
U
D
G
B
T
M
0.356 (0.014)
M
Q
5 PL
Q
K
F
J
C
E
T
L
1
2
3
4
5
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.568
0.583
14.43
14.81
B
0.395
0.405
10.03
10.29
C
0.170
0.180
4.32
4.57
D
0.028
0.036
0.71
0.91
E
0.045
0.055
1.14
1.40
F
0.543
0.558
13.79
14.17
G
0.067 BSC
1.70 BSC
J
0.014
0.022
0.36
0.56
K
0.073
0.088
1.85
2.24
L
0.324
0.339
8.23
8.61
Q
0.146
0.156
3.71
3.96
S
0.000
0.010
0.00
0.25
U
0.460
0.475
11.68
12.07
SEATING
PLANE
W
M
0.102 (0.004)
N
S
W
5
5
CS8126
http://onsemi.com
12
D
2
PAK
7PIN
DPS SUFFIX
CASE 936H01
ISSUE O
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.326
0.336
8.28
8.53
B
0.396
0.406
10.05
10.31
C
0.170
0.180
4.31
4.57
D
0.026
0.036
0.66
0.91
E
0.045
0.055
1.14
1.40
F
0.058
0.078
1.41
1.98
G
0.050 BSC
1.27 BSC
H
0.100
0.110
2.54
2.79
J
0.018
0.025
0.46
0.64
K
0.204
0.214
5.18
5.44
M
0.055
0.066
1.40
1.68
N
0.000
0.004
0.00
0.10
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
B AND M.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAX.
B
N
A
K
M
E
C
SEATING
PLANE
F
H
J
D
7 PL
G
T
M
0.13 (0.005)
M
B
1 2 3 4 5
U
0.256 REF
6.50 REF
V
0.305 REF
7.75 REF
6 7
8
U
V
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