MC100E241
Semiconductor Components Industries, LLC, 2002
January, 2002 Rev. 0
1
Publication Order Number:
MC100E241/D
MC100E241
5V ECL 8 Bit Scannable
Register
The MC100E241 is an 8-bit shiftable register. Unlike a standard
universal shift register such as the E141, the E241 features internal
data feedback organized so that the SHIFT control overrides the
HOLD/LOAD control. This enables the normal operations of HOLD
and LOAD to be toggled with a single control line without the need for
external gating. It also enables switching to scan mode with the single
SHIFT control line.
The eight inputs D0 D7 accept parallel input data, while S-IN
accepts serial input data when in shift mode. Data is accepted a set-up
time before the positive-going edge of CLK; shifting is also
accomplished on the positive clock edge. A HIGH on the Master Reset
pin (MR) asynchronously resets all the registers to zero.
The 100 Series contains temperature compensation.
SHIFT overrides HOLD/LOAD Control
1000 ps Max. CLK to Q
Asynchronous Master Reset
Pin-Compatible with E141
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
ESD Protection: > 1 KV HBM, > 75 V MM
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 code V0 @ 1/8
,
Oxygen Index 28 to 34
Transistor Count = 529 devices
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC100E241FN
PLCC28
37 Units/Rail
MC100E241FNR2
PLCC28
500 Units/Reel
MARKING
DIAGRAM
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PLCC28
FN SUFFIX
CASE 776
MC100E241FN
AWLYYWW
1
28
Figure 2. Logic Diagram
Q0
Q1 Q6
Q7
S-IN
D0
D1 D6
D7
HOLD/LOAD
SHIFT
CLK
MR
BITS 1-6
D
D
D
Q
Q
Q
R
R
R
1
0
1
0
1
0
1
0
1
0
1
0
MC100E241
http://onsemi.com
2
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
SEL1
CLK
MR
VEE
S-IN
D0
D1
26
27
28
2
3
4
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
5
6
7
8
9
10
SEL0 NC
D7
D6
D5 VCCO Q7
Q6
Q5
VCC
NC
VCCO
Q4
Q3
D2
D3
D4 VCCO Q0
Q1
Q2
1
Pinout: 28-Lead PLCC
(Top View)
* All VCC and VCCO pins are tied together on the die.
Figure 1. Pinout Assignment
PIN DESCRIPTION
PIN
FUNCTION
D0 D7
ECL Parallel Date Inputs
S-IN
ECL Serial Data Inputs
SEL0
ECL SHIFT Control
SEL1
ECL HOLD/LOAD Control
CLK
ECL Clock
MR
ECL Master Reset
Q0 Q7
ECL Data Outputs
VCC, VCCO
Positive Supply
VEE
Negative Supply
NC
No Connect
FUNCTION TABLE
MR
SEL0
SEL1
Function
1
X
X
Outputs LOW
0
1
X
Shift Data
0
0
1
Hold Data
0
0
0
Load Data
X = Don't Care
MC100E241
http://onsemi.com
3
MAXIMUM RATINGS
(Note 1)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
8
V
VI
PECL Mode Input Voltage
VEE = 0 V
VI
VCC
6
V
I
C
ode
u
o age
NECL Mode Input Voltage
EE
0
VCC = 0 V
I
CC
VI
VEE
6
6
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
C
Tstg
Storage Temperature Range
65 to +150
C
JA
Thermal Resistance (JunctiontoAmbient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
C/W
C/W
JC
Thermal Resistance (JunctiontoCase)
std bd
28 PLCC
22 to 26
C/W
VEE
PECL Operating Range
NECL Operating Range
4.2 to 5.7
5.7 to 4.2
V
V
Tsol
Wave Solder
< 2 to 3 sec @ 248
C
265
C
1. Maximum Ratings are those values beyond which device damage may occur.
100E SERIES PECL DC CHARACTERISTICS
VCCx = 5.0 V; VEE = 0.0 V (Note 2)
0
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
125
150
125
150
144
173
mA
VOH
Output HIGH Voltage (Note 3)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 3)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
4050
4120
3835
4120
4120
3835
4120
4120
mV
VIL
Input LOW Voltage
3190
3300
3525
3190
3525
3525
3190
3525
3525
mV
IIH
Input HIGH Current
150
150
150
A
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.8 V.
3. Outputs are terminated through a 50
resistor to VCC 2.0 V.
100E SERIES NECL DC CHARACTERISTICS
VCCx = 0.0 V; VEE = 5.0 V (Note 4)
0
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
125
150
125
150
144
173
mA
VOH
Output HIGH Voltage
1025
950
880
1025
950
880
1025
950
880
mV
VOL
Output LOW Voltage
1810
1705
1620
1810
1745
1620
1810
1740
1620
mV
VIH
Input HIGH Voltage (SingleEnded)
1165
950
880
1165
880
880
1165
880
880
mV
VIL
Input LOW Voltage (SingleEnded)
1810
1700
1475
1810
1475
1475
1810
1475
1475
mV
IIH
Input HIGH Current
150
150
150
A
IIL
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / 0.8 V.
5. Outputs are terminated through a 50
resistor to VCC 2.0 V.
MC100E241
http://onsemi.com
4
AC CHARACTERISTICS
VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = 5.0 V (Note 6)
0
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fMAX
Maximum Toggle Frequency
TBD
TBD
TBD
GHz
fSHIFT
Max. Shift Frequency
700
900
700
900
700
900
MHz
tPLH
Propagation Delay to Output
ps
tPHL
Clk
625
750
975
625
750
975
625
750
975
MR
600
725
975
600
725
975
600
725
975
ts
Setup Time
ps
D
175
25
175
25
175
25
SEL0 (SHIFT)
350
200
350
200
350
200
SEL1 (HOLD/LOAD)
400
250
400
250
400
250
S-IN
125
100
125
100
125
100
th
Hold Time
ps
D
200
25
200
25
200
25
SEL0 (SHIFT)
100
200
100
200
100
200
SEL1 (HOLD/LOAD)
50
250
50
250
50
250
S-IN
300
100
300
100
300
100
tRR
Reset Recovery Time
900
600
900
600
900
600
ps
tPW
Minimum Pulse Width
ps
Clk, MR
400
400
400
tSKEW
Within-Device Skew (Note 7)
60
60
60
ps
tJITTER
CycletoCycle Jitter
TBD
TBD
TBD
ps
tr
Rise/Fall Times
ps
tf
(20 - 80%)
300
525
800
300
525
800
300
525
800
6. 100 Series: VEE can vary +0.46 V / 0.8 V.
7. Within-device skew is defined as identical transitions on similar paths through a device.
Q
D
D
Q
Driver
Device
Receiver
Device
50
50
VTT
Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 Termination of ECL Logic Devices.)
VTT = VCC 2.0 V
MC100E241
http://onsemi.com
5
Resource Reference of Application Notes
AN1404
ECLinPS Circuit Performance at NonStandard VIH Levels
AN1405
ECL Clock Distribution Techniques
AN1406
Designing with PECL (ECL at +5.0 V)
AN1503
ECLinPS I/O SPICE Modeling Kit
AN1504
Metastability and the ECLinPS Family
AN1568
Interfacing Between LVDS and ECL
AN1596
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
Using WireOR Ties in ECLinPS Designs
AN1672
The ECL Translator Guide
AND8001
Odd Number Counters Design
AND8002
Marking and Date Codes
AND8020
Termination of ECL Logic Devices
PDF 
ZIP