Semiconductor Components Industries, LLC, 2001
February, 2001 Rev. 2
1
Publication Order Number:
MC100EL30/D
MC100EL30
5V ECL Triple D Flip-Flop
with Set and Reset
The MC100EL30 is a triple masterslave D flip flop with differential
outputs. Data enters the master latch when the clock input is LOW and
transfers to the slave upon a positive transition on the clock input.
In addition to a common Set input individual Reset inputs are provided
for each flip flop. Both the Set and Reset inputs function asynchronous and
overriding with respect to the clock inputs.
1200 MHz Minimum Toggle Frequency
450 ps Typical Propagation Delays
ESD Protection: >2 KV HBM
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range: V
CC
= 4.2 V to 5.7 V with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V with V
EE
= 4.2 V to 5.7 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL94 code V0 @ 1/8",
Oxygen Index 28 to 34
Transistor Count = 347 devices
D1
Logic Diagram and Pinout: 20-Lead SOIC (Top View)
R0
R1
D2
17
18
16
15
14
13
12
4
3
5
6
7
8
9
Q0
11
10
V
CC
Q1
Q1
V
CC
Q2
Q2
V
EE
D0
19
20
2
1
V
CC
Q0
CLK0
CLK1
S012
CLK2 R2
D
R
S
Q
Q
D
R
S
Q
Q
D
R
S
Q
Q
Warning: All V
CC
and V
EE
pins must be externally connected to
Power Supply to guarantee proper operation.
PIN DESCRIPTION
FUNCTION
ECL Data Inputs
ECL Reset Inputs
ECL Clock Inputs
ECL Common Set Input
ECL Differential Data Outputs
Positive Supply
Negative Supply
PIN
D0D2
R0R2
CLK0CLK2
S012
Q0Q2; Q0Q2
V
CC
V
EE
R*
TRUTH TABLE
S*
D*
CLK*
Q
Z = LOW to HIGH Transition
X = Don't Care
Q
L
L
H
L
H
L
L
L
H
H
L
H
X
X
X
Z
Z
X
X
X
L
H
L
H
Undef
H
L
H
L
Undef
* Pins will default low when
left open.
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MARKING
DIAGRAM*
1
20
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
SO20
DW SUFFIX
CASE 751D
100EL30
AWLYYWW
1
20
Device
Package
Shipping
ORDERING INFORMATION
MC100EL30DW
SO20
38 Units/Rail
MC100EL30DWR2
SO20
1000 Units/Reel
*For additional information, see Application Note
AND8002/D
MC100EL30
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2
MAXIMUM RATINGS
(Note 1.)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
CC
PECL Mode Power Supply
V
EE
= 0 V
8 to 0
V
V
EE
NECL Mode Power Supply
V
CC
= 0 V
8 to 0
V
V
I
PECL Mode Input Voltage
V
EE
= 0 V
V
I
V
CC
6 to 0
V
I
C
ode
u
o age
NECL Mode Input Voltage
EE
0
V
CC
= 0 V
I
CC
V
I
V
EE
6 o 0
6 to 0
V
I
out
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
40 to +85
C
T
stg
Storage Temperature Range
65 to +150
C
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
20 SOIC
20 SOIC
90
60
C/W
C/W
JC
Thermal Resistance (Junction to Case)
std bd
20 SOIC
30 to 35
C/W
T
sol
Wave Solder
<2 to 3 sec @ 248
C
265
C
1. Maximum Ratings are those values beyond which device damage may occur.
PECL DC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= 0.0 V (Note 1.)
40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Power Supply Current
55
62
55
62
55
64
mA
V
OH
Output HIGH Voltage (Note 2.)
3915
3995
4120
3975
4045
4120
3975
4050
4120
mV
V
OL
Output LOW Voltage (Note 2.)
3170
3305
3445
3190
3295
3380
3190
3295
3380
mV
V
IH
Input HIGH Voltage
3835
4120
3835
4120
3835
4120
mV
V
IL
Input LOW Voltage
3190
3525
3190
3525
3190
3525
mV
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.5
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.8 V / 0.5 V.
2. Outputs are terminated through a 50 ohm resistor to V
CC
2 volts.
NECL DC CHARACTERISTICS
V
CC
= 0.0 V; V
EE
= 5.0 V (Note 1.)
40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Power Supply Current
55
62
55
62
55
64
mA
V
OH
Output HIGH Voltage (Note 2.)
1085
1005
880
1025
955
880
1025
955
880
mV
V
OL
Output LOW Voltage (Note 2.)
1830
1695
1555
1810
1705
1620
1810
1705
1620
mV
V
IH
Input HIGH Voltage
1165
880
1165
880
1165
880
mV
V
IL
Input LOW Voltage
1810
1475
1810
1475
1810
1475
mV
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.5
A
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.8 V / 0.5 V.
2. Outputs are terminated through a 50 ohm resistor to V
CC
2 volts.
MC100EL30
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3
AC CHARACTERISTICS
V
CC
= 5.0 V; V
EE
= 0.0 V or V
CC
= 0.0 V; V
EE
= 5.0 V (Note 1.)
40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Toggle Frequency
1.0
1.2
1.2
GHz
t
PLH
t
PHL
Propagation Delay
CLK
to Output
S, R
460
470
690
710
480
490
710
730
500
515
730
755
ps
t
S
t
H
Setup Time
Hold Time
150
200
0
100
150
200
0
100
150
200
0
100
ps
t
RR
Set/Reset Recovery
400
200
400
200
400
200
ps
t
PW
Minimum Pulse Width
CLK
Set, Reset
400
650
400
650
400
650
ps
t
JITTER
CycletoCycle Jitter
TBD
TBD
TBD
ps
t
r
t
f
Output Rise/Fall Times Q
(20% 80%)
280
550
280
450
550
280
550
ps
1. V
EE
can vary +0.8 V / 0.5 V.
V TT = V CC 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 Termination of ECL Logic Devices.)
W
Driver
Device
Receiver
Device
Q
Qb
D
Db
50
W
50
V TT
Resource Reference of Application Notes
AN1404
ECLinPS Circuit Performance at NonStandard V
IH
Levels
AN1405
ECL Clock Distribution Techniques
AN1406
Designing with PECL (ECL at +5.0 V)
AN1503
ECLinPS I/O SPICE Modeling Kit
AN1504
Metastability and the ECLinPS Family
AN1560
Low Voltage ECLinPS SPICE Modeling Kit
AN1568
Interfacing Between LVDS and ECL
AN1596
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
Using WireOR Ties in ECLinPS Designs
AN1672
The ECL Translator Guide
AND8001
Odd Number Counters Design
AND8002
Marking and Date Codes
AND8020
Termination of ECL Logic Devices
MC100EL30
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4
PACKAGE DIMENSIONS
SO20
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D05
ISSUE F
20
1
11
10
B
20X
H
10X
C
L
18X
A1
A
SEATING
PLANE
q
h
X 45
_
E
D
M
0.25
M
B
M
0.25
S
A
S
B
T
e
T
B
A
DIM
MIN
MAX
MILLIMETERS
A
2.35
2.65
A1
0.10
0.25
B
0.35
0.49
C
0.23
0.32
D
12.65
12.95
E
7.40
7.60
e
1.27 BSC
H
10.05
10.55
h
0.25
0.75
L
0.50
0.90
q
0
7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
_
_
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