Semiconductor Components Industries, LLC, 2000
March, 2000 Rev. 3
1
Publication Order Number:
MC14069UB/D
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS Pchannel
and Nchannel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two LowPower TTL Loads or One LowPower
Schottky TTL Load Over the Rated Temperature Range
Triple Diode Protection on All Inputs
PinforPin Replacement for CD4069UB
Meets JEDEC UB Specifications
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
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A
= Assembly Location
WL or L
= Wafer Lot
YY or Y
= Year
WW or W = Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14069UBCP
PDIP14
2000/Box
MC14069UBD
SOIC14
2750/Box
MC14069UBDR2
SOIC14
2500/Tape & Reel
MC14069UBDT
TSSOP14
MC14069UBF
SOEIAJ14
96/Rail
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP14
P SUFFIX
CASE 646
MC14069UBCP
AWLYYWW
SOIC14
D SUFFIX
CASE 751A
TSSOP14
DT SUFFIX
CASE 948G
1
14
14069U
AWLYWW
14
069U
ALYW
1
14
SOEIAJ14
F SUFFIX
CASE 965
1
14
MC14069U
AWLYWW
MC14069UBFEL
SOEIAJ14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14069UBDTR2 TSSOP14 2500/Tape & Reel
MC14069UBDTEL TSSOP14 2000/Tape & Reel
MC14069UB
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2
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
OUT 5
IN 5
OUT 6
IN 6
V
DD
OUT 4
IN 4
OUT 2
IN 2
OUT 1
IN 1
V
SS
OUT 3
IN 3
CIRCUIT SCHEMATIC
(1/6 OF CIRCUIT SHOWN)
LOGIC DIAGRAM
13
11
9
5
3
1
12
10
8
6
4
2
V
DD
= PIN 14
V
SS
= PIN 7
V
DD
V
SS
OUTPUT
INPUT*
*Double diode protection on all
inputs not shown.
Figure 1. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR
V
DD
V
SS
7
INPUT
OUTPUT
C
L
14
20 ns
20 ns
V
DD
V
SS
V
OH
V
OL
t
THL
t
TLH
OUTPUT
INPUT
t
PHL
t
PLH
90%
50%
10%
90%
50%
10%
MC14069UB
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3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
Symbo
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Symbo
l
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
V
OL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
V
in
= 0
"1" Level
V
OH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 Vdc)
(V
O
= 9.0 Vdc)
(V
O
= 13.5 Vdc)
V
IL
5.0
10
15
--
--
--
1.0
2.0
2.5
--
--
--
2.25
4.50
6.75
1.0
2.0
2.5
--
--
--
1.0
2.0
2.5
Vdc
"1" Level
(V
O
= 0.5 Vdc)
(V
O
= 1.0 Vdc)
(V
O
= 1.5 Vdc)
V
IH
5.0
10
15
4.0
8.0
12.5
--
--
--
4.0
8.0
12.5
2.75
5.50
8.25
--
--
--
4.0
8.0
12.5
--
--
--
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
4.2
0.88
2.25
8.8
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
0.88
2.25
8.8
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(V
in
= 0)
C
in
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
--
--
--
0.25
0.5
1.0
--
--
--
0.0005
0.0010
0.0015
0.25
0.5
1.0
--
--
--
7.5
15
30
Adc
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Gate) (C
L
= 50 pF)
I
T
5.0
10
15
I
T
= (0.3
A/kHz) f + I
DD
/6
I
T
= (0.6
A/kHz) f + I
DD
/6
I
T
= (0.9
A/kHz) f + I
DD
/6
Adc
Output Rise and Fall Times
(5.)
(C
L
= 50 pF)
t
TLH
, t
THL
= (1.35 ns/pF) C
L
+ 33 ns
t
TLH
, t
THL
= (0.60 ns/pF) C
L
+ 20 ns
t
TLH
, t
THL
= (0.40 ns/pF) C
L
+ 20 ns
t
TLH
,
t
THL
5.0
10
15
--
--
--
--
--
--
--
--
--
100
50
40
200
100
80
--
--
--
--
--
--
ns
Propagation Delay Times
(5.)
(C
L
= 50 pF)
t
PLH
, t
PHL
= (0.90 ns/pF) C
L
+ 20 ns
t
PLH
, t
PHL
= (0.36 ns/pF) C
L
+ 22 ns
t
PLH
, t
PHL
= (0.26 ns/pF) C
L
+ 17 ns
t
PLH
,
t
PHL
5.0
10
15
--
--
--
--
--
--
--
--
--
65
40
30
125
75
55
--
--
--
--
--
--
ns
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
50) Vfk
where: I
T
is in
A (per package), C
L
in pF, V = (V
DD
V
SS
) in volts, f in kHz is input frequency, and k = 0.002.
MC14069UB
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4
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE M
1
7
14
8
B
A
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
18.80
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
M
10
10
N
0.015
0.039
0.38
1.01
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
H
G
D
K
C
SEATING
PLANE
N
T
14 PL
M
0.13 (0.005)
L
M
J
0.290
0.310
7.37
7.87
MC14069UB
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5
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
B
G
P
7 PL
14
8
7
1
M
0.25 (0.010)
B
M
S
B
M
0.25 (0.010)
A
S
T
T
F
R
X 45
SEATING
PLANE
D
14 PL
K
C
J
M
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
8.55
8.75
0.337
0.344
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.228
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
MC14069UB
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6
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
1.20
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.50
0.60
0.020
0.024
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4.
DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5.
DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6.
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7.
DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
_
_
_
_
S
U
0.15 (0.006) T
2X
L/2
S
U
M
0.10 (0.004)
V
S
T
L
U
SEATING
PLANE
0.10 (0.004)
T
SECTION NN
DETAIL E
J J1
K
K1
DETAIL E
F
M
W
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U
0.15 (0.006) T
V
14X REF
K
N
N
MC14069UB
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7
PACKAGE DIMENSIONS
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96501
ISSUE O
H
E
A
1
DIM
MIN
MAX
MIN
MAX
INCHES
2.05
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
9.90
10.50
0.390
0.413
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
1.42
0.056
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1.
DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2.
CONTROLLING DIMENSION: MILLIMETER.
3.
DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4.
TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5.
THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005)
M
0.10 (0.004)
D
Z
E
1
14
8
7
e
A
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
MC14069UB
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8
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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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MC14069UB/D
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