MC14007UB (4) VIEW
Semiconductor Components Industries, LLC, 2000
August, 2000 Rev. 4
1
Publication Order Number:
MC14007UB/D
MC14007UB
Dual Complementary Pair
Plus Inverter
The MC14007UB multipurpose device consists of three
Nchannel and three Pchannel enhancement mode devices packaged
to provide access to each device. These versatile parts are useful in
inverter circuits, pulseshapers, linear amplifiers, high input
impedance amplifiers, threshold detectors, transmission gating, and
functional gating.
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Lowpower TTL Loads or One Lowpower
Schottky TTL Load Over the Rated Temperature Range
PinforPin Replacement for CD4007A or CD4007UB
This device has 2 outputs without ESD Protection. Antistatic
precautions must be taken.
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Ambient Temperature Range
55 to +125
C
T
stg
Storage Temperature Range
65 to +150
C
T
L
Lead Temperature
(8Second Soldering)
260
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic "P and D/DW" Packages: 7.0 mW/
_
C From 65
_
C To 125
_
C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highimpedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v
(V
in
or V
out
)
v
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
Device
Package
Shipping
ORDERING INFORMATION
MC14007UBCP
PDIP14
2000/Box
MC14007UBD
SOIC14
55/Rail
MC14007UBDR2
SOIC14
2500/Tape & Reel
MC14007UBDT
TSSOP14
MC14007UBF
SOEIAJ14
96/Rail
See Note 1.
MARKING
DIAGRAMS
1
14
PDIP14
P SUFFIX
CASE 646
MC14007UBCP
AWLYYWW
SOIC14
D SUFFIX
CASE 751A
TSSOP14
DT SUFFIX
CASE 948G
1
14
14007U
AWLYWW
14
007U
ALYW
1
14
SOEIAJ14
F SUFFIX
CASE 965
1
14
MC14007U
ALYW
MC14007UBFEL
SOEIAJ14
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MC14007UB
http://onsemi.com
2
Figure 1. Typical Application: 2Input Analog Multiplexer
A
B
C
INPUT
INPUT
A
B
C
12
1
3
5
9
2
4
11
10
14
V
DD
6
7
V
SS
8
13
INPUT
1
0
OUTPUT CONDITION
A = C, B = OPEN
A = B, C = OPEN
Substrates of Pchannel devices internally
connected to V
DD
; substrates of Nchannel
devices internally connected to V
SS
.
11
12
13
14
8
9
10
5
4
3
2
1
7
6
GATE
C
S-P
C
OUT
C
D-P
A
V
DD
D-N
A
S-N
C
S-N
B
GATE
B
S-P
B
D-P
B
V
SS
GATE
A
D-N
B
PIN ASSIGNMENT
D = DRAIN
S = SOURCE
SCHEMATIC
14 13
2
1
11
12
6
7
8
3
4
5
10
9
V
DD
= PIN 14
V
SS
= PIN 7
MC14007UB
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
V
DD
55
_
C
25
_
C
125
_
C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ
(4.)
Max
Min
Max
Unit
Output Voltage
"0" Level
V
in
= V
DD
or 0
V
OL
5.0
10
15
--
--
--
0.05
0.05
0.05
--
--
--
0
0
0
0.05
0.05
0.05
--
--
--
0.05
0.05
0.05
Vdc
V
in
= 0 or V
DD
"1" Level
V
OH
5.0
10
15
4.95
9.95
14.95
--
--
--
4.95
9.95
14.95
5.0
10
15
--
--
--
4.95
9.95
14.95
--
--
--
Vdc
Input Voltage
"0" Level
(V
O
= 4.5 Vdc)
(V
O
= 9.0 Vdc)
(V
O
= 13.5 Vdc)
V
IL
5.0
10
15
--
--
--
1.0
2.0
2.5
--
--
--
2.25
4.50
6.75
1.0
2.0
2.5
--
--
--
1.0
2.0
2.5
Vdc
(V
O
= 0.5 Vdc)
"1" Level
(V
O
= 1.0 Vdc)
(V
O
= 1.5 Vdc)
V
IH
5.0
10
15
4.0
8.0
12.5
--
--
--
4.0
8.0
12.5
2.75
5.50
8.25
--
--
--
4.0
8.0
12.5
--
--
--
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc)
Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
3.0
0.64
1.6
4.2
--
--
--
--
2.4
0.51
1.3
3.4
5.0
1.0
2.5
10
--
--
--
--
1.7
0.36
0.9
2.4
--
--
--
--
mAdc
(V
OL
= 0.4 Vdc)
Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
--
--
--
0.51
1.3
3.4
1.0
2.5
10
--
--
--
0.36
0.9
2.4
--
--
--
mAdc
Input Current
I
in
15
--
0.1
--
0.00001
0.1
--
1.0
Adc
Input Capacitance
(V
in
= 0)
C
in
--
--
--
--
5.0
7.5
--
--
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
--
--
--
0.25
0.5
1.0
--
--
--
0.0005
0.0010
0.0015
0.25
0.5
1.0
--
--
--
7.5
15
30
Adc
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Gate) (C
L
= 50 pF)
I
T
5.0
10
15
I
T
= (0.7
A/kHz) f + I
DD
/6
I
T
= (1.4
A/kHz) f + I
DD
/6
I
T
= (2.2
A/kHz) f + I
DD
/6
Adc
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
5. The formulas given are for the typical characteristics only at 25
_
C.
6. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
50) Vfk
where: I
T
is in
A (per package), C
L
in pF, V = (V
DD
V
SS
) in volts, f in kHz is input frequency, and k = 0.003.
MC14007UB
http://onsemi.com
4
SWITCHING CHARACTERISTICS
(7.)
(C
L
= 50 pF, T
A
= 25
_
C)
Characteristic
Symbol
V
DD
Vdc
Min
Typ
(8.)
Max
Unit
Output Rise Time
t
TLH
= (1.2 ns/pF) C
L
+ 30 ns
t
TLH
= (0.5 ns/pF) C
L
+ 20 ns
t
TLH
= (0.4 ns/pF) C
L
+ 15 ns
t
TLH
5.0
10
15
--
--
--
90
45
35
180
90
70
ns
Output Fall Time
t
THL
= (1.2 ns/pF) C
L
+ 15 ns
t
THL
= (0.5 ns/pF) C
L
+ 15 ns
t
THL
= (0.4 ns/pF) C
L
+ 10 ns
t
THL
5.0
10
15
--
--
--
75
40
30
150
80
60
ns
TurnOff Delay Time
t
PLH
= (1.5 ns/pF) C
L
+ 35 ns
t
PLH
= (0.2 ns/pF) C
L
+ 20 ns
t
PLH
= (0.15 ns/pF) C
L
+ 17.5 ns
t
PLH
5.0
10
15
--
--
--
60
30
25
125
75
55
ns
TurnOn Delay Time
t
PHL
= (1.0 ns/pF) C
L
+ 10 ns
t
PHL
= (0.3 ns/pF) C
L
+ 15 ns
t
PHL
= (0.2 ns/pF) C
L
+ 15 ns
t
PHL
5.0
10
15
--
--
--
60
30
25
125
75
55
ns
7. The formulas given are for the typical characteristics only. Switching specifications are for device connected as an inverter.
8. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
Figure 2. Typical Output Source Characteristics
Figure 3. Typical Output Sink Characteristics
V
DD
= -V
GS
V
DD
= V
GS
14
14
V
DS
= V
OH
- V
DD
V
DS
= V
OL
V
SS
V
SS
7
7
I
OH
I
OL
I OH
, DRAIN CURRENT
(mAdc)
I OL
, DRAIN CURRENT
(mAdc)
0
-4.0
-8.0
-12
-16
-20
-8.0
-10
-6.0
-4.0
-2.0
-0
V
DS
, DRAIN VOLTAGE (Vdc)
20
16
12
8.0
4.0
0
0
2.0
4.0
6.0
8.0
10
V
DS
, DRAIN VOLTAGE (Vdc)
T
A
= -55
C
T
A
= +25
C
T
A
= +125
C
a
b
c
V
GS
= -5.0 Vdc
b
c
a
-10 Vdc
-15 Vdc
c
b
c
b
a
a
a
b
c
a
b
c
a
b
c
5.0 Vdc
T
A
= -55
C
T
A
= +25
C
T
A
= +125
C
a
b
c
V
GS
= 15 Vdc
10 Vdc
All unused inputs connected to ground.
All unused inputs connected to ground.
These typical curves are not guarantees, but are design aids.
Caution: The maximum current rating is 10 mA per pin.
MC14007UB
http://onsemi.com
5
Figure 4. Switching Time and Power Dissipation Test Circuit and Waveforms
PULSE
GENERATOR
V
DD
500
F
0.01
F
CERAMIC
14
C
L
V
out
V
SS
7
V
in
I
D
V
in
V
out
90%
50%
10%
90%
50%
10%
20 ns
20 ns
V
DD
V
SS
V
OH
V
OL
t
THL
t
TLH
t
PHL
t
PLH
APPLICATIONS
The MC14007UB dual pair plus inverter, which has
access to all its elements offers a number of unique circuit
applications. Figures 1, 5, and 6 are a few examples of the
device flexibility.
Figure 5. 3State Buffer
+V
DD
DISABLE 3
INPUT 10
DISABLE 6
12 OUTPUT
11
1
2
9
8
7
INPUT
DISABLE
OUTPUT
1
0
X
0
0
1
0
1
OPEN
X = Don't Care
Figure 6. AOI Functions Using Tree Logic
V
DD
14
13
11
10
3
6
B
C
A
9
5
4
8
7
1
2
OUTPUT
OUT = A+B
C
Substrates of Pchannel devices internally connected to V
DD
;
Substrates of Nchannel devices internally connected to V
SS
.
12
MC14007UB
http://onsemi.com
6
PACKAGE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE M
1
7
14
8
B
A
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
18.80
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
M
---
10 ---
10
N
0.015
0.039
0.38
1.01
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
H
G
D
K
C
SEATING
PLANE
N
T
14 PL
M
0.13 (0.005)
L
M
J
0.290
0.310
7.37
7.87
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
B
G
P
7 PL
14
8
7
1
M
0.25 (0.010)
B
M
S
B
M
0.25 (0.010)
A
S
T
T
F
R
X 45
SEATING
PLANE
D
14 PL
K
C
J
M
_
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
8.55
8.75
0.337
0.344
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.228
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
MC14007UB
http://onsemi.com
7
PACKAGE DIMENSIONS
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G01
ISSUE O
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
4.90
5.10
0.193
0.200
B
4.30
4.50
0.169
0.177
C
---
1.20
---
0.047
D
0.05
0.15
0.002
0.006
F
0.50
0.75
0.020
0.030
G
0.65 BSC
0.026 BSC
H
0.50
0.60
0.020
0.024
J
0.09
0.20
0.004
0.008
J1
0.09
0.16
0.004
0.006
K
0.19
0.30
0.007
0.012
K1
0.19
0.25
0.007
0.010
L
6.40 BSC
0.252 BSC
M
0
8
0
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
_
_
_
_
S
U
0.15 (0.006) T
2X
L/2
S
U
M
0.10 (0.004)
V
S
T
L
U
SEATING
PLANE
0.10 (0.004)
T
SECTION NN
DETAIL E
J J1
K
K1
DETAIL E
F
M
W
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U
0.15 (0.006) T
V
14X REF
K
N
N
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96501
ISSUE O
H
E
A
1
DIM
MIN
MAX
MIN
MAX
INCHES
---
2.05
---
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
9.90
10.50
0.390
0.413
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
---
1.42
---
0.056
A
1
H
E
Q
1
L
E
_
10
_
0
_
10
_
L
E
Q
1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.13 (0.005)
M
0.10 (0.004)
D
Z
E
1
14
8
7
e
A
b
VIEW P
c
L
DETAIL P
M
A
b
c
D
E
e
0.50
M
Z
MC14007UB
http://onsemi.com
8
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
CENTRAL/SOUTH AMERICA:
Spanish Phone: 3033087143 (MonFri 8:00am to 5:00pm MST)
Email: ONlitspanish@hibbertco.com
ASIA/PACIFIC: LDC for ON Semiconductor Asia Support
Phone: 3036752121 (TueFri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
00180044223781
Email: ONlitasia@hibbertco.com
JAPAN: ON Semiconductor, Japan Customer Focus Center
4321 NishiGotanda, Shinagawaku, Tokyo, Japan 1410031
Phone: 81357402745
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
MC14007UB/D
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
Fax Response Line: 3036752167 or 8003443810 Toll Free USA/Canada
N. American Technical Support: 8002829855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor European Support
German Phone: (+1) 3033087140 (MonFri 2:30pm to 7:00pm CET)
Email: ONlitgerman@hibbertco.com
French Phone: (+1) 3033087141 (MonFri 2:00pm to 7:00pm CET)
Email: ONlitfrench@hibbertco.com
English Phone: (+1) 3033087142 (MonFri 12:00pm to 5:00pm GMT)
Email: ONlit@hibbertco.com
EUROPEAN TOLLFREE ACCESS*: 0080044223781
*Available from Germany, France, Italy, UK
PDF 
ZIP