Semiconductor Components Industries, LLC, 2003

June, 2003 - Rev. 4

Publication Order Number:

NB100LVEP224/D

NB100LVEP224

2.5V/3.3V 1:24 Differential
ECL/PECL Clock Driver with
Clock Select and Output
Enable

The NB100LVEP224 is a low skew 1-to-24 differential clock

driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The part is designed for use in low
voltage applications which require a large number of outputs to drive
precisely aligned low skew signals to their destination. The two clock
inputs are differential ECL/PECL and they are selected by the
CLK_SEL pin. To avoid generation of a runt clock pulse when the
device is enabled/disabled, the Output Enable (OE) is synchronous
ensuring the outputs will only be enabled/disabled when they are
already in LOW state (See Figure 4).

The NB100LVEP224 guarantees low output-to-output skew. The

optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to "reduce power and switching noise as much as
possible." Any unused single line of a differential pair should be
terminated the same as the used line to maintain balanced loads on the
differential driver outputs. The wide VIHCMR specification allows
both pair of CLOCK inputs to accept LVDS levels.

The NB100LVEP224, as with most other ECL devices, can be

operated from a positive V

supply in LVPECL mode. This allows

the LVEP224 to be used for high performance clock distribution in
+3.3 V or +2.5 V systems. Single-ended CLK input operation is
limited to a V

3.0 V in LVPECL mode, or V

-3.0 V in NECL

mode. In a PECL environment, series or Thevenin line terminations
are typically used as they require no additional power supplies. For
more information on PECL terminations, designers should refer to
Application Note AND8020/D.

20 ps Typical Output-to-Output Skew

75 ps Typical Device-to- Device Skew

Maximum Frequency > 1 GHz

650 ps Typical Propagation Delay

LVPECL Mode Operating Range:

= 2.375 V to 3.8 V with V

= 0 V

NECL Mode Operating Range:

= 0 V with V

= -2.375 V to -3.8 V

Internal Input Pulldown Resistors

Q Output will Default Low with Inputs Open or at V

Thermally Enhanced 64-Lead LQFP

CLOCK Inputs are LVDS-Compatible; Requires External 100

LVDS Termination Resistor

64-LEAD LQFP

CASE 848G

THERMALLY ENHANCED

FA SUFFIX

Device

Package

Shipping

ORDERING INFORMATION

NB100LVEP224FA

LQFP-64

160 Units/Tray

NB100LVEP224FAR2 LQFP-64 1500/Tape & Reel

MARKING

DIAGRAM*

*For additional information, see Application Note
AND8002/D

= Assembly Location

= Wafer Lot

= Year

= Work Week

NB100

LVEP224

AWLYYWW

http://onsemi.com

NB100LVEP224

http://onsemi.com

All V

, V

CCO

, and V

pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally

conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transfer-
ring 1.2 Watts. This exposed pad is electrically connected to V

internally.

FUNCTION TABLE

OE (1)

L
L

H
H

PIN DESCRIPTION

FUNCTION

ECL Differential Input Clock
ECL Differential Input Clock
ECL Input CLK Select
ECL Output Enable
ECL Differential Outputs
Positive Supply
Negative Supply

PIN

CLK0*, CLK0**
CLK1*, CLK1**
CLK_SEL*
OE*
Q0-Q23, Q0-Q23
V

, V

CCO

***

Figure 1. 64-Lead LQFP Pinout (Top View)

CCO

CLK0

CLK_SEL

CLK1

Q10

CCO

Q15

Q16

Q17

CCO

CLK_SEL

Q0-Q23

CLK0
CLK1

L
L

CLK0
CLK1

H
H

1. The OE (Output Enable) signal is synchronized with the

falling edge of the LVPECL_CLK signal.

NB100LVEP224

* Pins will default LOW when left open.
** Pins will default HIGH when left open.
*** The thermally conductive exposed pad on the bottom of the
package is electrically connected to V

internally.

Q23

CCO

Q22

Q18

Q19

Q20

Q21

Q12

Q13

Q14

NB100LVEP224

http://onsemi.com

Figure 2. Logic Diagram

CLK_SEL

CLK0

CLK1

Q0-Q23

ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

75 k

Internal Input Pullup Resistor

37.5 k

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 150 V

> 2 kV

Moisture Sensitivity (Note 1)

Level 3

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

Transistor Count

654 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, refer to Application Note AND8003/D.

MAXIMUM RATINGS

(Note 2)

Symbol

Parameter

Condition 1

Condition 2

Rating

Units

PECL Mode Power Supply

= 0 V

NECL Mode Power Supply

= 0 V

-6

PECL Mode Input Voltage
NECL Mode Input Voltage

= 0 V

6 to 0

-6 to 0

Operating Temperature Range

0 to +85

stg

Storage Temperature Range

-65 to +150

Thermal Resistance (Junction-to-Ambient)
(See Application Information)

0 LFPM

500 LFPM

64 LQFP
64 LQFP

35.6

C/W

Thermal Resistance (Junction-to-Case)
(See Application Information)

0 LFPM

500 LFPM

64 LQFP
64 LQFP

3.2
6.4

C/W

sol

Wave Solder

< 2 to 3 sec @ 248

265

2. Maximum Ratings are those values beyond which device damage may occur.

NB100LVEP224

http://onsemi.com

LVPECL DC CHARACTERISTICS

= 2.5 V; V

= 0 V (Note 3)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Power Supply Current

130

160

195

135

165

200

140

165

205

Output HIGH Voltage (Note 8)

1355

1480

1605

1355

1480

1605

1355

1480

1605

Output LOW Voltage (Note 8)

555

680

900

555

680

900

555

680

900

Input HIGH Voltage (Single-Ended)
(Note 9)

1335

1620

1335

1620

1275

1620

Input LOW Voltage (Single-Ended)
(Note 9)

555

900

555

900

555

900

IHCMR

Input HIGH Voltage Common Mode
Range (Differential) (Note 10)

CLK/CLK

1.2

2.5

1.2

2.5

1.2

2.5

Input HIGH Current

150

Input LOW Current

CLK
CLK

0.5

-150

0.5

-150

0.5

-150

NOTE:

100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been

established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is
maintained.

3. Input and output parameters vary 1:1 with V

. V

can vary + 0.125 V to -1.3 V.

4. All outputs loaded with 50

to V

- 2.0 V.

5. Do not use V

at VCC < 3.0 V.

6. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differen-

tial input signal.

LVPECL DC CHARACTERISTICS

= 3.3 V; V

= 0 V (Note 7)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Power Supply Current

140

165

195

145

175

205

145

175

210

Output HIGH Voltage (Note 8)

2155

2280

2405

2155

2280

2405

2155

2280

2405

Output LOW Voltage (Note 8)

1355

1480

1700

1355

1480

1700

1355

1480

1700

Input HIGH Voltage (Single-Ended)
(Note 9)

2135

2420

2135

2420

2135

2420

Input LOW Voltage (Single-Ended)
(Note 9)

1355

1700

1355

1700

1355

1700

IHCMR

Input HIGH Voltage Common Mode
Range (Differential) (Note 10) (Figure
5)

1.2

3.3

1.2

3.3

1.2

3.3

Input HIGH Current

150

Input LOW Current

CLK
CLK

0.5

-150

0.5

-150

0.5

-150

NOTE:

100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.

The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

7. Input and output parameters vary 1:1 with V

. V

can vary +0.925 V to -0.5 V.

8. All outputs loaded with 50

to V

- 2.0 V.

9. Single ended input operation is limited V

3.0 V in LVPECL mode.

10. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differential

input signal.

NB100LVEP224

http://onsemi.com

NECL DC CHARACTERISTICS

= 0 V, V

= -2.375 V to -3.8 V (Note 11)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Power Supply Current

= -2.5 V

= -3.3 V

130
140

160
165

195
195

135
145

165
175

200
205

140
145

165
175

205
210

Output HIGH Voltage (Note 12)

-1 145

-1020

-895

-1 145

-1020

-895

-1 145

-1020

-895

Output LOW Voltage (Note 12)

-1945

-1820

-1600

-1945

-1820

-1600

-1945

-1820

-1600

Input HIGH Voltage (Single-Ended)
(Note 13)

-1 165

-880

-1 165

-880

-1 165

-880

Input LOW Voltage (Single-Ended)
(Note 13)

-1945

-1600

-1945

-1600

-1945

-1600

IHCMR

Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
(Figure 5)

+ 1.2

0.0

+ 1.2

0.0

+ 1.2

0.0

Input HIGH Current

150

Input LOW Current

CLK
CLK

0.5

-150

0.5

-150

0.5

-150

NOTE:

100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established.

The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.

11. Input and output parameters vary 1:1 with V

12. All outputs loaded with 50

to V

- 2.0 V.

13. Single ended input operation is limited V

-3.0 V in NECL mode.

14. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differential

input signal.

AC CHARACTERISTICS

= 2.375 V to 3.8 V; V

= 0 V (Note 15)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Opp

Differential Output Voltage
(Figure 3)

out

< 50 MHz

out

< 0.8 GHz

out

< 1.0 GHz

600
600
600

750
750
700

600
600
525

725
725
650

575
550
400

700
650
525

mV
mV
mV

PLH

PHL

Propagation Delay (Differential)

CLKx-Qx

CLK_SELx-Qx

500
600

600
700

700
800

550
650

650
800

750
900

650
750

750
850

1000

1150

ps
ps

skew

Within-Device Skew (Note 16)
Device-to-Device Skew (Note 17)

20
50

300

20
50

300

100

300

ps
ps

JITTER

Random Clock Jitter (Figure 3) (RMS)

Input Swing (Differential) (Note 19) (Figure 5)

200

800

1200

200

800

1200

200

800

1200

OE Set Up Time (Note 18)

200

OE Hold Time

200

Output Rise/Fall Time

(20%-80%)

100

200

300

100

200

300

150

250

350

15. Measured with PECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50

to V

- 2 V.

16. Skew is measured between outputs under identical transitions and conditions on any one device.
17. Device-to-Device skew for identical transitions at identical V

levels.

18. OE Set Up Time is defined with respect to the falling edge of the clock. OE High-to-Low transition ensures outputs remain disabled during

the next clock cycle. OE Low-to-High transition enables normal operation of the next input clock.

19. V

is the differential input voltage swing required to maintain AC characteristics including t

and device-to-device skew.

NB100LVEP224

http://onsemi.com

Figure 3. Output Amplitude (V

OPP

) versus Input Frequency and Random Clock Jitter (t

JITTER

)

INPUT FREQUENCY (GHz)

0.5 0.6

0.7

0.8

1.3

1.5

800

900

700

600

500

400

300

200

OUTPUT AMPLITUDE (mV)

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0

RMS JITTER (ps)

Q AMP (mV)

RMS JITTER (ps)

1.0

0.9

1.4

1.2

1.1

2.5 V
3.3 V

Figure 4. Output Enable (OE) Timing Diagram

CLK

Figure 5. LVPECL Differential Input Levels

(DIFF)

(LVPECL)

IHCMR

Resource Reference of Application Notes

AN1405

ECL Clock Distribution Techniques

AND8002

Marking and Date Codes

AND8009

ECLinPS Plus Spice I/O Model Kit

AND8020

Termination of ECL Logic Devices

For an updated list of Application Notes, please see our website at http://onsemi.com.

NB100LVEP224

http://onsemi.com

APPLICATIONS INFORMATION

Using the thermally enhanced package of the
NB100LVEP224

The NB100LVEP224 uses a thermally enhanced 64-lead

LQFP package. The package is molded so that a portion of
the leadframe is exposed at the surface of the package
bottom side. This exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the NB100LVEP224 high-speed bipolar integrated circuit
and will ease the power management task for the system
design. In multilayer board designs, a thermal land pattern
on the printed circuit board and thermal vias are
recommended to maximize both the removal of heat from
the package and electrical performance of the
NB100LVEP224. The size of the land pattern can be larger,
smaller, or even take on a different shape than the exposed
pad on the package. However, the solderable area should be
at least the same size and shape as the exposed pad on the
package. Direct soldering of the exposed pad to the thermal
land will provide an efficient thermal conduit. The thermal
vias will connect the exposed pad of the package to internal
copper planes of the board. The number of vias, spacing, via
diameters and land pattern design depend on the application
and the amount of heat to be removed from the package.

Maximum thermal and electrical performance is achieved

when an array of vias is incorporated in the land pattern.

The recommended thermal land design for

NB100LVEP224 applications on multi-layer boards
comprises a 4 X 4 thermal via array using a 1.2 mm pitch as
shown in Figure 6 providing an efficient heat removal path.

Figure 6. Recommended Thermal Land Pattern

All Units mm

Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter

Exposed Pad
Land Pattern

4.6

The via diameter should be approximately 0.3 mm with

1 oz. copper via barrel plating. Solder wicking inside the via
may result in voiding during the solder process and must be
avoided. If the copper plating does not plug the vias, stencil
print solder paste onto the printed circuit pad. This will

supply enough solder paste to fill those vias and not starve
the solder joints. The attachment process for the exposed pad
package is equivalent to standard surface mount packages.
Figure 7, "Recommended solder mask openings", shows a
recommended solder mask opening with respect to a 4 X 4
thermal via array. Because a large solder mask opening may
result in a poor rework release, the opening should be
subdivided as shown in Figure 7. For the nominal package
standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should
be considered.

Figure 7. Recommended Solder Mask Openings

All Units mm

Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter

Exposed Pad
Land Pattern

4.6

0.2

1.0

0.2

Proper thermal management is critical for reliable system

operation. This is especially true for high-fanout and high
output drive capability products.

For thermal system analysis and junction temperature

calculation the thermal resistance parameters of the package
is provided:

Table 1. Thermal Resistance *

LFPM

C/W

35.6

3.2

100

32.8

4.9

500

30.0

6.4

* Junction to ambient and Junction to board, four-conductor
layer test board (2S2P) per JESD 51-8

These recommendations are to be used as a guideline,

only. It is therefore recommended that users employ
sufficient thermal modeling analysis to assist in applying the
general recommendations to their particular application to
assure adequate thermal performance. The exposed pad of
the NB100LVEP224 package is electrically shorted to the
substrate of the integrated circuit and V

. The thermal land

should be electrically connected to V

NB100LVEP224

http://onsemi.com

PACKAGE DIMENSIONS

LQFP

FA SUFFIX

64-LEAD PACKAGE

CASE 848G-02

ISSUE A

ÉÉÉÉ

-Y-

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MM.

3. DATUM PLANE E" IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING PLANE.

4. DATUM X", Y" AND Z" TO BE DETERMINED AT

DATUM PLANE DATUM E".

5. DIMENSIONS M AND L TO BE DETERMINED AT

SEATING PLANE DATUM T".

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25

(0.010) PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLAND E".

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL NOT CAUSE THE LEAD

WIDTH TO EXCEED THE MAXIMUM D DIMENSION

BY MORE THAN 0.08 (0.003). DAMBAR CANNOT

BE LOCATED ON THE LOWER RADIUS OR THE

FOOT. MINIMUM SPACE BETWEEN PROTRUSION

AND ADJACENT LEAD OR PROTRUSION 0.07

(0.003).

8. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

DIM

MIN

MAX

MIN

MAX

INCHES

10.00 BSC

0.394 BSC

MILLIMETERS

10.00 BSC

0.394 BSC

1.35

1.45

0.053

0.057

0.17

0.27

0.007

0.011

0.45

0.75

0.018

0.030

0.50 BSC

0.020 BSC

1.00 REF

0.039 BSC

0.09

0.20

0.004

0.008

0.05

0.15

0.002

0.006

12.00 BSC

0.472 BSC

12.00 BSC

0.472 BSC

0.20 0.008

---

1.60

---

0.063

0.17

0.23

0.007

0.009

0.09

0.16

0.004

0.006

0.08

---

0.003

---

0.08

---

0.003

---

4.50

4.78

0.180

0.188

0.05 (0.002)

B/2

-X-

L/2

-Z-

M/2

A/2

0.20 (0.008) T X-Y

4 PL

0.20 (0.008) E X-Y

-T-

SEATING
PLANE

G/2

4 PL

64 PL

0.08 (0.003)

T X-Y

-E-

0.08 (0.003) T

EXPOSED PAD

VIEW AG-AG

DETAIL AH

ÇÇÇÇ

DETAIL AJ-AJ

REF

BASE

METAL

PLATING

0.08 (0.003)

Y T-U

0.25

GAGE

PLANE

60 PL

---

4.50

4.78

0.180

0.188

NB100LVEP224

http://onsemi.com

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

JAPAN: ON Semiconductor, Japan Customer Focus Center

2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

NB100LVEP224/D

Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com

N. American Technical Support: 800-282-9855 Toll Free USA/Canada

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NB100LVEP224

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NB100LVEP224