Semiconductor Components Industries, LLC, 2004

December, 2004 - Rev. 5

Publication Order Number:

NB100LVEP56/D

NB100LVEP56

2.5V / 3.3V / 5V ECL Dual

Differential 2:1 Multiplexer

The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The

differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
both ECL and CMOS input voltage levels. Multiple V

pins are

provided.

The V

pin, an internally generated voltage supply, is available to

this device only. For single-ended input operation, the unused
differential input is connected to V

as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V

and V

via a 0.01

mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, V

should be left open.

Maximum Input Clock Frequency > 2.5 GHz Typical

Maximum Input Data Rate > 2.5 Gb/s Typical

525 ps Typical Propagation Delays

Low Profile QFN Package

PECL Mode Operating Range:

= 2.375 V to 5.5 V with V

= 0 V

NECL Mode Operating Range:

= 0 V with V

= -2.375 V to -5.5 V

Separate, Common Select, and Individual Select

(Compatible with ECL and CMOS Input Voltage Levels)

Q Output Will Default LOW with Inputs Open or at V

Multiple V

Outputs

Pb-Free Packages are Available*

*For additional information on our Pb-Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

TSSOP-20

DT SUFFIX

CASE 948E

MARKING

DIAGRAMS*

*For additional information, see Application Note

AND8002/D

N100

VP56

ALYW

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week

N100

VP56

ALYW

QFN-24

MN SUFFIX

CASE 485L

See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

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NB100LVEP56

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Table 1. PIN FUNCTION DESCRIPTION

Pin No.

Default

ÁÁÁÁÁ

TSSOP

ÁÁÁÁ

QFN

Name

I/O

Default

State

Description

14,20

3,9,18,19,

Positive Supply Voltage. All VCC Pins must be Externally

Connected to Power Supply to Guarantee Proper Operation.

15,24

Negative Supply Voltage. All VEE Pins must be Externally

Connected to Power Supply to Guarantee Proper Operation.

3,8

6,12

BB0

BB1

ECL Reference Voltage Output

D0a

ECL Input

Low

Noninverted Differential Data a Input to MUX 0. Internal 75 kW to

D0a

ECL Input

High

Inverted Differential Data a Input to MUX 0. Internal 75 kW to V

and 37 kW to V

D0b

ECL Input

Low

Noninverted Differential Data b Input to MUX 0. Internal 75 kW to

D0b

ECL Input

High

Inverted Differential Data b Input to MUX 0. Internal 75 kW to V

and 37 kW to V

D1a

ECL Input

Low

Noninverted Differential Data a Input to MUX 1. Internal 75 kW to

D1a

ECL Input

High

Inverted Differential Data a Input to MUX 1. Internal 75 kW to V

and 37 kW to V

D1b

ECL Input

Low

Noninverted Differential Data b Input to MUX 1. Internal 75 kW to

D1b

ECL Input

High

Inverted Differential Data b Input to MUX 1. Internal 75 kW to V

and 37 kW to V

ECL Output

Noninverted Differential Output MUX 0. Typically Terminated with

50 W to V

= V

- 2.0 V.

ECL Output

Inverted Differential Output MUX 0. Typically Terminated with

50 W to V

= V

- 2.0 V.

ECL Output

Noninverted Differential Output MUX 1. Typically Terminated with

50 W to V

= V

- 2.0 V.

ECL Output

Inverted Differential Output MUX 1. Typically Terminated with

50 W to V

= V

- 2.0 V.

SEL0

ECL, CMOS

Input

Low

Noninverted Differential Select Input to MUX 0. Internal 75 W to

COM_SEL

ECL, CMOS

Input

Low

Noninverted Differential Common Select Input to Both MUX.

Internal 75 W to V

SEL1

ECL, CMOS

Input

Low

Noninverted Differential Select Input to MUX 1. Internal 75 W to

N/A

Exposed Pad. (Note 1)

1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit.

NB100LVEP56

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D0b

D1a

BBO

SEL0

SEL1

D0a

D1a

D0a

COM_SEL

BB1

D1b

SEL0

L
L

H
H

Table 2. TRUTH TABLE

Q0, Q0

a
b
b
a
a

SEL1

H
H

COM_SEL

L
L
L
L

Q1, Q1

a
b
a
a
b

NB100LVEP56

D0b

D0a

SEL0

SEL1

D1a D1a

COM

SEL

NB100LVEP56

D0a

BB0

BB1

D1b

Exposed Pad
(EP)

D0b

D1a

SEL0

SEL1

D0a

D1a

D0a

COM_SEL

D1b

Figure 1. Logic Diagram

Figure 2. TSSOP-20 Lead Pinout (Top View)

Figure 3. QFN-24 Lead Pinout (Top View)

Table 3. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

(R1)

75 kW

Internal Input Pullup Resistor

(R2)

37 kW

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 150 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

Transistor Count

354 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

NB100LVEP56

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Table 4. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

Positive Mode Power Supply

= 0 V

Negative Mode Power Supply

= 0 V

-6

Positive Mode Input Voltage

Negative Mode Input Voltage

= 0 V

v V

w V

-6

V
V

out

Output Current

Continuous

Surge

100

mA
mA

Sink/Source

"0.5

Operating Temperature Range

-40 to +85

°C

stg

Storage Temperature Range

-65 to +150

°C

Thermal Resistance (Junction-to-Ambient)

JEDEC 51-3 (1S - Single Layer Test Board)

0 lfpm

500 lfpm

TSSOP-20

140

°C/W

Thermal Resistance (Junction-to-Ambient)

JEDEC 51-6 (2S2P-Multi Layer Test Board)

with Filled Thermal Vias

0 lfpm

500 lfpm

QFN-24

37
32

°C/W

Thermal Resistance (Junction-to-Case)

Standard Board

TSSOP-20

QFN-24

23 to 41

°C/W

sol

Wave Solder

Pb-Free

<2 to 3 sec @ 248°C

<2 to 3 sec @ 260°C

265
265

°C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

Table 5. DC CHARACTERISTICS, PECL

= 2.5 V, V

= 0 V (Note 2)

-40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current

Output HIGH Voltage (Note 3)

1355 1480 1605

1355

1480

1605

1355

1480

1605

Output LOW Voltage (Note 3)

555

775

900

555

775

900

555

775

900

Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs) (Note 4)

1335

1620

1335

1620

1275

1620

Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs) (Note 4)

555

875

555

875

555

875

IHCMR

Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 5)

1.2

2.5

1.2

2.5

1.2

2.5

Input HIGH Current (@V

)

150

Input LOW Current (@V

)

D
D

SEL

0.5

-150

0.5

-150

0.5

-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

2. Input and output parameters vary 1:1 with V

. V

can vary +0.125 V to -1.3 V.

3. All loading with 50 W to V

- 2.0 V.

4. Do not use V

at V

< 3.0 V.

5. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differential

input signal.

NB100LVEP56

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Table 6. DC CHARACTERISTICS, PECL

= 3.3 V, V

= 0 V (Note 6)

-40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current

Output HIGH Voltage (Note 7)

2155 2280 2405 2155 2280 2405

2155

2280

2405

Output LOW Voltage (Note 7)

1355 1575 1700 1355 1575 1700

1355

1575

1700

Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)

2135

2420

2135

2420

2135

2420

Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)

1355

1675

1355

1675

1355

1675

Output Reference Voltage (Note 8)

1775 1875 1975 1775 1875 1975

1775

1875

1975

IHCMR

Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 9)

1.2

3.3

1.2

3.3

1.2

3.3

Input HIGH Current (@V

)

150

Input LOW Current (@V

)

D
D

SEL

0.5

-150

0.5

-150

0.5

-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

6. Input and output parameters vary 1:1 with V

. V

can vary +0.925 V to -0.5 V.

7. All loading with 50 W to V

- 2.0 V.

8. Single-Ended input operation is limited to V

w 3.0 V in PECL mode.

9. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differential

input signal.

Table 7. DC CHARACTERISTICS, PECL

= 5.0 V, V

= 0 V (Note 10)

-40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current

Output HIGH Voltage (Note 11)

3855 3980 4105 3855 3980 4105

3855

3980

4105

Output LOW Voltage (Note 11)

3055 3275 3400 3055 3275 3400

3055

3275

3400

Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)

3775

4120

3775

4120

3775

4120

Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)

3055

3375

3055

3375

3055

3375

Output Voltage Reference

3475 3575 3675 3475 3575 3675

3475

3575

3675

IHCMR

Input HIGH Voltage Common Mode Range

(Differential Configuration) (Note 12)

1.2

5.0

1.2

5.0

1.2

5.0

Input HIGH Current (@V

)

150

Input LOW Current (@V

)

D
D

SEL

0.5

-150

0.5

-150

0.5

-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

10.Input and output parameters vary 1:1 with V

. V

can vary +2.0 V to -0.5 V.

11. All loading with 50 W to V

- 2.0 V.

12.V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differential

input signal.

NB100LVEP56

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Table 8. DC CHARACTERISTICS, NECL

= 0 V, V

= -3.8 V to -2.375 V (Note 13)

-40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current

Output HIGH Voltage (Note 14)

-1145 -1020

-895

-1145 -1020

-895

-1145 -1020

-895

Output LOW Voltage (Note 14)

-1945 -1725 -1600 -1945 -1725 -1600 -1945 -1725 -1600

Input HIGH Voltage

(SEL0, SEL1, COM_SEL)

Input HIGH Voltage (D Inputs)

-1165

-880

-1165

-880

-1165

-880

Input LOW Voltage

(SEL0, SEL1, COM_SEL)

Input LOW Voltage (D Inputs)

-1945

-1600

-1945

-1600

-1945

-1600

Output Reference Voltage (Note 15)

-1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325

IHCMR

Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 16)

+1.2

0.0

+1.2

0.0

+1.2

0.0

Input HIGH Current (@V

)

150

Input LOW Current (@V

)

D
D

SEL

0.5

-150
-150

0.5

-150
-150

0.5

-150
-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

13.Input and output parameters vary 1:1 with V

14.All loading with 50 W to V

- 2.0 V.

15.Single-Ended input operation is limited to V

from -3.0 V to -5.5 V in NECL mode.

16.V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differential

input signal.

Table 9. DC CHARACTERISTICS, NECL

= 0 V, V

= -3.8 V to -5.5 V (Note 17)

-40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current

Output HIGH Voltage (Note 18)

-1145 -1020

-895

-1145 -1020

-895

-1145 -1020

-895

Output LOW Voltage (Note 18)

-1945 -1725 -1600 -1945 -1725 -1600 -1945 -1725 -1600

Input HIGH Voltage

(SEL0, SEL1, COM_SEL)

Input HIGH Voltage (D Inputs)

-1165

-880

-1165

-880

-1165

-880

Input LOW Voltage

(SEL0, SEL1, COM_SEL)

Input LOW Voltage (D Inputs)

-1945

-1600

-1625

-1945

-1600

-1625

-1945

-1600

-1625

Output Reference Voltage (Note 19)

-1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325

IHCMR

Input HIGH Voltage Common Mode

Range (Differential Configuration)

(Note 20)

+1.2

0.0

+1.2

0.0

+1.2

0.0

Input HIGH Current (@V

)

150

Input LOW Current (@V

)

D
D

SEL

0.5

-150
-150

0.5

-150
-150

0.5

-150
-150

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

17.Input and output parameters vary 1:1 with V

18.All loading with 50 W to V

- 2.0 V.

19.Single-Ended input operation is limited to V

from -3.0 V to -5.5 V in NECL mode.

20.V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differential

input signal.

NB100LVEP56

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Table 10. AC CHARACTERISTICS

= 0 V; V

= -2.375 V to -3.8 V or V

= 2.375 V to 3.8 V; V

= 0 V (Note 21)

-40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

OUTPP

Output Voltage Amplitude

v 1 GHz

(See Figure 4)

= 2 GHz

= 2.5 GHz

525

500

400

700

600

500

550

500

350

700

600

450

500

400

200

700

500

300

PLH

PHL

Propagation Delay to Output Differential

D to Q, Q

SEL to Q, Q

COM_SEL to Q, Q

375

575

550

500

775

750

625

975

950

400

625

600

525

825

800

650

1025

1000

450

700

575

900

700

1100

Skew

Pulse Skew (Note 22)

Within Device Input Skew (Note 23)

Within Device Output Skew (Note 24)

Device-to-Device Skew (Note 25)

200

JITTER

RMS Random Clock Jitter

= 2.5 GHz

(Note 26)

Peak-to-Peak Data Dependent Jitter

=1.5 Gb/s

(Note 27)

= 2.5 Gb/s

INPP

Input Voltage Swing (Differential Configuration)

(Note 28)

150

800

1200 150

800

1200 150

800

1200

Output Rise/Fall Times @ 50 MHz

Q, Q

(20% - 80%)

110

150

120

170

140

230

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

21.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V

- 2.0 V. Input edge rates 150 ps (20% - 80%).

22.Pulse Skew |t

PLH

- t

PHL

23.Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input.

24.Worst case difference between Q0 and Q1 outputs.

25.Skew is measured between outputs under identical transitions.

26.Additive RMS jitter with 50% Duty Cycle Clock Signal at f

= 2.5 GHz.

27.Additive Peak-to-Peak jitter with input NRZ data at PRBS 2

-1 at f

= 2.5 Gb/s.

28.Input voltage swing is a single-ended measurement operating in differential mode.

NB100LVEP56

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Table 11. AC CHARACTERISTICS

= 0 V; V

= -4.2 V to -5.5 V or V

= 4.2 V to 5.5 V; V

= 0 V (Note 29)

-40°C

25°C

85°C

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

OUTPP

Output Voltage Amplitude

v 1 GHz

(See Figure 5)

= 2 GHz

= 2.5 GHz

600

550

400

750

650

550

600

500

350

750

600

450

600

400

200

750

500

300

PLH

PHL

Propagation Delay to Output Differential

D to Q, Q

SEL to Q, Q

COM_SEL to Q, Q

375

575

550

500

775

750

625

975

950

400

625

600

525

825

800

650

1025

1000

450

700

575

900

700

1100

Skew

Pulse Skew (Note 30)

Within Device Input Skew (Note 31)

Within Device Output Skew (Note 32)

Device-to-Device Skew (Note 33)

200

JITTER

RMS Random Clock Jitter

= 2.5 GHz

(Note 34)

Peak-to-Peak Data Dependent Jitter

=1.5 Gb/s

(Note 35)

= 2.5 Gb/s

INPP

Input Voltage Swing (Differential Configuration)

(Note 36)

150

800

1200 150

800

1200 150

800

1200

Output Rise/Fall Times @ 50 MHz

Q, Q

(20% - 80%)

110

150

120

170

140

230

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

29.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V

- 2.0 V. Input edge rates 150 ps (20% - 80%).

30.Pulse Skew |t

PLH

- t

PHL

31.Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input.

32.Worst case difference between Q0 and Q1 outputs.

33.Skew is measured between outputs under identical transitions.

34.Additive RMS jitter with 50% Duty Cycle Clock Signal at f

= 2.5 GHz.

35.Additive Peak-to-Peak jitter with input NRZ data at PRBS 2

-1 at f

= 2.5 Gb/s.

36.Input voltage swing is a single-ended measurement operating in differential mode.

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Figure 4. Output Voltage Amplitude (V

OUTPP

) / RMS Jitter vs.

Input Frequency (f

) at V

= 2.5 V, 255C

INPUT FREQUENCY (GHz)

OUTPUT

VOL

T
AGE AMPLITUDE (mV)

250

350

450

550

650

750

850

0.5

1.0

1.5

2.0

2.5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

RMS JITTER (ps)

Q AMP (mV)

JITTER (ps)

250

350

450

550

650

750

850

0.5

1.0

1.5

2.0

2.5

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

INPUT FREQUENCY (GHz)

OUTPUT

VOL

T
AGE AMPLITUDE (mV)

RMS JITTER (ps)

Q AMP (mV)

JITTER (ps)

Figure 5. Output Voltage Amplitude (V

OUTPP

) / RMS Jitter vs.

Input Frequency (f

) at V

= 5.0 V, 255C

Figure 6. AC Reference Measurement

PHL

PLH

INPP

= V

(D) - V

(D)

OUTPP

= V

(Q) - V

(Q)

NB100LVEP56

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Figure 7. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D - Termination of ECL Logic Devices.)

Driver

Device

Receiver

Device

= 50 W

50 W

= V

- 2.0 V

ORDERING INFORMATION

Device

Package

Shipping

NB100LVEP56DT*

TSSOP-20

(Pb-Free)

75 Units / Rail

NB100LVEP56DTR2*

TSSOP-20

(Pb-Free)

2500 Tape & Reel

NB100LVEP56MN

QFN-24

92 Units / Rail

NB100LVEP56MNG

QFN-24

(Pb-Free)

92 Units / Rail

NB100LVEP56MNR2

QFN-24

3000 Tape & Reel

NB100LVEP56MNR2G

QFN-24

(Pb-Free)

3000 Tape & Reel

*These devices are manufactured with a Pb-Free external lead finish only.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specification Brochure, BRD8011/D.

NB100LVEP56

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PACKAGE DIMENSIONS

TSSOP-20

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948E-02

ISSUE B

DIM

MIN

MAX

MIN

MAX

INCHES

6.60

0.260

MILLIMETERS

4.30

4.50

0.169

0.177

1.20

0.047

0.05

0.15

0.002

0.006

0.50

0.75

0.020

0.030

0.65 BSC

0.026 BSC

0.27

0.37

0.011

0.015

0.09

0.20

0.004

0.008

0.09

0.16

0.004

0.006

0.19

0.30

0.007

0.012

0.19

0.25

0.007

0.010

6.40 BSC

0.252 BSC

0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER

SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER

SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE -W-.

ÍÍÍÍ

PIN 1

IDENT

-T-

0.100 (0.004)

SECTION N-N

J J1

-W-

SEATING

PLANE

-V-

-U-

0.10 (0.004)

20X REF

L/2

0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40

0.252

---

0.15 (0.006) T

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