November, 2005 - Rev. 1

Publication Order Number:

NB4N11M/D

NB4N11M

3.3 V 2.5 Gb/s Multi Level

Clock/Data Input to CML

Receiver/ Buffer/ Translator

Description

T h e N B4 N 11 M i s a d i ff e r e n t i a l 1 -t o -2 c l o c k / d a t a

distribution/translation chip with CML output structure, targeted for
high-speed clock/data applications. The device is functionally
equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device
produces two identical differential output copies of clock or
data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,
NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and
other clock/data distribution applications.

Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS

(See Table 5). The CML outputs are 16 mA open collector
(See Figure 18) which requires resistor (R

) load path to V

termination voltage. The open collector CML outputs must be
terminated to V

at power up. Differential outputs produces

currentmode logic (CML) compatible levels when receiver loaded
with 50

W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies

(see Figure 19). This simplifies device interface by eliminating a need
for coupling capacitors.

The device is offered in a small 8-pin TSSOP package.
Application notes, models, and support documentation are available

at www.onsemi.com.

Features

Maximum Input Clock Frequency > 2.5 GHz

Maximum Input Data Rate > 2.5 Gb/s

Typically 1 ps of RMS Clock Jitter

Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, R

= 25

420 ps Typical Propagation Delay

150 ps Typical Rise and Fall Times

Operating Range: V

= 3.0 V to 3.6 V with V

= 0 V and

= 1.8 V to 3.6 V

Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,

EP, and SG Devices

These are Pb-Free Devices*

*For additional information on our Pb-Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

MARKING

DIAGRAM*

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TSSOP-8

DT SUFFIX

CASE 948R

E11M

ALYWG

See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb-Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

Figure 1. Functional Block Diagram

NB4N11M

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Figure 2. Pinout (Top View) and Logic Diagram

Table 1. Pin Description

Pin

Name

I/O

Description

CML Output

Noninverted differential output. Typically receiver terminated with 50 W

resistor to V

. Open collector CML outputs must be terminated to V

powerup.

CML Output

Inverted differential output. Typically receiver terminated with 50 W resistor

to V

. Open collector CML outputs must be terminated to V

at powerup.

CML Output

Noninverted differential output. Typically receiver terminated with 50 W

resistor to V

. Open collector CML outputs must be terminated to V

powerup.

CML Output

Inverted differential output. Typically receiver terminated with 50 W resistor

to V

. Open collector CML outputs must be terminated to V

at powerup.

Negative supply voltage.

LVPECL, CML, HSTL,

LVCMOS, LVDS, LVTTL Input

Inverted differential input.

LVPECL, CML, HSTL,

LVCMOS, LVDS, LVTTL Input

Noninverted differential input.

Positive supply voltage.

NB4N11M

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Table 2. ATTRIBUTES

Characteristics

Value

ESD Protection

Human Body Model

Machine Model

> 1000 V

> 70 V

Moisture Sensitivity (Note 1)

8-TSSOP

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

Transistor Count

197

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

Positive Power Supply

= -0.5 V

Negative Power Supply

= +0.5 V

-4

Positive Input

Negative Input

= 0 V

= V

+0.4 V

= V

0.4 V

-4

Output Voltage

Minimum

Maximum

+ 600

+ 400

Operating Temperature Range

-40 to +85

°C

stg

Storage Temperature Range

-65 to +150

°C

Thermal Resistance (Junction-to-Ambient)

(Note 2)

0 lfpm

500 lfpm

TSSOP-8

190

130

°C/W

Thermal Resistance (Junction-to-Case)

1S2P (Note 2)

TSSOP-8

41 to 44

°C/W

sol

Wave Solder

< 3 Sec @ 260°C

265

°C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit

values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

2. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.

NB4N11M

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Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs

= 3.0 V to 3.6 V, V

= 0 V, T

= -40°C to +85°C

Symbol

Characteristic

Min

Typ

Max

Unit

Power Supply Current (Inputs and Outputs Open)

= 50 W, V

= 3.6 V to 2.5 V

Output HIGH Voltage (Note 3)

- 60

- 10

Output LOW Voltage (Note 3)

- 1100

- 800

- 640

Differential Output Voltage Magnitude

640

780

1000

= 25 W, V

= 3.6 V to 2.5 V $5%

Output HIGH Voltage (Note 3)

- 60

- 10

Output LOW Voltage (Note 3)

- 550

- 400

- 320

Differential Output Voltage Magnitude

320

390

500

= 50 W, V

= 1.8 V $5%

Output HIGH Voltage (Note 3)

- 170

- 10

Output LOW Voltage (Note 3)

- 1100

- 800

- 640

Differential Output Voltage Magnitude

570

780

1000

= 25 W, V

= 1.8 V $5%

Output HIGH Voltage (Note 3)

- 85

- 10

Output LOW Voltage (Note 3)

- 500

- 400

- 320

Differential Output Voltage Magnitude

285

390

500

DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 14 and 16)

Input Threshold Reference Voltage Range (Note 5)

Single-ended Input HIGH Voltage

+ 100

+ 400

Single-ended Input LOW Voltage

- 400

- 100

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15 and 17)

IHD

Differential Input HIGH Voltage

+ 400

ILD

Differential Input LOW Voltage

- 400

- 100

CMR

Input Common Mode Range (Differential Configuration)

Differential Input Voltage Magnitude (|V

IHD

- V

ILD

|) (Note 7)

100

- V

Input Capacitance (Note 7)

1.5

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.

3. CML outputs require R

receiver termination resistors to V

for proper operation. Outputs must be connected through R

to V

at power

up. The output parameters vary 1:1 with V

4. Input parameters vary 1:1 with V

5. V

is applied to the complementary input when operating in single-ended mode.

6. V

CMR

(MIN) varies 1:1 with V

, V

CMR

max varies 1:1 with V

7. Parameter guaranteed by design and evaluation but not tested in production.

NB4N11M

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Table 5. AC CHARACTERISTICS

= 3.0 V to 3.6 V, V

= 0 V; (Note 8)

Symbol

Characteristic

-40°C

25°C

85°C

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

OUTPP

Output Voltage Amplitude (R

= 50 W)

1 GHz

(See Figure 12)

1.5 GHz

2.5GHz

550

400

150

660

640

400

550

400

150

660

640

400

550

400

150

660

640

400

OUTPP

Output Voltage Amplitude (R

= 25 W)

1 GHz

(See Figure 12)

1.5 GHz

2.5GHz

280

100

370

360

300

280

100

370

360

400

280

100

370

360

400

DATA

Maximum Operating Data Rate

1.5

2.5

1.5

2.5

1.5

2.5

Gb/s

PLH

PHL

Propagation Delay to Output Differential

@ 0.5 GHz

300

420

600

300

420

600

300

420

600

SKEW

Duty Cycle Skew (Note 9)

Within Device Skew

Device to Device Skew (Note 13)

100

JITTER

RMS Random Clock Jitter R

= 50 W and

= 25 W (Note 11)

= 750 MHz

= 1.5 GHz

= 2.5 GHz

Peak-to-Peak Data Dependent Jitter R

= 50 W

DATA

= 1.5 Gb/s

(Note 12)

DATA

= 2.5 Gb/s

Peak-to-Peak Data Dependent Jitter R

= 25 W

DATA

= 1.5 Gb/s

(Note 12)

DATA

= 2.5 Gb/s

INPP

Input Voltage Swing/Sensitivity

(Differential Configuration) (Note 10)

100

Output Rise/Fall Times @ 0.5 GHz

Q, Q

(20% - 80%)

150

300

150

300

150

300

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

8. Measured by forcing V

INPP

(MIN) from a 50% duty cycle clock source. All output loaded with an external R

= 50 W and R

= 25 W to V

Outputs must be connected through R

to V

at power up. Input edge rates 150 ps (20% - 80%).

9. Duty cycle skew is measured between differential outputs using the deviations of the sum of T

pw-

and T

pw+

@ 0.5 GHz.

10.V

INPP

(MAX) cannot exceed V

- V

. Input voltage swing is a single-ended measurement operating in differential mode.

11. Additive RMS jitter with 50% duty cycle clock signal.

12.Additive peak-to-peak data dependent jitter with input NRZ data signal (PRBS 2

-1).

13.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.

Figure 3. Output Voltage Amplitude (V

OUTPP

) versus Input Clock Frequency (f

) at Ambient Temperature (Typical)

100

200

300

400

500

600

700

800

0.75 1

1.25 1.5 1.75 2

2.25 2.5 2.75 3

= 50 W

= 25 W

INPUT CLOCK FREQUENCY (GHz)

OUTPUT

VOL

T
AGE AMPLITUDE (mV)

- V

= 3.3 V V

= 3.3 V @ 255C V

= 100 mV)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.75 1

1.25 1.5 1.75 2

2.25 2.5 2.75 3

INPUT CLOCK FREQUENCY (GHz)

OUTPUT

VOL

T
AGE AMPLITUDE (mV)

- V

= 3.0 V V

= 1.71 V @255C V

= 100 mV)

= 50 W

= 25 W

NB4N11M

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NB4N11M

0.5 0.75 1

1.25 1.5 1.75 2

2.25 2.5 2.75 3

-40°C

25°C

85°C

INPUT CLOCK FREQUENCY (GHz)

TIME (ps)

Figure 4. Data Dependent Jitter vs. Frequency

and Temperature (V

- V

= 3.3 V; V

= 3.3 V

@ 255C; V

= 100 mV; PRBS 2

-1; R

= 50 W)

0.5 0.75 1

1.25 1.5 1.75 2

2.25 2.5 2.75 3

25°C

-40°C

85°C

INPUT CLOCK FREQUENCY (GHz)

TIME (ps)

Figure 5. Data Dependent Jitter vs. Frequency

and Temperature (V

- V

= 3.3 V; V

= 3.3 V

@ 255C; V

= 100 mV; PRBS 2

-1; R

= 25 W)

300

350

400

450

500

550

600

-40

Figure 6. Typical Propagation Delay vs.

Temperature (V

- V

= 3.3 V; V

= 3.3 V

@ 255C; V

= 100 mV; R

= 50 W)

TEMPERATURE (°C)

TIME (ps)

Figure 7. Typical Propagation Delay vs. Input

Offset Voltage (V

- V

= 3.3 V; V

= 3.3 V

@ 255C; V

= 100 mV R

= 50 W)

300

350

400

450

500

550

600

INPUT OFFSET VOLTAGE (V)

TIME (ps)

- 0.5 V

+ 0.5 V

* V

Figure 8. Supply Current vs. Temperature

-40

TEMPERATURE (°C)

CURRENT (mA)

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Figure 9. Typical Differential Output Waveform at 750 Mb/s

= 50 W Left Plot, R

= 25 W Right Plot, V

= 100 mV, System DDJ = 24 ps)

Figure 10. Typical Differential Output Waveform 1.5 Gb/s

= 50 W Left Plot, R

= 25 W Right Plot, V

= 100 mV, System DDJ = 25 ps)

DDJ = 5 ps

TIME (266.8 ps/div)

VOL

T
AGE (200 mV/div)

TIME (133.2 ps/div)

VOL

T
AGE (200 mV/div)

TIME (266.8 ps/div)

VOL

T
AGE (100 mV/div)

TIME (133.2 ps/div)

VOL

T
AGE (100 mV/div)

DDJ = 3 ps

DDJ = 5 ps

DDJ = 12 ps

Figure 11. Typical Differential Output Waveform 2.5 Gb/s

= 50 W Left Plot, R

= 25 W Right Plot, V

= 100 mV, System DDJ = 24 ps)

TIME (80 ps/div)

VOL

T
AGE (200 mV/div)

TIME (80 ps/div)

VOL

T
AGE (100 mV/div)

DDJ = 20 ps

DDJ = 7 ps

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Figure 12. AC Reference Measurement

PHL

PLH

INPP

= V

(D) - V

(D)

OUTPP

= V

(Q) - V

(Q)

Driver

Device

Receiver

Device

Figure 13. Typical Termination for Output Driver and Device Evaluation

50 W

Z = 50 W

DUT

Figure 14. Differential Input Driven

Single-Ended

Figure 15. Differential Inputs Driven

Differentially

Figure 16. V

Diagram

Figure 17. V

CMR

Diagram

GND

IHmin

IHmax

thmax

thmin

CMmax

CMR

GND

ILmax

ILmin

ILCLKmax

IHCLKmax

= V

IHD

- V

ILD

ILDtyp

IHDtyp

ILDmin

IHDmin

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Figure 19. Typical Examples of the Application Interface

Receiver

CCB

= 1.8 V 2.5 V or 3.3 V

CCA

= 1.8 V 2.5 V or 3.3 V

= 3.3 V

= 0 V

50 W

TTB

= V

CCB

TTB

= V

CCB

TTA

= V

CCA

Z = 50 W

NB4N11M

Receiver

CCD

= 1.8 V 2.5 V or 3.3 V

CCC

= 1.8 V 2.5 V or 3.3 V

= 3.3 V

= 0 V

100 W

75 W

TTD

= V

CCD

TTC

= V

CCC

Z = 75 W

Z = 100 W

NB4N11M

ORDERING INFORMATION

Device

Package

Shipping

NB4N11MDTG

TSSOP-8

(Pb-Free)

100 Units / Rail

NB4N11MDTR2G

TSSOP-8

(Pb-Free)

2500 / Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

NB4N11M

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PACKAGE DIMENSIONS

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

2.90

3.10

0.114

0.122

2.90

3.10

0.114

0.122

0.80

1.10

0.031

0.043

0.05

0.15

0.002

0.006

0.40

0.70

0.016

0.028

0.65 BSC

0.026 BSC

4.90 BSC

0.193 BSC

SEATING

PLANE

PIN 1

DETAIL E

L/2

-U-

0.15 (0.006) T

0.10 (0.004)

-T-

-V-

-W-

0.25 (0.010)

8x REF

IDENT

0.25

0.40

0.010

0.016

TSSOP-8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R-02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800-282-9855 Toll Free

USA/Canada

Japan: ON Semiconductor, Japan Customer Focus Center

2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051

Phone: 81-3-5773-3850

NB4N11M/D

ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).

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For additional information, please contact your

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