Semiconductor Components Industries, LLC, 2004

April, 2004 - Rev. 2

Publication Order Number:

NB6L11/D

NB6L11

2.5V/3.3V Multilevel Input to

Differential LVPECL/LVNECL

1:2 Clock or Data

Fanout Buffer/Translator

The NB6L11 is an enhanced differential 1:2 clock or data fanout

buffer/translator. The device has the same pinout and is functionally
equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW
jitter and LOW power consumption.

Differential input can be configured to accept single-ended signal

by applying an external reference voltage to unused complimentary
input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS,
CML, or LVDS. The outputs are 800 mV ECL signals.

Maximum Input Clock Frequency

w 6 GHz Typical

Maximum Input Data Rate

w 6 Gb/s Typical

Low 14 mA Typical Power Supply Current

150 ps Typical Propagation Delay

5 ps Typical Within Device Skew

75 ps Typical Rise/Fall Times

PECL Mode Operating Range: V

= 2.375 V to 3.465 V

with V

= 0 V

NECL Mode Operating Range: V

= 0 V

with V

= -2.375 V to -3.465 V

Open Input Default State

Q Outputs Will Default LOW with Inputs Open or at V

LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input

Compatible

A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week

*For additional marking information, refer to

Application Note AND8002/D.

SO-8

D SUFFIX

CASE 751

MARKING DIAGRAMS*

TSSOP-8

DT SUFFIX

CASE 948R

Device

Package

Shipping

ORDERING INFORMATION

NB6L11D

SO-8

98 Units/Rail

NB6L11DR2

SO-8

2500/

Tape & Reel

NB6L11DT**

TSSOP-8

100 Units/Rail

NB6L11DTR2**

TSSOP-8

2500/

Tape & Reel

ALYW

6L11

ALYW

6L11

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For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

**Future Product - Contact factory for availability.

NB6L11

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Figure 1. Pinout (Top View) and Logic Diagram

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Default State

Description

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁ

ECL Output

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Non-inverted differential clock/data output 0. Typically
terminated with 50

Resistor to V

= V

- 2 V.

ECL Output

Inverted differential clock/data output 0. Typically termi-
nated with 50

resistor to V

= V

- 2 V.

ECL Output

Non-inverted differential clock/data output 1. Typically
terminated with 50

resistor to V

= V

- 2 V.

ECL Output

Inverted differential clock/data output 1. Typically termi-
nated with 50

resistor to V

= V

- 2 V.

Negative power supply voltage

LVDS, CML, LVPECL,

LVNECL, LVCMOS,

LVTTL Input

HIGH

Inverted differential clock/data input. Internal 37.5 k

and 75 k

to V

LVDS, CML, LVPECL,

LVNECL, LVCMOS,

LVTTL Input

LOW

Non-inverted differential clock/data input. Internal
75 k

to V

and 37.5 k

to V

Positive power supply voltage

Table 2. ATTRIBUTES

Characteristics

Value

Internal Input Default State Resistor

)

37.5 k

Internal Input Default State Resistor

)

75 k

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 100 V

> 1 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

Transistor Count

167

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

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Table 3. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

Positive Power Supply

= 0 V

3.6

Negative Power Supply

= 0 V

-3.6

Positive Input Voltage

Negative Input Voltage

= 0 V

3.6

-3.6

INPP

Differential Input Voltage

|D - D|

- V

2.8 V

- V

2.8 V

2.8

- V

out

Output Current

Continuous

Surge

Operating Temperature Range

-40 to +85

stg

Storage Temperature Range

-65 to +150

Thermal Resistance (Junction-to-Ambient)

0 lfpm

500 lfpm

SOIC-8

190

130

C/W

Thermal Resistance (Junction-to-Case)

Standard Board

SOIC-8

41 to 44

C/W

Thermal Resistance (Junction-to-Ambient)

0 lfpm

500 lfpm

TSSOP-8

185

140

C/W

Thermal Resistance (Junction-to-Case)

Standard Board

TSSOP-8

41 to 44

C/W

sol

Wave Solder

< 2 to 3 sec @ 248

265

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not im-
plied, damage may occur and reliability may be affected.

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Table 4. DC CHARACTERISTICS, PECL

= 2.5 V, V

= 0 V (Note 4)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current (Note 5)

Output HIGH Voltage (Note 6)

1350

1450

1550

1400

1500

1600

1450

1550

1650

Output LOW Voltage (Note 6)

630

750

870

680

800

920

730

850

970

DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 10, 12)

Input Threshold Reference Voltage Range
(Note 2)

1125

-75

1125

-75

1125

-75

Single-Ended Input HIGH Voltage

+75

Single-Ended Input LOW Voltage

-75

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)

IHD

Differential Input HIGH Voltage

1200

ILD

Differential Input LOW Voltage

-75

CMR

Input Common Mode Range
(Differential Cross-Point Voltage) (Note 3)

1163

-38

1163

-38

1163

-38

Differential Input Voltage (V

IHD

- V

ILD

)

2500

Input HIGH Current

D
D

50
10

150
150

50
10

150
150

50
10

150
150

Input LOW Current

D
D

-150
-150

-5

-30

-150
-150

-5

-30

-150
-150

-5

-30

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.

2. V

is applied to the complementary input when operating in single-ended mode.

3. V

CMR

minimum varies 1:1 with V

, V

CMR

maximum varies 1:1 with V

4. Input and output parameters vary 1:1 with V

. V

can vary +0.125 V to -1.3 V.

5. All input and output pins left open.
6. All loading with 50

to V

- 2.0 V.

NB6L11

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Table 5. DC CHARACTERISTICS, PECL

= 3.3 V, V

= 0 V (Note 9)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current (Note 10)

Output HIGH Voltage (Note 11)

2150

2250

2350

2200

2300

2400

2250

2350

2450

Output LOW Voltage (Note 11)

1430

1550

1670

1480

1600

1720

1530

1650

1770

DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 10, 12)

Input Threshold Reference Voltage Range
(Note 7)

1125

-75

1125

-75

1125

-75

Single-Ended Input HIGH Voltage

+75

Single-Ended Input LOW Voltage

-75

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)

IHD

Differential Input HIGH Voltage

1200

ILD

Differential Input LOW Voltage

-75

CMR

Input Common Mode Range
(Differential Cross-Point Voltage) (Note 8)

1163

-38

1163

-38

1163

-38

Differential Input Voltage (V

IHD

- V

ILD

)

2500

Input HIGH Current

D
D

50
10

150
150

50
10

150
150

50
10

150
150

Input LOW Current

D
D

-150
-150

-5

-30

-150
-150

-5

-30

-150
-150

-5

-30

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

7. V

is applied to the complementary input when operating in single-ended mode.

8. V

CMR

minimum varies 1:1 with V

, V

CMR

maximum varies 1:1 with V

9. Input and output parameters vary 1:1 with V

. V

can vary +0.3 V to -2.2 V.

10. All input and output pins left open.
11. All loading with 50

to V

- 2.0 V.

NB6L11

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Table 6. DC CHARACTERISTICS, NECL

= 0 V; V

= -3.465 V to -2.375 V (Note 14)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Negative Power Supply Current
(Note 15)

Output HIGH Voltage (Note 16)

-1150

-1050

-950

-1100

-1000

-900

-1050

-950

-850

Output LOW Voltage (Note 16)

-1870

-1750

-1630

-1820

-1700

-1580

-1770

-1650

-1530

DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 10, 12)

Input Threshold Reference Voltage
Range (Note 12)

+1125

-75

+1125

-75

+1125

-75

Single-Ended Input HIGH Voltage

+75

Single-Ended Input LOW Voltage

-75

DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)

IHD

Differential Input HIGH Voltage

+1200

ILD

Differential Input LOW Voltage

-75

CMR

Input Common Mode Range
(Differential Cross-Point Voltage)
(Note 13)

+1163

-38

+1163

-38

+1163

-38

Differential Input Voltage (V

IHD

ILD

)

2500

Input HIGH Current

D
D

50
10

150
150

50
10

150
150

50
10

150
150

Input LOW Current

D
D

-150
-150

-5

-30

-150
-150

-5

-30

-150
-150

-5

-30

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

12. V

is applied to the complementary input when operating in single-ended mode.

13. V

CMR

minimum varies 1:1 with V

, V

CMR

maximum varies 1:1 with V

14. Input and output parameters vary 1:1 with V

15. Input and output pins left open.
16. All loading with 50

to V

- 2.0 V.

NB6L11

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Table 7. AC CHARACTERISTICS

= 0 V; V

= -3.465 V to -2.375 V or V

= 2.375 V to 3.465 V; V

= 0 V (Note 17)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

OUTPP

Output Voltage Amplitude

3 GHz

(See Figures 2 & 3

)

6 GHz

480
270

700
300

480
270

700
300

480
270

700
300

PLH

PHL

Propagation Delay to
Output Differential @ 1 GHz

D to Q, Q

110

150

190

110

150

200

120

160

220

SKEW

Duty Cycle Skew
Within Device Skew

(Note 18)

Device-to-Device Skew

2
5

10
15
60

2
5

10
15
60

2
5

10
15
60

JITTER

RMS Random Clock Jitter
(Note 19)

6 GHz

Peak-to-Peak Data Dependent Jitter
(Note 20)

6 Gb/s

0.2

INPP

Input Voltage Swing / Sensitivity
(Differential Configuration) (Note 21)

700

2500

700

2500

700

2500

Output Rise/Fall Times @ 1 GHz

Q, Q

(20% - 80%)

120

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

17. Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50

to V

- 2.0 V. Input edge rates 40 ps (20% - 80%).

18. See Figure 9 t

skew

= |t

PLH

- t

PHL

| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical

transitions and conditions @ 1 GHz.

19. Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
20. Additive Peak-to-Peak data dependent jitter with NRZ PRBS 2

-1 data rate at 6 Gb/s.

21. V

INPP(max)

cannot exceed V

- V

(applicable only when V

- V

< 2500 mV). Input voltage swing is a single-ended measurement

operating in differential mode

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

OUTPUT

VOL

AGE

AMPLITUDE (V)

Figure 2. Output Voltage Amplitude (V

OUTPP

)

versus Input Clock Frequency (f

) and

Temperature at V

- V

= 3.3 V

INPUT CLOCK FREQUENCY (GHz)

-40

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

OUTPUT

VOL

AGE

AMPLITUDE (V)

-40

Figure 3. Output Voltage Amplitude (V

OUTPP

)

versus Input Clock Frequency (f

) and

Temperature at V

- V

= 2.5 V

INPUT CLOCK FREQUENCY (GHz)

NB6L11

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Figure 4. Typical Output Waveform at

2.488 Gb/s with PRBS 2

-1 (Total System

Pk-Pk Jitter is 17 ps. Device Pk-Pk Jitter

Contribution is 4 ps)

TIME (64 ps/div)

OUTPUT VOL

AGE AMPLITUDE

(100 mV/div)

Figure 5. Typical Output Waveform at

6.125 Gb/s with PRBS 2

-1 (Total System

Pk-Pk Jitter is 20 ps. Device Pk-Pk Jitter

Contribution is 5 ps)

TIME (32 ps/div)

OUTPUT VOL

AGE AMPLITUDE

(100 mV/div)

NOTE:

- V

= 3.3 V; V

= 700 mV; T

= 25

110

130

150

170

190

210

2.375

2.5

3.3

3.465

-40

PROP

AGA

TION DELA

(ps)

Figure 6. Propagation Delay versus Power

Supply Voltage and Temperature

POWER SUPPLY VOLTAGE (V)

100

110

120

2.375

2.5

3.3

3.465

-40

Figure 7. Rise/Fall Time versus Power Supply

Voltage and Temperature

POWER SUPPLY VOLTAGE (V)

RISE/F

ALL

TIME

(ps)

-40

- V

= -3.465 V

- V

= -2.375 V

Figure 8. I

Current versus Temperature and

Power Supply Voltage

TEMPERATURE (

CURRENT (mA)

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Figure 9. AC Reference Measurement

PHL

PLH

INPP

(D) = V

(D) - V

(D)

INPP

(D) = V

(D) - V

(D)

OUTPP

(Q) = V

(Q) - V

(Q)

OUTPP

(Q) = V

(Q) - V

(Q)

Figure 10. Differential Input Driven

Single-Ended

Figure 11. Differential Inputs Driven

Differentially

IHmax

ILmax

IHmin

ILmin

thmax

thmin

GND

IHDmax

ILDmax

IHDmin

ILDmin

IHDtyp

ILDtyp

= V

IHD

- V

ILD

CMR

CMmax

GND

Figure 12. V

Diagram

Figure 13. V

CMR

Diagram

Figure 14. Typical Termination for Output Driver and Device Evaluation

(See Application Note AND8020/D - Termination of ECL Logic Devices.)

Driver
Device

Receiver
Device

= 50

= V

- 2.0 V

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PACKAGE DIMENSIONS

SOIC-8

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751-07

ISSUE AB

SEATING
PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751-01 THRU 751-06 ARE OBSOLETE. NEW

STANDARD IS 751-07.

0.10 (0.004)

DIM

MIN

MAX

MIN

MAX

INCHES

4.80

5.00

0.189

0.197

MILLIMETERS

3.80

4.00

0.150

0.157

1.35

1.75

0.053

0.069

0.33

0.51

0.013

0.020

1.27 BSC

0.050 BSC

0.10

0.25

0.004

0.010

0.19

0.25

0.007

0.010

0.40

1.27

0.016

0.050

0.25

0.50

0.010

0.020

5.80

6.20

0.228

0.244

-X-

-Y-

0.25 (0.010)

-Z-

0.25 (0.010)

SO-8

1.52

0.060

7.0

0.275

0.6

0.024

1.270
0.050

4.0

0.155

inches

SCALE 6:1

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PACKAGE DIMENSIONS

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

2.90

3.10

0.114

0.122

2.90

3.10

0.114

0.122

0.80

1.10

0.031

0.043

0.05

0.15

0.002

0.006

0.40

0.70

0.016

0.028

0.65 BSC

0.026 BSC

4.90 BSC

0.193 BSC

SEATING

PLANE

PIN 1

DETAIL E

L/2

-U-

0.15 (0.006) T

0.10 (0.004)

-T-

-V-

-W-

0.25 (0.010)

8x REF

IDENT

0.25

0.40

0.010

0.016

TSSOP-8

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948R-02

ISSUE A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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NB6L11/D

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