Semiconductor Components Industries, LLC, 2005
May, 2005 - Rev. 0
1
Publication Order Number:
NB7L111M/D
NB7L111M
2.5V / 3.3V, 6.125Gb/s 1:10
Differential Clock/Data
Driver with CML Output
Description
The NB7L111M is a low skew 1to10 differential clock/data
driver, designed with clock/data distribution in mind. It accepts two
clock/data sources into multiplexer input and reproduces ten identical
CML differential outputs. This device is ideal for clock/data
distribution across the backplane or a board, and redundant clock
switchover applications.
The input signals can be either differential or singleended (if the
external reference voltage is provided). Differential inputs incorporate
internal 50
W termination resistors and accept Negative ECL (NECL),
Positive ECL (PECL), LVCMOS, LVTTL, CML, or LVDS (using
appropriate power supplies). The differential 16 mA CML output
provides matching internal 50
W termination, and 400 mV output
swing when externally terminated 50
W to V
CC.
The NB7L111M operates from a 2.5 V
$5% supply or a
3.3 V
$5% supply and is guaranteed over the full industrial
temperature range of -40
C to +85C. This device is packaged in a
low profile 8x8 mm, QFN-52 package with 0.5 mm pitch (see
package dimension on the back of the datasheet).
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
Maximum Input Clock Frequency > 5.5 GHz Typical
Maximum Input Data Rate > 6.125 Gb/s Typical
< 0.5 ps Maximum Clock RMS Jitter
< 15 ps Maximum Data Dependent Jitter at 3.125 Gb/s
50 ps Typical Rise and Fall Times
240 ps Typical Propagation Delay
2 ps Typical Duty Cycle Skew
10 ps Typical Within Device Skew
15 ps Typical Device-to-Device Skew
Operating Range: V
CC
= 2.5 V
$5 and 3.3 V $5
400 mV Differential CML Output Swing
50
W Internal Input and Output Termination Resistors
Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
NB7L111M = Device Code
A
= Assembly Site
WL
= Wafer Lot
YY
= Year
WW
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
QFN-52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
NB7L
111M
AWLYYWW
http://onsemi.com
1
52
1
52
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
ORDERING INFORMATION
NB7L111M
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2
NC
Q0
Q0
V
EE
Q1
Q1
V
EE
V
CC
Q2
V
EE
V
CC
Q3
Q2
NC
V
EE
VTCLK0
SEL
Q4
V
EE
V
CC
NC
Q8
Q7
V
EE
Q7
Q9
1
2
3
4
5
6
7
8
9
10
11
12
13
CLK0
CLK0
VTCLK0
VTSEL
SEL
VTSEL
VTCLK1
CLK1
CLK1
VTCLK1
14
15
16
17
18
19
20
21
22
23
24
25
26
V
CC
Q9
V
EE
Q8
V
CC
NC
V
EE
39
38
37
36
35
34
33
32
31
30
29
28
27
Q4
V
EE
Q3
52
51
50
49
48
47
46
45
44
43
42
41
40
V
CC
Exposed Pad (EP)
QFN52
Q5
Q5
V
EE
Q6
Q6
Figure 1. Pinout (Top View)
CLK0
CLK0
CLK1
CLK1
SEL
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
Q
8
Q
9
Q
9
VTCLK0
VTCLK1
VTCLK1
VTSEL
Figure 2. Logic Diagram
50 W
R
2
R
3
50 W
VTCLK0
50 W
50 W
50 W
50 W
SEL
VTSEL
R
1
V
CC
V
EE
0
1
Table 1. FUNCTION TABLE
SEL
SEL
CLK0/CLK0
CLK1/CLK1
LOW
HIGH
ON
OFF
HIGH
LOW
OFF
ON
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Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
15, 24, 27, 39, 42, 51
V
CC
-
Positive supply voltage. All V
CC
pins must be externally connected to
power supply to guarantee proper operation.
1, 18, 21, 26, 30, 33,
36, 40, 45, 48
V
EE
-
Negative supply voltage. All V
EE
pins must be externally connected to
power supply to guarantee proper operation.
2
VTCLK0
-
Internal 50 W termination pin for CLK0. (Note 2)
3
CLK0
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Non-inverted differential clock/data input 0 (Note 2).
4
CLK0
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data input 0 (Note 2).
5
VTCLK0
-
Internal 50 W termination pin for CLK0. (Note 2)
6
VTSEL
Internal 50 W termination pin for SEL. (Note 2)
7
SEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Non-inverted differential clock/data select input. Internal 75 kW to V
EE
.
8
SEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data select input. Internal 56 KW to V
CC
and
56 kW to V
EE
bias this pin to (V
CC
-V
EE
)/2.
9
VTSEL
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Internal 50 W termination pin for SEL. (Note 2)
10
VTCLK1
-
Internal 50 W termination pin for CLK1. (Note 2)
11
CLK1
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Non-inverted differential clock/data input 1 (Note 2).
12
CLK1
LVPECL, CML,
LVCMOS, LVTTL,
LVDS Input
Inverted differential clock/data input 1 (Note 2).
13
VTCLK1
-
Internal 50 W termination pin for CLK1. (Note 2)
14, 25, 41, 52
NC
-
17, 20, 23, 29, 32, 35,
38, 44, 47, 50
Q[0-9]
CML Outputs
Non-inverted CML outputs [0-9] with internal 50 W source termination
resistor (Note 1).
16, 19, 22, 28, 31, 34,
37, 43, 46, 49
Q[0-9]
CML Outputs
Inverted CML outputs [0-9] with internal 50 W source termination
resistor (Note 1).
EP
-
-
Exposed Pad (EP). The thermally exposed pad on package bottom (see
case drawing) must be attached to a heat-sinking conduit on the printed
circuit board.
1. CML output requires 50 W receiver termination resistor to V
CC
for proper operation.
2. In the differential configuration when the input termination pin (VTCLK, VTCLK) are connected to a common termination voltage or left open,
and if no signal is applied on CLK and CLK then the device will be susceptible to self-oscillation.
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4
Table 3. ATTRIBUTES
Characteristics
Value
Input Default State Resistors
R1, R3
R2
56 kW
75 kW
ESD Protection
Human Body Model
Machine Model
> 1400 V
> 80 V
Moisture Sensitivity (Note 3)
QFN52
Level 2
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
339
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
(Note 4)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
CC
Positive Power Supply
V
EE
= 0 V
3.6
V
V
I
Input Voltage
V
EE
= 0 V
V
EE
v V
I
v V
CC
3.6
V
V
INPP
Differential Input Voltage |CLK - CLK|
V
CC
- V
EE
2.8 V
V
CC
- V
EE
< 2.8 V
2.8
|V
CC
- V
EE
|
V
V
I
in
Input Current Through R
T
(50 W Resistor)
Continuous
Surge
25
50
mA
mA
I
out
Output Current
Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range
QFN52
-40 to +85
_C
T
stg
Storage Temperature Range
-65 to +150
_C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 5)
0 lfpm
500 lfpm
QFN52
25
19.6
_C/W
_C/W
q
JC
Thermal Resistance (Junction-to-Case)
1S2P (Note 8)
QFN52
21
_C/W
T
sol
Wave Solder
Pb
Pb-Free
< 3 Sec @ 248_C
< 3 Sec @ 260_C
265
265
_C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
4. Maximum Ratings are those values beyond which device damage may occur.
5. JEDEC standard multilayer board - 1S2P (1 signal, 2 power).
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Table 5. DC CHARACTERISTICS
V
CC
= 2.375 V 2.625 V and 3.135 V to 3.465 V, V
EE
= 0 V, T
A
= -40C to +85C (Notes 6 and 7)
Symbol
Characteristic
Min
Typ
Max
Unit
I
CC
Power Supply Current (Inputs and Outputs Open)
V
CC
= 2.375 V to 2.625 V
V
CC
= 3.135 V to 3.465 V
255
270
290
305
325
340
mA
V
OH
Output HIGH Voltage (Notes 6 and 7)
V
CC
- 40
V
CC
- 20
V
CC
mV
V
OL
Output LOW Voltage (Notes 6 and 7)
V
CC
= 2.375 V to 2.625 V
V
CC
= 3.135 V to 3.465 V
V
CC
- 440
V
CC
- 490
V
CC
- 350
V
CC
- 400
V
CC
290
V
CC
- 340
mV
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (See Figures 13 and 15)
V
th
Input Threshold Reference Voltage Range (Note 8)
1125
V
CC
75
mV
V
IH
Single-ended Input HIGH Voltage (Note 7)
V
th
+ 75
V
CC
mV
V
IL
Single-ended Input LOW Voltage (Note 7)
V
EE
V
CC
150
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (See Figures 14 and 16)
V
IHD
Differential Input HIGH Voltage
1200
V
CC
mV
V
ILD
Differential Input LOW Voltage
V
EE
V
CC
75
mV
V
CMR
Input Common Mode Range (Differential Configuration) (Note 9)
1163
V
CC
37
mV
V
ID
Differential Input Voltage (V
IHD
- V
ILD
)
75
2500
mV
I
IH
Input HIGH Current
CLK[0-1]/CLK[0-1]
(Termination Pins Open)
SEL/SEL
-100
-150
5
100
150
mA
I
IL
Input LOW Current
CLK[0-1]/CLK[0-1]
(Termination Pins Open)
SEL/SEL
-100
-150
5
100
150
mA
R
TIN
Internal Input Termination Resistor
45
50
55
W
R
TOUT
Internal Output Termination Resistor
45
50
55
W
R
Temp
Coef
Internal I/O Termination Resistor Temperature Coefficient
-3.75
mW/C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. CML outputs require 50 W receiver termination resistors to V
CC
for proper operation.
7. Input and output parameters vary 1:1 with V
CC
.
8. V
th
is applied to the complementary input when operating in single-ended mode.
9. V
CMR
(MIN) varies 1:1 with V
EE
, V
CMR
(MAX) varies 1:1 with V
CC
.
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Table 6. AC CHARACTERISTICS
V
CC
= 2.375 V to 2.625 V and 3.135 V to 3.465 V, V
EE
= 0 V; (Note 10)
-40_C
25_C
85_C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
OUTPP
Output Voltage Amplitude (@ V
inppmin
)
(See Figures 3, 4, 5, and 6)
V
CC
= 2.375 V to 2.625 V
f
in
3 GHz
f
in
5.5 GHz
V
CC
= 3.135 V to 3.465 V
f
in
3 GHz
f
in
5.5 GHz
240
115
250
130
330
220
350
250
240
115
250
130
330
220
350
250
240
115
250
130
330
220
350
250
mV
f
DATA
Maximum Operating Data Rate
5
6
5
6
5
6
Gb/s
t
PLH
,
t
PHL
Differential Input-to-Output Propagation Delay
@ 1 GHz (See Figures 7 and 11)
CLK-Q
SEL-Q
200
290
240
340
280
390
200
290
240
340
280
390
200
290
240
340
280
390
ps
t
SKEW
Duty Cycle Skew (Note 11)
Within Device Skew
Device-to-Device Skew (Note 15)
2
10
15
15
20
80
2
10
15
15
20
80
2
10
15
15
20
80
ps
t
JITTER
RMS Random Clock Jitter (Note 13)
f
in
= 3 GHz
f
in
= 5.5 GHz
Peak-to-Peak Data Dependent Jitter
(Note 14)
f
DATA
= 3.125 Gb/s
f
DATA
= 5 Gb/s
f
DATA
= 6.125 Gb/s
0.2
0.2
6
15
15
0.5
0.5
15
25
25
0.2
0.2
6
15
15
0.5
0.5
15
25
25
0.2
0.2
6
15
15
0.5
0.5
15
25
25
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration)
(Note 12 and Figures 3, 4, 5, and 6)
75
400
2500
75
400
2500
75
400
2500
mV
t
r
t
f
Output Rise/Fall Times @ 1 GHz
(20% - 80%)
50
75
50
75
50
75
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All loading with an external R
L
= 50 W to V
CC
. Input edge rates 40 ps
(20% - 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 1 GHz.
12.V
INPP
(MAX) cannot exceed V
CC
- V
EE
. Input voltage swing is a single-ended measurement operating in differential mode.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 2
23
-1.
15.Device-to-device skew is measured between outputs under identical transition and conditions @ 1 GHz.
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0
50
100
150
200
250
300
350
400
1
2
3
3.5 4
4.5 5
5.5 6
6.5
O
UTPUT V
O
LTA
G
E AMPLITUDE
(
mV
)
INPUT CLOCK FREQUENCY (GHz)
25
85
-40
Figure 3. Output Voltage Amplitude vs. Input
Clock Frequency and Temperature
(V
inpp
= 400 mV; V
CC
= 3.3 V)
0
50
100
150
200
250
300
350
400
1
2
3
3.5
4
4.5
5
5.5
6 6.5
OUTPUT VOL
T
AGE
AMPLITUDE
(mV)
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude vs. Input
Clock Frequency and Temperature
(V
inpp
= 75 mV; V
CC
= 3.3 V)
25
85
-40
0
50
100
150
200
250
300
350
400
1
2
3
3.5
4
4.5
5
5.5
6
6.5
0
50
100
150
200
250
300
350
400
1
2
3
3.5
4
4.5
5
5.5
6
6.5
INPUT CLOCK FREQUENCY (GHz)
OUTPUT VOL
T
AGE
AMPLITUDE
(mV)
-40
85
25
OUTPUT VOL
T
AGE
AMPLITUDE
(mV)
INPUT CLOCK FREQUENCY (GHz)
25
85
-40
Figure 5. Output Voltage Amplitude vs. Input
Clock Frequency and Temperature
(V
inpp
= 400 mV; V
CC
= 2.5 V)
Figure 6. Output Voltage Amplitude vs. Input
Clock Frequency and Temperature
(V
inpp
= 75 mV; V
CC
= 2.5 V)
Figure 7. Propagation Delay versus Temperature
-40
25
85
200
210
220
230
240
250
260
270
280
Temperature (C)
PROP
AGA
TION DELA
Y
(ps)
Typical Tpd
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Figure 8. Typical Output Waveform at 3.125 Gb/s with PRBS 2
23
-1 (V
inpp
= 75 mV-left and 400 mV-right)
Device DDJ = 6 ps
Device DDJ = 7 ps
VOL
T
AGE (50 mV/div)
TIME (22.1 ps/div)
VOL
T
AGE (50 mV/div)
TIME (22.1 ps/div)
Figure 9. Typical Output Waveform at 5 Gb/s with PRBS 2
23
-1 (V
inpp
=75 mV-left and 400 mV-right)
Device DDJ=16ps
Device DDJ=17ps
VOL
T
AGE (40 mv/ div)
TIME (22.1 ps/div)
VOL
T
AGE (40 mv/ div)
TIME (22.1 ps/div)
Figure 10. Typical Output Waveform at 6.125 Gb/s with PRBS 2
23
-1 (V
inpp
= 75 mV-left and 400 mV-right)
Device DDJ=12ps
Device DDJ=15ps
VOL
T
AGE (35 mv/div)
TIME (22.1 ps/div)
VOL
T
AGE (35 mv/div)
TIME (22.1 ps/div)
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9
Figure 11. AC Reference Measurement
CLK
CLK
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(CLK) - V
IL
(CLK)
V
OUTPP
= V
OH
(Q) - V
OL
(Q)
W
Receiver
Device
Q
CLK
50
W
50
Figure 12. Typical Termination for 16 mA Output Drive and Device Evaluation
Q
CLK
V
CC
W
50
W
50
V
CC
NB7L111M
CLK
V
th
CLK
V
th
Figure 13. Differential Input Driven
Single-Ended
CLK
CLK
Figure 14. Differential Inputs Driven
Differentially
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
GND
V
th
V
IHDmax
V
ILDmax
V
IHDmin
V
ILDmin
V
IHDtyp
V
ILDtyp
V
ID
= V
IHD
- V
ILD
V
CMR
V
CC
V
CMmax
V
CMmax
GND
Figure 15. V
th
Diagram
Figure 16. V
CMR
Diagram
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10
Q
Q
V
CC
16 mA
50 W
50 W
Figure 17. CML Output Structure
V
EE
Table 7. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK0, VTCLK0, VTCLK1, VTCLK1, VTSEL, VTSEL to V
CC
LVDS
Connect VTCLK0, VTCLK0 together for CLK0 input; Connect VTCLK1, VTCLK1 together for CLK1 input;
Connect VTSEL, VTSEL together for SEL control input.
AC-COUPLED
Bias VTCLK0, VTCLK0, VTSEL, VTSEL and VTCLK1, VTCLK1 inputs within (VCMR) Common Mode
Range.
RSECL, LVPECL
Standard ECL termination techniques. See AND8020.
LVTTL, LVCMOS
An external voltage should be applied to the unused complementary differential input. Nominal voltage 1.5 V
for LVTTL and V
CC
/2 for LVCMOS inputs.
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Application Information
All NB7L111M inputs can accept PECL, CML, LVTTL,
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
minimum input swing of 100 mV and the maximum input
swing of 450 mV. Within these conditions, the input voltage
can range from V
CC
to 1.2 V. Examples interfaces are
illustrated below in a 50
W environment (Z = 50 W).
50 W
V
CC
CLK
CLK
50 W
CML
or
NB7L111M
V
CC
V
TCLK
V
EE
V
CC
Q
50 W 50 W
CML
or
NB7L111M
V
EE
Figure 18. CML to CML Interface
Z
Q
Z
50 W
Z
Z
V
CC
V
CC
LVDS
Driver
50 W
NB7L111M
V
EE
V
EE
Figure 19. PECL to CML Receiver Interface
50 W
Z
Z
V
CC
V
CC
PECL
Driver
CLK
CLK
50 W
NB7L111M
V
EE
V
BIAS
*
V
TCLK
V
EE
R
T
R
T
V
EE
V
CC
R
T
5.0 V 290 W
3.3 V 150 W
2.5 V 80 W
Recommended R
T
Values
50 W
50 W
V
CC
V
TCLK
V
BIAS
*
V
TCLK
CLK
CLK
V
TCLK
V
TCLK
Figure 20. LVDS to CML Receiver Interface
*V
BIAS
is within V
CMR
Range.
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Figure 21. LVCMOS/LVTTL to CML Receiver Interface
50 W
Z
V
CC
V
CC
LVTTL/
LVCMOS
Driver
CLK
CLK
50 W
NB7L111M
V
EE
No Connect
V
TCLK
V
CC
V
TCLK
No Connect
V
REF
V
REF
LVCMOS
LVTTL
1.5 V
Recommended V
REF
Values
VCC * VEE
2
ORDERING INFORMATION
Device
Package
Shipping
NB7L111MMN
QFN-52
46 Units / Rail
NB7L111MMNG
QFN-52
(Pb-Free)
46 Units / Rail
NB7L1MMNR2
QFN-52
2000 / Tape & Reel
NB7L1MMNR2G
QFN-52
(Pb-Free)
2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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13
PACKAGE DIMENSIONS
QFN-52, 8 x 8 mm, 0.5 mm Pitch
Quad Flat No Lead Package
CASE 485M-01
ISSUE O
C
0.15
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
A
D
E
B
C
0.08
A1
A3
A
D2
L
NOTE 3
C
0.15
2X
2X
SEATING PLANE
C
0.10
A2
C
E2
52 X
e
1
13
14
26
27
39
40
52
b
52 X
A
0.10
B
C
0.05 C
DIM
MIN
MAX
MILLIMETERS
A
0.80
1.00
A1
0.00
0.05
A2
0.60
0.80
A3
0.20 REF
b
0.23
0.28
D
8.00 BSC
D2
6.50
6.80
E
8.00 BSC
E2
6.50
6.80
e
0.50 BSC
K
0.20
---
REF
K
52 X
L
0.35
0.45
NB7L111M
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