Semiconductor Components Industries, LLC, 2005
November, 2005 - Rev. 0
1
Publication Order Number:
NB7L32M/D
NB7L32M
2.5V/3.3V, 14GHz 2 Clock
Divider w/CML Output and
Internal Termination
Descriptions
The NB7L32M is an integrated
2 divider with differential clock
inputs and asynchronous reset.
Differential clock inputs incorporate internal 50
W termination
resistors and accept LVPECL (Positive ECL), CML, or LVDS. The
high frequency reset pin is asserted on the rising edge. Upon
power-up, the internal flip-flops will attain a random state; the reset
allows for the synchronization of multiple NB7L32M's in a system.
The differential 16 mA CML output provides matching internal
50
W termination which guarantees 400 mV output swing when
externally receiver terminated 50
W to V
CC
(See Figure 16).
The device is housed in a small 3x3 mm 16 pin QFN package.
Features
Maximum Input Clock Frequency 14 GHz Typical
200 ps Max Propagation Delay
30 ps Typical Rise and Fall Times
< 0.5 ps Maximum (RMS) Random Clock Jitter
Operating Range: V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
CML Output Level (400 mV Peak-to-Peak Output), Differential
Output Only
50
W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
These are Pb-Free Devices
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
QFN-16
MN SUFFIX
CASE 485G
http://onsemi.com
16
NB7L
32M
ALYWG
1
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
VTCLK
CLK
CLK
VTCLK
50 W
50 W
Q
Q
Divide by 2
Reset
R
V
EE
R1
FUNCTIONAL BLOCK DIAGRAM
V
CC
CLK
TRUTH TABLE
x
x
H
Z
W
L
CLK
R
Q
Q
L
2
2
H
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don't Care
NB7L32M
http://onsemi.com
2
NC
V
EE
V
CC
R
V
CC
V
CC
V
CC
Q
Q
V
CC
VTCLK
CLK
CLK
VTCLK
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NB7L32M
Exposed Pad (EP)
V
EE
V
EE
Figure 1. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
VTCLK
-
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination volt-
age or left open, and if no signal is applied on CLK/CLK input then the device
will be susceptible to self-oscillation.
2
CLK
ECL, CML, LVDS Input
Noninverted differential input. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination volt-
age or left open and if no signal is applied on CLK/CLK input, then the device
will be susceptible to self-oscillation.
3
CLK
ECL, CML, LVDS Input
Inverted differential input. In the differential configuration when the input ter-
mination pin (VTCLK, VTCLK) are connected to a common termination voltage
or left open and if no signal is applied on CLK/CLK input, then the device will
be susceptible to self-oscillation.
4
VTCLK
-
Internal 50 W termination pin. In the differential configuration when the input
termination pin (VTCLK, VTCLK) are connected to a common termination volt-
age or left open and if no signal is applied on CLK/CLK input, then the device
will be susceptible to self-oscillation.
5
NC
-
No connect. NC pin must be left open.
6, 7, 8
V
EE
-
Negative supply voltage.
9, 12, 13,
14, 16
V
CC
-
Positive supply voltage.
10
Q
CML Output
Inverted differential output. Typically terminated with 50 W resistor to V
CC
.
11
Q
CML Output
Noninverted differential output. Typically terminated with 50 W resistor to V
CC
.
15
R
LVTTL/LVCMOS
Reset Input. Internal pulldown to 75 kW to V
EE
.
-
EP
-
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case
drawing) must be attached to a heat-sinking conduit. EP is electrically isolated
from V
CC
and V
EE
.
NB7L32M
http://onsemi.com
3
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
R1
75 kW
ESD Protection
Human Body Model
Machine Model
> 500 V
> 30 V
Moisture Sensitivity (Note 1)
QFN-16
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
349
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
CC
Positive Power Supply
V
EE
= 0 V
3.6
V
V
EE
Negative Power Supply
V
CC
= 0 V
-3.6
V
V
I
Positive Input
Negative Input
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
3.6
-3.6
V
V
V
INPP
Differential Input Voltage
2.8
V
I
IN
Input Current Through R
T
(50 W Resistor)
Static
Surge
45
80
mA
mA
I
out
Output Current
Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range
QFN-16
-40 to +85
C
T
stg
Storage Temperature Range
-65 to +150
C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 2)
0 lfpm
500 lfpm
QFN-16
QFN-16
41.6
35.2
C/W
C/W
q
JC
Thermal Resistance (Junction-to-Case)
1S2P
QFN-16
4.0
C/W
T
sol
Wave Solder
Pb-Free <3 sec @ 260C
265
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
2. JEDEC standard multilayer board - 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB7L32M
http://onsemi.com
4
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS
V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V,
T
A
= -40C to +85C
Symbol
Characteristic
Min
Typ
Max
Unit
I
CC
Power Supply Current (Note 3)
50
65
80
mA
V
OH
Output HIGH Voltage (Note 4)
V
CC
- 40
V
CC
- 10
V
CC
mV
V
OL
Output LOW Voltage (Note 4)
V
CC
- 500
V
CC
- 400
V
CC
- 330
mV
R
TOUT
Internal Output Termination Resistor
45
50
55
W
R
Temp
Coef
Internal I/O Termination Resistor Temperature Coefficient
6.38
mW/C
DIFFERENTIAL CLK/CLK INPUT DRIVEN SINGLE-ENDED (see Figure 10 and 12)
V
th
Input Threshold Reference Voltage Range (Note 6)
1050
V
CC
mV
V
IH
Single-ended Input HIGH Voltage
V
th
+ 150
V
CC
+ 300
mV
V
IL
Single-ended Input LOW Voltage
V
EE
V
th
- 150
mV
DIFFERENTIAL CLK/CLK INPUTS DRIVEN DIFFERENTIALLY (see Figure 11 and 13)
V
IHD
Differential Input HIGH Voltage
1200
V
CC
+ 300
mV
V
ILD
Differential Input LOW Voltage
V
EE
V
CC
- 75
mV
V
CMR
Input Common Mode Range (Differential Configuration, Note 7)
1125
V
CC
mV
V
ID
Differential Input Voltage (V
IHD
- V
ILD
)
150
2500
mV
I
IH
Input HIGH Current
CLK/CLK (VTCLK/R/VTCLK/R Open)
0
30
100
mA
I
IL
Input LOW Current
CLK/CLK(VTCLK/R/VTCLK/R Open)
-50
0
50
mA
R
TIN
Internal Input Termination Resistor
45
50
55
W
LVTTL/LVCMOS RESET INPUT
V
IH
Single-ended Input HIGH Voltage
2000
V
CC
mV
V
IL
Single-ended Input LOW Voltage
V
EE
800
mV
I
IH
Input HIGH Current
R
0
30
100
mA
I
IL
Input LOW Current
R
0
10
100
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input termination pins open and all outputs loaded with external R
L
= 50 W receiver termination resistor.
4. CML outputs require R
L
= 50 W receiver termination resistors to V
CC
for proper operation. (See Figure 9)
5. Input and output parameters vary 1:1 with V
CC
.
6. V
th
is applied to the complementary input when operating in single-ended mode.
7. V
CMR(MIN)
varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential input
signal.
NB7L32M
http://onsemi.com
5
Table 6. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V (Note 8)
Symbol
Characteristic
-40C
255C
855C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
V
OUTPP
Output Voltage Amplitude (@ V
INPP(MIN)
)
f
in
7 GHz
(See Figures 2, 3, 4, 5, 6, and 7)
f
in
12 GHz
190
160
330
320
190
160
330
320
190
160
330
320
mV
f
IN
Maximum Input Clock Frequency
(See Figures 2 and 3)
12
14
12
14
12
14
GHz
t
PLH
,
t
PHL
Propagation Delay to
CLK to Q
Output Differential (See Figure 8)
R to Q
130
200
155
240
200
300
130
200
155
240
200
300
130
200
155
260
200
300
ps
t
skew
Duty Cycle Skew (Note 9)
Device-to-Device Skew (Note 12)
2
6
20
50
2
6
20
50
2
6
20
50
t
RR
Reset Recovery (See Figure 8)
300
135
300
135
300
135
ps
t
PW
Minimum Pulse Width
R 500
210
500
210
500
210
ps
t
JITTER
Random Clock Jitter (RMS)
f
in
7 GHz
(Note 11)
f
in
= 12 GHz
0.13
0.14
0.5
0.5
0.13
0.14
0.5
0.5
0.13
0.14
0.5
0.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
150
2500
150
2500
150
2500
mV
t
r
t
f
Output Rise/Fall Times @ 1 GHz
(20% - 80%)
30
45
30
45
30
45
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing V
INPP(MIN)
from a 50% duty cycle clock source. All loading with an external R
L
= 50 W to V
CC
. Input edge rates 40 ps
(20% - 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ 1 GHz.
10.V
INPP(MAX)
cannot exceed V
CC
- V
EE
. Input voltage swing is a single-ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle input clock signal.
12.Device-to-device skew is measured between outputs under identical transition @ 1 GHz.
NB7L32M
http://onsemi.com
6
Figure 2. Output Voltage Amplitude (V
OUTPP
) versus Input Clock Frequency (f
OUT
) at
Ambient Temperature (V
INPP
= 150 mV)
INPUT CLOCK FREQUENCY (GHz)
0
50
100
150
200
250
300
350
400
450
2
4
6
8
10
12
14
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0
2
4
6
8
10
12
14
16
Figure 3. Input Signal Amplitude vs Input Clock Frequency (All Temperatures and Power Supplies;
Guaranteed Output Amplitude of at Least V
OUTPP
= 160 mV)
INPUT CLOCK FREQUENCY (GHz)
INPUT POWER (dBm)
OUTPUT VOL
T
AGE
AMPLITUDE
(mV)
V
CC
= 3.3 V
V
CC
= 2.5 V
0
INPUT VOL
T
AGE
(mV
rms)
+223.61
+125.74
+70.71
+39.76
+22.36
+12.57
+7.07
+3.98
+2.24
+1.26
Safe Operating Area
Typical
NB7L32M
http://onsemi.com
7
TIME (190 ps/div)
Figure 4. Typical Output Waveform with
f
IN
= 7 GHz( V
CC
= 2.5 V, V
INPP
= 400 mV,
Room Temperature, V
OUTPP
= 357 mV,
t
r
= 33 ps, t
f
= 30 ps, f
OUT
= 3.499 GHz)
TIME (190 ps/div)
Figure 5. Typical Output Waveform with
f
IN
= 7 GHz(V
CC
= 3.3 V, V
INPP
= 400 mV, Room
Temperature, V
OUTPP
= 387 mV, t
r
= 32 ps,
t
f
= 29.8 ps, f
OUT
= 3.499 GHz)
TIME (52 ps/div)
Figure 6. Typical Output Waveform with
f
IN
= 14 GHz(V
CC
= 2.5 V, V
INPP
= 400 mV,
Room Temperature, V
OUTPP
= 292 mV,
t
r
= 25 ps, t
f
= 27 ps, f
OUT
= 7.01 GHz)
TIME (52 ps/div)
Figure 7. Typical Output Waveform with
f
IN
= 14 GHz(V
CC
= 3.3 V, V
INPP
= 400 mV,
Room Temperature, V
OUTPP
= 319 mV,
tr = 25 ps, t
f
= 26 ps, f
OUT
= 7.01 GHz)
VOL
T
AGE (50 mV/div)
VOL
T
AGE (50 mV/div)
VOL
T
AGE (50 mV/div)
VOL
T
AGE (50 mV/div)
Figure 8. AC Reference Measurement (Timing Diagram)
t
PHL
t
PLH
t
RR(MIN)
50%
50%
50%
50%
50%
Q
CLK
R
V
OUTPP
= V
OH
(Q) - V
OL
(Q)
V
INPP
= V
IH
(CLK) - V
IL
(CLK)
NB7L32M
http://onsemi.com
8
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8073/D - Termination of CML Logic Devices.)
Driver
Device
Receiver
Device
Q
D
Q
D
Z
o
= 50 W
Z
o
= 50 W
50 W
50 W
V
CC
Figure 10. Differential Input Driven
Single-Ended
Figure 11. Differential Inputs Driven
Differentially
Figure 12. V
th
Diagram
Figure 13. V
CMR
Diagram
D
V
CC
GND
V
IH
V
IHmin
V
IHmax
V
thmax
V
th
V
th
V
thmin
V
CMmin
V
CMmax
D
V
CMR
V
CC
GND
CLK
CLK
V
th
V
th
CLK
CLK
V
ILmax
V
IL
V
ILmin
D
V
ILDmax
V
IHDmax
V
ID
= V
IHD
- V
ILD
V
ILDtyp
V
IHDtyp
V
ILDmin
V
IHDmin
NOTE: V
EE
v V
IN
v V
CC
+ 300 mV; V
IH
> V
IL
Q
Q
V
CC
16 mA
50 W
50 W
Figure 14. CML Output Structure
V
EE
NB7L32M
http://onsemi.com
9
APPLICATION INFORMATION
All NB7L32M inputs can accept PECL, CML, and LVDS signal levels. The limitations for differential input signal (LVDS,
PECL, or CML) are minimum input swing of 150 mV and the maximum input swing of 2500 mV. Within these conditions,
the input voltage can range from V
CC
to 1.2 V. Examples interfaces are illustrated below in a 50
W environment (Z = 50 W).
For output termination and interface, refer to application note AND8020/D.
Table 5. INTERFACING OPTIONS
Interfacing Options
Connections
CML
Connect VTD and VTD to V
CC
(See Figure 15)
LVDS
Connect VTD and VTD Together (See Figure 17)
AC-COUPLED
Bias VTD and VTD Inputs within Common Mode Range (V
CMR
) (See Figure 16)
RSECL, PECL, NECL
Standard ECL Termination Techniques (See Figure 9)
50 W
V
CC
D
D
50 W
NB7L32M
V
CC
VTD
V
EE
V
CC
Q
50 W 50 W
CML
Driver
V
EE
Figure 15. CML to NB7L32M Interface
Q
Z = 50 W
Figure 16. PECL to NB7L32M Interface
50 W
V
CC
V
CC
PECL
Driver
D
D
50 W
NB7L32M
V
EE
V
Bias
*
VTD
V
EE
R
T
R
T
V
EE
V
CC
R
T
5.0 V 290 W
3.3 V 150 W
2.5 V 80 W
Recommended R
T
Values
VTD
V
CC
VTD
V
Bias
*
Z = 50 W
Z = 50 W
Z = 50 W
C
C
*V
Bias
must be within common mode range limits (V
CMR
)
NB7L32M
http://onsemi.com
10
APPLICATION INFORMATION
50 W
V
CC
V
CC
LVDS
Driver
D
D
50 W
NB7L32M
V
EE
VTD
V
EE
VTD
Figure 17. LVDS to NB7L32M Interface
Z = 50 W
Z = 50 W
ORDERING INFORMATION
Device
Package
Shipping
NB7L32MMNG
QFN-16
(Pb-Free)
123 Units / Rail
NB7L32MMNR2G
QFN-16
(Pb-Free)
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NB7L32M
http://onsemi.com
11
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE B
16X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
1
4
5
8
12
9
16
13
B
A
0.15 C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.10 C
0.08 C
(A3)
C
16 X
e
16X
NOTE 5
0.10 C
0.05 C
A B
NOTE 3
K
16X
EXPOSED PAD
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. L
max
CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
DIM MIN
MAX
MILLIMETERS
A
0.80
1.00
A1
0.00
0.05
A3
0.20 REF
b
0.18
0.30
D
3.00 BSC
D2
1.65
1.85
E
3.00 BSC
E2
1.65
1.85
e
0.50 BSC
K
0.20
---
L
0.30
0.50
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
NB7L32M/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082-1312 USA
Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada
Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
PDF 
ZIP