Semiconductor Components Industries, LLC, 2003
May, 2003 - Rev. 2
1
Publication Order Number:
NBC12439/D
NBC12439
3.3 V/5 V Programmable
PLL Synthesized Clock
Generator
50 MHz to 800 MHz
The NBC12439 is a general purpose, PLL based synthesized clock
source. The VCO will operate over a frequency range of 400 MHz to
800 MHz. The VCO frequency is sent to the N-output divider, where
it can be configured to provide division ratios of 1, 2, 4 or 8. The VCO
and output frequency can be programmed using the parallel or serial
interfaces to the configuration logic. The PLL loop filter is fully
integrated and does not require any external components.
Best-in-Class Output Jitter Performance,
20 ps Peak-to-Peak
50 MHz to 800 MHz Programmable Differential PECL Outputs
Fully Integrated Phase-Lock-Loop with Internal Loop Filter
Parallel Interface for Programming Counter and Output Dividers
During Power-Up
Minimal Frequency Overshoot
Serial 3-Wire Programming Interface
Crystal Oscillator Interface
Operating Range: V
CC
= 3.135 V to 5.25 V
CMOS and TTL Compatible Control Inputs
Pin Compatible with Motorola MC12439
Power-Down of PECL Outputs (
B16)
MARKING
DIAGRAMS
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PLCC-28
FN SUFFIX
CASE 776
NBC12439
AWLYYWW
1 28
LQFP-32
FA SUFFIX
CASE 873A
NBC12439
AWLYYWW
Device
Package
Shipping
ORDERING INFORMATION
NBC12439FN
PLCC-28
37 Units/Rail
NBC12439FNR2
PLCC-28
500 Tape & Reel
NBC12439FA
LQFP-32
250 Units/Tray
NBC12439FAR2
LQFP-32
2000 Tape & Reel
1
32
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NBC12439
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2
Figure 1. NBC12439 Block Diagram (28-Lead PLCC)
7-BIT
B
M
COUNTER
B
2
7- BIT SR
2- BIT SR
3- BIT SR
B
2
10-20MHz
S_LOAD
P_LOAD
S_DATA
S_CLOCK
XTAL1
XTAL2
OSC
4
5
PHASE
DETECTOR
28
7
LATCH
VCO
B
N
(1, 2, 4, 8)
LATCH
400-800
MHz
FOUT
FOUT
+3.3 or 5.0 V
21, 25
24
23
V
CC
LATCH
TEST
20
+3.3 or 5.0 V
PLL_V
CC
F
REF
0
1
27
26
0
1
M[6:0]
7
8
14
N[1:0]
2
17, 18
22, 19
OE
6
FREF_EXT
3
XTAL_SEL
15
1
N [1:0]
Output Division
0 0
0 1
1 0
1 1
2
4
8
1
Input
0
PWR_DOWN
XTAL_SEL
OE
FOUT
FREF_EXT
Disabled
1
FOUT
B
16
XTAL
Enabled
PWR_DOWN
2
POWER
DOWN
Table 1. Output Division
Table 2. XTAL_SEL and OE
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3
N[1]
N[0]
NC
XTAL_SEL
M[6]
M[5]
M[4]
XTAL1
FREF_EXT
PWR_DOWN
PLL_V
CC
S_LOAD
S_DATA
S_CLOCK
Figure 2. 28-Lead PLCC (Top View)
V
CC
FOUT
FOUT
GND
V
CC
GND
TEST
XT
AL2
OE
P_LOAD
M[0]
M[1]
M[2]
M[3]
Figure 3. 32-Lead LQFP (Top View)
N/C
N[1]
N[0]
NC
XTAL_SEL
M[6]
M[5]
FREF_EXT
PWR_DOWN
PLL_V
CC
PLL_V
CC
S_LOAD
S_DATA
S_CLOCK
FOUT
FOUT
GND
V
CC
V
CC
GND
TEST
OE
P_LOAD
M[0]
M[1]
M[2]
M[3]
N/C
M[4]
XTAL1
V
CC
XT
AL2
26
27
28
1
2
3
4
18
17
16
15
14
13
12
5
6
7
8
9
10
11
25
24
23
22
21
20
19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
NBC12439
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4
The following gives a brief description of the functionality of the NBC12439 Inputs and Outputs. Unless explicitly stated,
all inputs are CMOS/TTL compatible with either pull-up or pulldown resistors. The PECL outputs are capable of driving two
series terminated 50
W transmission lines on the incident edge.
PIN FUNCTION DESCRIPTION
Pin Name
Function
Description
INPUTS
XTAL1, XTAL2
Crystal Inputs
These pins form an oscillator when connected to an external series-resonant
crystal.
S_LOAD*
CMOS/TTL Serial Latch Input
(Internal Pulldown Resistor)
This pin loads the configuration latches with the contents of the shift registers. The
latches will be transparent when this signal is HIGH; thus, the data must be stable
on the HIGH-to-LOW transition of S_LOAD for proper operation.
S_DATA*
CMOS/TTL Serial Data Input
(Internal Pulldown Resistor)
This pin acts as the data input to the serial configuration shift registers.
S_CLOCK*
CMOS/TTL Serial Clock Input
(Internal Pulldown Resistor)
This pin serves to clock the serial configuration shift registers. Data from S_DATA
is sampled on the rising edge.
P_LOAD**
CMOS/TTL Parallel Latch Input
(Internal Pullup Resistor)
This pin loads the configuration latches with the contents of the parallel inputs
.The latches will be transparent when this signal is LOW; therefore, the parallel
data must be stable on the LOW-to-HIGH transition of P_LOAD for proper opera-
tion.
M[6:0]**
CMOS/TTL PLL Loop Divider
Inputs (Internal Pullup Resistor)
These pins are used to configure the PLL loop divider. They are sampled on the
LOW-to-HIGH transition of P_LOAD. M[8] is the MSB, M[0] is the LSB.
N[1:0]**
CMOS/TTL Output Divider Inputs
(Internal Pullup Resistor)
These pins are used to configure the output divider modulus. They are sampled
on the LOW-to-HIGH transition of P_LOAD.
OE**
CMOS/TTL Output Enable Input
(Internal Pullup Resistor)
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of
runt pulse generation on the FOUT output.
FREF_EXT*
CMOS/TTL Input
(Internal Pulldown Resistor)
This pin can be used as the PLL Reference
XTAL_SEL**
CMOS/TTL Input
(Internal Pullup Resistor)
This pin selects between the crystal and the FREF_EXT source for the PLL refer-
ence signal. A HIGH selects the crystal input.
PWR_DOWN
CMOS/TTL Input
(Internal Pulldown Resistor)
PWR_DOWN forces the FOUT outputs to synchronously reduce frequency by a
factor of 16.
OUTPUTS
FOUT, FOUT
PECL Differential Outputs
These differential, positive-referenced ECL signals (PECL) are the outputs of the
synthesizer.
TEST
CMOS/TTL Output
The function of this output is determined by the serial configuration bits T[2:0].
POWER
V
CC
Positive Supply for the Logic
The positive supply for the internal logic and output buffer of the chip, and is con-
nected to +3.3 V or +5.0 V.
PLL_V
CC
Positive Supply for the PLL
This is the positive supply for the PLL and is connected to +3.3 V or +5.0 V.
GND
Negative Power Supply
These pins are the negative supply for the chip and are normally all connected to
ground.
*
When left Open, these inputs will default LOW.
** When left Open, these inputs will default HIGH.
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5
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
W
Internal Input Pullup Resistor
37.5 k
W
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 1 kV
Moisture Sensitivity (Note 1)
PLCC
LQFP
Level 1
Level 2
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
2269
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS
(Note 2)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
CC
Positive Supply
GND = 0 V
-
6
V
V
I
Input Voltage
GND = 0 V
V
I
V
CC
6
V
I
out
Output Current
Continuous
Surge
-
-
50
100
mA
mA
TA
Operating Temperature Range
-
-
0 to +70
C
T
stg
Storage Temperature Range
-
-
-65 to +150
C
q
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
C/W
C/W
q
JC
Thermal Resistance (Junction to Case)
std bd
28 PLCC
22 to 26
C/W
q
JA
Thermal Resistance (Junction to Ambient)
0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
C/W
C/W
q
JC
Thermal Resistance (Junction to Case)
std bd
32 LQFP
12 to 17
C/W
T
sol
Wave Solder
< 3 sec @ 248
C
-
265
C
2. Maximum Ratings are those values beyond which device damage may occur.
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6
DC CHARACTERISTICS
(V
CC
= 3.3 V
5%)
0
C
25
C
70
C
Symbol
Characteristic
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
IH
LVCMOS/
LVTTL
Input HIGH Voltage
V
CC
= 3.3 V
2.0
-
-
2.0
-
-
2.0
-
-
V
V
IL
LVCMOS/
LVTTL
Input LOW Voltage
V
CC
= 3.3 V
-
-
0.8
-
-
0.8
-
-
0.8
V
I
IN
Input Current
-
-
1.0
-
-
1.0
-
-
1.0
mA
V
OH
Output HIGH Voltage
TEST
I
OH
= -0.8 mA
2.5
-
-
2.5
-
-
2.5
-
-
V
V
OL
Output LOW Voltage
TEST
I
OL
= 0.8 mA
-
-
0.4
-
-
0.4
-
-
0.4
V
V
OH
PECL
Output HIGH Voltage
FOUT
FOUT
V
CC
= 3.3 V
(Notes 3, 4)
2.155
-
2.405
2.155
-
2.405
2.155
-
2.405
V
V
OL
PECL
Output LOW Voltage
FOUT
FOUT
V
CC
= 3.3 V
(Notes 3, 4)
1.355
-
1.675
1.355
-
1.675
1.355
-
1.675
V
I
CC
Power Supply Current
V
CC
PLL_V
CC
44
19
56
23
80
28
44
19
58
23
80
28
44
19
61
23
80
28
mA
mA
3. FOUT/FOUT output levels will vary 1:1 with V
CC
variation.
4. FOUT/FOUT outputs are terminated through a 50
W
resistor to V
CC
- 2.0 volts.
DC CHARACTERISTICS
(V
CC
= 5.0 V
5%)
0
C
25
C
70
C
Symbol
Characteristic
Condition
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
IH
CMOS/
TTL
Input HIGH Voltage
V
CC
= 5.0 V
2.0
-
-
2.0
-
-
2.0
-
-
V
V
IL
CMOS/
TTL
Input LOW Voltage
V
CC
= 5.0 V
-
-
0.8
-
-
0.8
-
-
0.8
V
I
IN
Input Current
-
-
1.0
-
-
1.0
-
-
1.0
mA
V
OH
Output HIGH Voltage
TEST
I
OH
= -0.8 mA
2.5
-
-
2.5
-
-
2.5
-
-
V
V
OL
Output LOW Voltage
TEST
I
OL
= 0.8 mA
-
-
0.4
-
-
0.4
-
-
0.4
V
V
OH
PECL
Output HIGH Voltage
FOUT
FOUT
V
CC
= 5.0 V
(Notes 5, 6)
3.855
-
4.105
3.855
-
4.105
3.855
-
4.105
V
V
OL
PECL
Output LOW Voltage
FOUT
FOUT
V
CC
= 5.0 V
(Notes 5, 6)
3.055
-
3.305
3.055
-
3.305
3.055
-
3.305
V
I
CC
Power Supply Current
V
CC
PLL_V
CC
47
19
58
24
85
28
47
19
60
24
85
28
47
19
64
24
85
28
mA
mA
5. FOUT/FOUT output levels will vary 1:1 with V
CC
variation.
6. FOUT/FOUT outputs are terminated through a 50
W
resistor to V
CC
- 2.0 volts.
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7
AC CHARACTERISTICS
(V
CC
= 3.135 V to 5.25 V
5%; T
A
= 0
to 70
C) (Note 8)
Symbol
Characteristic
Condition
Min
Max
Unit
F
MAXI
Maximum Input Frequency
S_CLOCK
Xtal Oscillator
FREF_EXT
(Note 7)
-
10
10
10
20
Note 9
MHz
F
MAXO
Maximum Output Frequency
VCO (Internal)
FOUT
400
50
800
800
MHz
t
LOCK
Maximum PLL Lock Time
-
10
ms
t
jitter
Cycle-to-Cycle Jitter (Peak-to-Peak)
(Note 10)
1000 Cycles
-
"
20
ps
t
s
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
-
-
-
ns
t
h
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
-
-
-
ns
tpw
MIN
Minimum Pulse Width
S_LOAD
P_LOAD
50
50
-
-
ns
DCO
Output Duty Cycle
47.5
52.5
%
t
r
, t
f
Output Rise/Fall
FOUT
20%-80%
175
425
ps
7. 10 MHz is the maximum frequency to load the feedback divide registers. S_CLOCK can be switched at higher frequencies when used as
a test clock in TEST_MODE 6.
8. FOUT/FOUT outputs are terminated through a 50
W
resistor to V
CC
- 2.0 V.
9. Maximum frequency on FREF_EXT is a function of setting the appropriate M counter value, 25 MHz
v
M
v
50 MHz, for the VCO to operate
within the valid range of 400 MHz
v
f
VCO
v
800 MHz. The internal phase detector can handle up to 100 MHz on its input.
10. See applications information section.
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8
FUNCTIONAL DESCRIPTION
The internal oscillator uses the external quartz crystal as
the basis of its frequency reference. The output of the
reference oscillator is divided by 16 before being sent to the
phase detector. With a 2 MHz crystal, this provides a
reference frequency of 8 MHz. Although this data sheet
illustrates functionality only for a 16 MHz crystal, Table 3,
any crystal in the 10-20 MHz range can be used, Table 5.
The VCO within the PLL operates over a range of 400 to
800 MHz. Its output is scaled by a divider, M divider, that is
configured by either the serial or parallel interfaces. The
output of this loop divider is also applied to the phase
detector.
The phase detector and the loop filter force the VCO
output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve loop lock.
The output of the VCO is also passed through an output
divider before being sent to the PECL output driver. This
N output divider is configured through either the serial or the
parallel interfaces and can provide one of four division ratios
(1, 2, 4, or 8). This divider extends the performance of the
part while providing a 50% duty cycle.
The output driver is driven differentially from the output
divider and is capable of driving a pair of transmission lines
terminated into 50
W
to V
CC
-2.0 V. The positive reference
for the output driver and the internal logic is separated from
the power supply for the phase-locked loop to minimize
noise induced jitter.
The configuration logic has two sections: serial and
parallel. The parallel interface uses the values at the M[6:0]
and N[1:0] inputs to configure the internal counters.
Normally upon system reset, the P_LOAD input is held
LOW until sometime after power becomes valid. On the
LOW-to-HIGH transition of P_LOAD, the parallel inputs
are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the
M[6:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface logic is implemented with a fourteen
bit shift register scheme. The register shifts once per rising
edge of the S_CLOCK input. The serial input S_DATA must
meet setup and hold timing as specified in the AC
Characteristics section of this document. With P_LOAD
held high, the configuration latches will capture the value of
the shift register on the HIGH-to-LOW edge of the
S_LOAD input. See the programming section for more
information.
The TEST output reflects various internal node values and
is controlled by the T[2:0] bits in the serial data stream. See
the programming section for more information.
Table 3. Programming VCO Frequency Function Table with 16 MHz Crystal
VCO
64
32
16
8
4
2
1
VCO
Frequency (MHz)
M Count
M6
M5
M4
M3
M2
M1
M0
400
25
0
0
1
1
0
0
1
416
26
0
0
1
1
0
1
0
432
27
0
0
1
1
0
1
1
448
28
0
0
1
1
1
0
0
752
47
0
1
0
1
1
1
1
768
48
0
1
1
0
0
0
0
784
49
0
1
1
0
0
0
1
800
50
0
1
1
0
0
1
0
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9
PROGRAMMING INTERFACE
Programming the NBC12439 is accomplished by
properly configuring the internal dividers to produce the
desired frequency at the outputs. The output frequency can
by represented by this formula:
FOUT
+
(FXTAL
B
2)
2M
B
N
(eq. 1)
This can be simplified to:
FOUT
+
FXTALxM
B
N
(eq. 2)
where F
XTAL
is the crystal frequency, M is the loop divider
modulus, and N is the output divider modulus. Note that it
is possible to select values of M such that the PLL is unable
to achieve loop lock. To avoid this, always make sure that M
is selected to be 25
M
50 for a 16 MHz input reference.
See Table 5.
Assuming that a 16 MHz reference frequency is used the
above equation reduces to:
FOUT
+
16M
B
N
(eq. 3)
Substituting the four values for N (1, 2, 4, 8) yields:
Table 4. Programmable Output Divider Function Table
N1
N0
N Divider
FOUT
Output Frequency
Range (MHz)*
1
1
B
1
M
16
400-800
0
0
B
2
M
8
200-400
0
1
B
4
M
4
100-200
1
0
B
8
M
2
50-100
*For crystal frequency of 16 MHz.
The user can identify the proper M and N values for the
desired frequency from the above equations. The four output
frequency ranges established by N are 400- 800
MHz,
200- 400 MHz, 100- 200 MHz and 50- 100 MHz, respectively.
From these ranges, the user will establish the value of N
required. The value of M can then be calculated based on
equation 1. For example, if an output frequency of 384 MHz
was desired, the following steps would be taken to identify the
appropriate M and N values. 384 MHz falls within the
frequency range set by an N value of 2; thus, N [1:0] = 00.
For N = 2, F
OUT
= 8M and M = F
OUT
B 8. Therefore,
M = 384
B 8 = 48, so M[6:0] = 0110000. Following this same
procedure, a user can generate a selected frequency. The size
of the programmable frequency steps of F
OUT
will be equal
to FXTAL
N.
For input reference frequencies other than 16 MHz, see
Table 5, which shows the usable VCO frequency and M
divider range.
The input frequency and the selection of the feedback
divider M is limited by the VCO frequency range and
fXTAL. M must be configured to match the VCO frequency
range of 400 to 800 MHz in order to achieve stable PLL
operation.
M min
+
fVCOmin
B
FXTAL and
(eq. 4)
M max
+
fVCOmax
B
FXTAL
(eq. 5)
The value for M falls within the constraints set for PLL
stability. If the value for M fell outside of the valid range, a
different N value would be selected to move M in the
appropriate direction.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is
controlled
via the P_LOAD signal such that a LOW to HIGH
transition will latch the information present on the M[6:0]
and N[1:0] inputs into the M and N counters. When the
P_LOAD signal is LOW, the input latches will be
transparent
and any changes on the M[6:0] and N[1:0] inputs
will affect the FOUT output pair. To use the serial port, the
S_CLOCK signal samples the information on the S_DATA
line and loads it into a 12 bit shift register. Note that the
P_LOAD signal must be HIGH for the serial load operation
to function. The Test register is loaded with the first three
bits, the N register with the next two, and the M register with
the final nine bits of the data stream on the S_DATA input.
For each register, the most significant bit is loaded first (T2,
N1, and M6). The HIGH to LOW transition on the S_LOAD
input will latch the new divide values into the counters. A
pulse on the S_LOAD pin after the shift register is fully
loaded will transfer the divide values into the counters.
Figures 4 and 5 illustrate the timing diagram for both a
parallel and a serial load of the NBC12439 synthesizer.
M[6:0] and N[1:0] are normally specified after power-up
through the parallel interface, and then possibly, fine tuned
again through the serial interface. This approach allows the
application to ramp up at one frequency and then change or
fine-tune the clock as the ability to control the serial
interface becomes available.
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. The T2, T1, and T0 control bits are preset
to `000' when P_LOAD is LOW so that the PECL FOUT
outputs are as jitter-free as possible. Any active signal on the
TEST output pin will have detrimental affects on the jitter
of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin.
NBC12439
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10
Table 5. NBC12439 Frequency Operating Range
VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of:
Output Frequency (MHz) for
fXTAL = 16 MHz and for N =
M
M[6:0]
10
12
14
16
18
20
B
1
B
2
B
4
B
8
20
0010100
400
21
0010101
420
22
0010110
440
23
0010111
414
460
24
0011000
432
480
25
0011001
400
450
500
400
200
100
50
26
0011010
416
468
520
416
208
104
52
27
0011011
432
486
540
432
216
108
54
28
0011100
448
504
560
448
224
112
56
29
0011101
406
464
522
580
464
232
116
58
30
0011110
420
480
540
600
480
240
120
60
31
0011111
434
496
558
620
496
248
124
62
32
0100000
448
512
576
640
512
256
128
64
33
0100001
462
528
594
660
528
264
132
66
34
0100010
408
476
544
612
680
544
272
136
68
35
0100011
420
490
560
630
700
560
280
140
70
36
0100100
432
504
576
648
720
576
288
144
72
37
0100101
444
518
592
666
740
592
296
148
74
38
0100110
456
532
608
684
760
608
304
152
76
39
0100111
468
546
624
702
780
624
312
156
78
40
0101000
400
480
560
640
720
800
640
320
160
80
41
0101001
410
492
574
656
738
656
328
164
82
42
0101010
420
504
588
672
756
672
336
168
84
43
0101011
430
516
602
688
774
688
344
172
86
44
0101100
440
528
616
704
792
704
352
176
88
45
0101101
450
540
630
720
720
360
180
90
46
0101110
460
552
644
736
736
368
184
92
47
0101111
470
564
658
752
752
376
188
94
48
0110000
480
576
672
768
768
384
192
96
49
0110001
490
588
686
784
784
392
196
98
50
0110010
500
600
700
800
800
400
200
100
51
0110011
510
612
714
52
0110100
520
624
728
53
0110101
530
636
742
54
0110110
540
648
756
55
0110111
550
660
770
56
0111000
560
672
784
57
0111001
570
684
798
58
0111010
580
696
59
0111011
590
708
60
0111100
600
720
61
0111101
610
732
62
0111110
620
744
63
0111111
630
756
64
1000000
640
768
65
1000001
650
780
66
1000010
660
792
67
1000011
670
68
1000100
680
69
1000101
690
70
1000110
700
71
1000111
710
72
1001000
720
73
1001001
730
74
1001010
740
75
1001011
750
76
1001100
760
77
1001101
770
78
1001110
780
79
1001111
790
80
1010000
800
NBC12439
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11
Most of the signals available on the TEST output pin are
useful only for performance verification of the NBC12439
itself. However, the PLL bypass mode may be of interest at
the board level for functional debug. When T[2:0] is set to
110, the NBC12439 is placed in PLL bypass mode. In this
mode the S_CLOCK input is fed directly into the M and N
dividers. The N divider drives the FOUT differential pair
and the M counter drives the TEST output pin. In this mode
the S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
FOUT directly gives the user more control on the test clocks
sent through the clock tree. Figure 6 shows the functional
setup of the PLL bypass mode. Because the S_CLOCK is a
CMOS level the input frequency is limited to 250 MHz or
less. This means the fastest the FOUT pin can be toggled via
the S_CLOCK is 250 MHz as the minimum divide ratio of
the N counter is 1. Note that the M counter output on the
TEST output will not be a 50% duty cycle due to the way the
divider is implemented.
T2
T1
T0
TEST OUTPUT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SHIFT REGISTER OUT
HIGH
FREF
M COUNTER OUT
FOUT
LOW
PLL BYPASS
FOUT
B
4
Figure 4. Parallel Interface Timing Diagram
M[8:0]
N[1:0]
P_LOAD
M, N
Figure 5. Serial Interface Timing Diagram
S_CLOCK
S_DATA
S_LOAD
T2
T1
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0
First
Bit
Last
Bit
Figure 6. Serial Test Clock Block Diagram
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
TEST
MUX
7
0
TEST
FOUT
(VIA ENABLE GATE)
N
B
(1, 2, 4, 8)
0
1
PLL 12439
LATCH
Reset
PLOAD
M COUNTER
SLOAD
T0
T1
T2
VCO_CLK
SHIFT
REG
12- BIT
DECODE
SDATA
SCLOCK
MCNT
FREF_EXT
SEL_CLK
T2=T1=1, T0=0: Test Mode
SCLOCK is selected, MCNT is on TEST output, SCLOCK
B
N is on FOUT pin.
PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.
NBC12439
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12
APPLICATIONS INFORMATION
Using the On-Board Crystal Oscillator
The NBC12439 features a fully integrated on-board
crystal oscillator to minimize system implementation costs.
The oscillator is a series resonant, multivibrator type design
as opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs, the user is
advised to mount the crystal as close to the NBC12439 as
possible to avoid any board level parasitics. To facilitate
co-location, surface mount crystals are recommended, but
not required. Because the series resonant design is affected
by capacitive loading on the crystal terminals, loading
variation introduced by crystals from different vendors
could be a potential issue. For crystals with a higher shunt
capacitance, it may be required to place a resistance across
the terminals to suppress the third harmonic. Although
typically not required, it is a good idea to layout the PCB
with the provision of adding this external resistor. The
resistor value will typically be between 500
W
and 1 K
W.
The oscillator circuit is a series resonant circuit and thus,
for optimum performance, a series resonant crystal should
be used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the NBC12439 with only a minor error in the
desired frequency. A parallel resonant mode crystal used in
a series resonant circuit will exhibit a frequency of
oscillation a few hundred ppm lower than specified (a few
hundred ppm translates to kHz inaccuracy). Table 6 below
specifies the performance requirements of the crystals to be
used with the NBC12439.
Table 6. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
75 ppm at 25
C
Frequency/Temperature Stability
150 ppm 0 to 70
C
Operating Range
0 to 70
C
Shunt Capacitance
5-7 pF
Equivalent Series Resistance (ESR)
50 to 80
W
Correlation Drive Level
100
m
W
Aging
5 ppm/Yr
(First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
Power Supply Filtering
The NBC12439 is a mixed analog/digital product and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NBC12439 provides
separate power supplies for the digital circuitry (V
CC
) and
the internal PLL (PLL_V
CC
) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phase-locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
filter on the PLL_V
CC
pin for the NBC12439.
Figure 7 illustrates a typical power supply filter scheme.
The NBC12439 is most susceptible to noise with spectral
content in the 1 KHz to 1 MHz range. Therefore, the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the V
CC
supply and the
PLL_V
CC
pin of the NBC12439. From the data sheet, the
PLL_V
CC
current (the current sourced through the
PLL_V
CC
pin) is typically 23 mA (28 mA maximum).
Assuming that a minimum of 2.8 V must be maintained on
the PLL_V
CC
pin, very little DC voltage drop can be
tolerated when a 3.3 V V
CC
supply is used. The resistor
shown in Figure 7 must have a resistance of 10-15
W to meet
the voltage drop criteria. The RC filter pictured will provide
a broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor, it's overall impedance begins to look inductive
and thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL.
NBC12439
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13
Figure 7. Power Supply Filter
PLL_V
CC
V
CC
NBC12439
0.01
m
F
22
m
F
L=1000
m
H
R=15
W
0.01
m
F
3.3 V or
5.0 V
R
S
= 10-15
W
3.3 V or
5.0 V
A higher level of attenuation can be achieved by replacing
the resistor with an appropriate valued inductor. Figure 7
shows a 1000
mH choke. This value choke will show a
significant impedance at 10 KHz frequencies and above.
Because of the current draw and the voltage that must be
maintained on the PLL_V
CC
pin, a low DC resistance
inductor is required (less than 15
W). Generally, the
resistor/capacitor filter will be cheaper, easier to implement,
and provide an adequate level of supply filtering.
The NBC12439 provides sub-nanosecond output edge
rates and therefore a good power supply bypassing scheme
is a must. Figure 8 shows a representative board layout for
the NBC12439. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 8 is the low impedance connections
between V
CC
and GND for the bypass capacitors.
Combining good quality general purpose chip capacitors
with good PCB layout techniques will produce effective
capacitor resonances at frequencies adequate to supply the
instantaneous switching current for the NBC12439 outputs.
It is imperative that low inductance chip capacitors are used.
It is equally important that the board layout not introduce
any of the inductance saved by using the leadless capacitors.
Thin interconnect traces between the capacitor and the
power plane should be avoided and multiple large vias
should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors.
Figure 8. PCB Board Layout for NBC12439 (28 PLCC)
C2
1
C3
R1
Xtal
C1
C1
R1 = 10-15
W
C1 = 0.01
m
F
C2 = 22
m
F
C3 = 0.1
m
F
= V
CC
= GND
= Via
Note the dotted lines circling the crystal oscillator
connection to the device. The oscillator is a series resonant
circuit and the voltage amplitude across the crystal is
relatively small. It is imperative that no actively switching
signals cross under the crystal as crosstalk energy coupled
to these lines could significantly impact the jitter of the
device. Special attention should be paid to the layout of the
crystal to ensure a stable, jitter free interface between the
crystal and the on-board oscillator. Note the provisions for
placing a resistor across the crystal oscillator terminals as
discussed in the crystal oscillator section of this data sheet.
Although the NBC12439 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL), there still
may be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise-related
problems in most designs.
NBC12439
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14
Jitter Performance of the NBC12439
Jitter is a common parameter associated with clock
generation and distribution. Clock jitter can be defined as the
deviation in a clock's output transition from its ideal
position.
Cycle-to-Cycle Jitter (short-term) is the period
variation
between adjacent periods over a defined number of
observed cycles. The number of cycles observed is
application dependent but the JEDEC specification is 1000
cycles. See Figure 9.
Figure 9. Cycle-to-Cycle Jitter
T
JITTER(cycle- cycle)
= T
1
- T
0
T
0
T
1
Random Peak-to-Peak Jitter is the difference between
the highest and lowest acquired value and is represented as
the width of the Gaussian base. See Figure 10.
Figure 10. Random Peak-to-Peak and RMS Jitter
Time*
Typical
Gaussian
Distribution
RMS
or one
Sigma
Jitter
Jitter Amplitude
Peak-to-Peak Jitter
*1,000 - 10,000 Cycles
There are different ways to measure jitter and often they
are confused with one another. An earlier method of
measuring jitter is to look at the timing signal with an
oscilloscope and observe the variations in period-to-period
or cycle-to-cycle. If the scope is set up to trigger on every
rising or falling edge, set to infinite persistence mode and
allowed to trace sufficient cycles, it is possible to determine
the maximum and minimum periods of the timing signal.
Digital scopes can accumulate a large number of cycles,
create a histogram of the edge placements and record
peak-to-peak as well as standard deviations of the jitter.
Care must be taken that the measured edge is the edge
immediately following the trigger edge. These scopes can
also store a finite number of period durations and
post-processing software can analyze the data to find the
maximum and minimum periods.
Recent hardware and software developments have
resulted in advanced jitter measurement techniques. The
Tektronix TDS-series oscilloscopes have superb jitter
analysis capabilities on non-contiguous clocks with their
histogram and statistics capabilities. The Tektronix
TDSJIT2/3 Jitter Analysis software provides many key
timing parameter measurements and will extend that
capability by making jitter measurements on contiguous
clock and data cycles from single-shot acquisitions.
M1 by Amherst was used as well and both test methods
correlated.
These test processes can be correlated to earlier test
methods and are more accurate. All of the jitter data reported
on the NBC12439 was collected in this manner. Figure 11
shows the RMS jitter performance as a function of the VCO
frequency range. The general trend is that as the VCO
frequency is increased, the RMS output jitter will decrease.
Figure 12 illustrates the RMS jitter performance versus
the output frequency. Note the jitter is a function of both the
output frequency as well as the VCO frequency. However,
the VCO frequency shows a much stronger dependence.
Long-Term Period Jitter is the maximum jitter
observed at the end of a period's edge when compared to the
position of the perfect reference clock's edge and is specified
by the number of cycles over which the jitter is measured.
The number of cycles used to look for the maximum jitter
varies by application but the JEDEC spec is 10,000 observed
cycles.
The NBC12439 exhibits long term and cycle-to-cycle
jitter, which rivals that of SAW based oscillators. This jitter
performance comes with the added flexibility associated
with a synthesizer over a fixed frequency oscillator. The
jitter data presented should provide users with enough
information to determine the effect on their overall timing
budget. The jitter performance meets the needs of most
system designs while adding the flexibility of frequency
margining and field upgrades. These features are not
available with a fixed frequency SAW oscillator.
NBC12439
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15
Figure 11. Cycle-to-Cycle RMS Jitter vs.
VCO Frequency
VCO FREQUENCY (MHz)
400
500
600
700
800
25
20
15
10
5
0
RMS JITTER (ps)
N = 1
N = 8
N = 2
N = 4
Figure 12. Cycle-to-Cycle RMS Jitter vs.
Output Frequency
25
20
15
10
5
0
RMS JITTER (ps)
800
700
600
500
400
300
200
100
OUTPUT FREQUENCY (MHz)
NBC12439
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16
t
SET- UP
t
HOLD
S_CLOCK
S_DATA
Figure 13. Set-Up and Hold
t
SET- UP
t
HOLD
S_LOAD
S_DATA
Figure 14. Set-Up and Hold
t
SET- UP
t
HOLD
P_
LOAD
M[8:0]
Figure 15. Set-Up and Hold
t
PERIOD
Pulse Width
F
OUT
F
OUT
Figure 16. Output Duty Cycle
N[1:0]
DCO
+
t
pw
t
PERIOD
NBC12439
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17
V TT = V CC - 2.0 V
Figure 17. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 - Termination of ECL Logic Devices.)
W
Driver
Device
Receiver
Device
D
50
W
50
V TT
F
OUT
D
F
OUT
NBC12439
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18
PACKAGE DIMENSIONS
PLCC-28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776-02
ISSUE E
-N-
-M-
-L-
V
W
D
D
Y BRK
28
1
VIEW S
S
L-M
S
0.010 (0.250)
N
S
T
S
L-M
M
0.007 (0.180)
N
S
T
0.004 (0.100)
G1
G
J
C
Z
R
E
A
SEATING
PLANE
S
L-M
M
0.007 (0.180)
N
S
T
-T-
B
S
L-M
S
0.010 (0.250)
N
S
T
S
L-M
M
0.007 (0.180)
N
S
T
U
S
L-M
M
0.007 (0.180)
N
S
T
Z
G1
X
VIEW D-D
S
L-M
M
0.007 (0.180)
N
S
T
K1
VIEW S
H
K
F
S
L-M
M
0.007 (0.180)
N
S
T
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.485
0.495
12.32
12.57
B
0.485
0.495
12.32
12.57
C
0.165
0.180
4.20
4.57
E
0.090
0.110
2.29
2.79
F
0.013
0.019
0.33
0.48
G
0.050 BSC
1.27 BSC
H
0.026
0.032
0.66
0.81
J
0.020
---
0.51
---
K
0.025
---
0.64
---
R
0.450
0.456
11.43
11.58
U
0.450
0.456
11.43
11.58
V
0.042
0.048
1.07
1.21
W
0.042
0.048
1.07
1.21
X
0.042
0.056
1.07
1.42
Y
---
0.020
---
0.50
Z
2
10
2
10
G1
0.410
0.430
10.42
10.92
K1
0.040
---
1.02
---
_
_
_
_
NBC12439
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19
PACKAGE DIMENSIONS
LQFP-32
FA SUFFIX
PLASTIC LQFP PACKAGE
CASE 873A-02
ISSUE A
DETAIL Y
A
S1
V
B
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
D
F
METAL
SECTION AE-AE
G
SEATING
PLANE
R
Q
_
W
K
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DETAIL AD
A1
B1
V1
4X
S
4X
9
-T-
-Z-
-U-
T-U
0.20 (0.008)
Z
AC
T-U
0.20 (0.008)
Z
AB
0.10 (0.004) AC
-AC-
-AB-
M
_
8X
-T-, -U-, -Z-
T-U
M
0.20 (0.008)
Z
AC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIM
A
MIN
MAX
MIN
MAX
INCHES
7.000 BSC
0.276 BSC
MILLIMETERS
B
7.000 BSC
0.276 BSC
C
1.400
1.600
0.055
0.063
D
0.300
0.450
0.012
0.018
E
1.350
1.450
0.053
0.057
F
0.300
0.400
0.012
0.016
G
0.800 BSC
0.031 BSC
H
0.050
0.150
0.002
0.006
J
0.090
0.200
0.004
0.008
K
0.500
0.700
0.020
0.028
M
12 REF
12 REF
N
0.090
0.160
0.004
0.006
P
0.400 BSC
0.016 BSC
Q
1
5
1
5
R
0.150
0.250
0.006
0.010
V
9.000 BSC
0.354 BSC
V1
4.500 BSC
0.177 BSC
_
_
_
_
_
_
B1
3.500 BSC
0.138 BSC
A1
3.500 BSC
0.138 BSC
S
9.000 BSC
0.354 BSC
S1
4.500 BSC
0.177 BSC
W
0.200 REF
0.008 REF
X
1.000 REF
0.039 REF
NBC12439
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20
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
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may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
NBC12439/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 800-282-9855 Toll Free USA/Canada
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