Semiconductor Components Industries, LLC, 2003
April, 2003 - Rev. 6
1
Publication Order Number:
NBSG11/D
NBSG11
2.5V/3.3V SiGe 1:2
Differential Clock Driver
with RSECL* Outputs
*Reduced Swing ECL
The NBSG11 is a 1-to-2 differential fanout buffer, optimized for
low skew and ultra-low JITTER.
Inputs incorporate internal 50
W termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS,
LVTTL, or LVDS. Outputs are RSECL (Reduced Swing ECL),
400 mV.
Maximum Input Clock Frequency
up to
12 GHz Typical
Maximum Input Data Rate
up to
12 Gb/s Typical
30 ps Typical Rise and Fall Times
125 ps Typical Propagation Delay
RSPECL Output with Operating Range: V
CC
= 2.375 V to 3.465 V
with V
EE
= 0 V
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= -2.375 V to -3.465 V
RSECL Output Level (400 mV Peak-to-Peak Output), Differential
Output Only
50
W Internal Input Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
*For further details, refer to Application Note
AND8002/D
FCBGA-16
BA SUFFIX
CASE 489
MARKING
DIAGRAM*
SG
11
Device
Package
Shipping
ORDERING INFORMATION
NBSG11BA
4x4 mm
FCBGA-16
100 Units / Tray
NBSG11BAR2
4x4 mm
FCBGA-16
500 / Tape & Reel
LYW
Board
Description
NBSG11BAEVB
NBSG11BA Evaluation Board
http://onsemi.com
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
SG11
ALYW
QFN-16
MN SUFFIX
CASE 485G
NBSG11MN
3x3 mm
QFN-16
123 Units / Rail
NBSG11MNR2
3x3 mm
QFN-16
3000 / Tape & Reel
NBSG11
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2
Figure 1. BGA-16 Pinout (Top View)
VTCLK
CLK
CLK
V
EE
VTCLK
NC
V
EE
NC
NC
Q1
V
CC
V
CC
NC
Q0
Q0
Q1
A
B
C
D
1
2
3
4
V
EE
NC
NC
V
CC
V
EE
NC
NC
V
CC
Q0
Q0
Q1
Q1
VTCLK
CLK
CLK
VTCLK
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG11
Exposed Pad (EP)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
Description
D1
1
VTCLK
-
Internal 50
W
Termination Pin. See Table 2.
C1
2
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 k
W
to V
EE
and 36.5 k
W
to V
CC
.
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 k
W
to V
EE
.
A1
4
VTCLK
-
Internal 50
W
Termination Pin. See Table 2.
B2,C2
5,16
V
EE
-
Negative Supply Voltage
A2,A3,D2,
D3
6,7,14,15
NC
-
No Connect
B3,C3
8,13
V
CC
-
Positive Supply Voltage
A4
9
Q1
RSECL Output
Inverted Differential Output 1. Typically Terminated with 50
W
to
V
TT
= V
CC
- 2 V
B4
10
Q1
RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50
W
to
V
TT
= V
CC
- 2 V
C4
11
Q0
RSECL Output
Inverted Differential output 0. Typically Terminated with 50
W
to
V
TT
= V
CC
- 2 V
D4
12
Q0
RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50
W
to
V
TT
= V
CC
- 2 V
N/A
-
EP
-
Exposed Pad (Note 2)
1. The NC pins are electrically connected to the die and must be left open.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat-sinking conduit.
3. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, and
if no signal is applied then the device will be susceptible to self-oscillation.
NBSG11
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3
50
W
50
W
VTCLK
CLK
CLK
VTCLK
V
EE
V
CC
Figure 3. Logic Diagram
75 K
W
75 K
W
36.5 K
W
Q1
Q1
Q0
Q0
Table 2. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK and VTCLK to V
CC
LVDS
Connect VTCLK and VTCLK together
AC-COUPLED
Bias VTCLK and VTCLK Inputs within
(VIHCMR) Common Mode Range
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An external voltage should be be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V
CC
/2
for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor (CLK, CLK)
75 k
W
Internal Input Pullup Resistor (CLK)
36.5 k
W
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 100 V
Moisture Sensitivity (Note 4)
FCBGA-16
QFN-16
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
125
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional information, see Application Note AND8003/D.
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4
Table 4. MAXIMUM RATINGS
(Note 5)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
CC
Positive Power Supply
V
EE
= 0 V
3.6
V
V
EE
Negative Power Supply
V
CC
= 0 V
-3.6
V
V
I
Positive Input
Negative Input
V
EE
= 0 V
V
CC
= 0 V
V
I
V
CC
V
I
V
EE
3.6
-3.6
V
V
V
INPP
Differential Input Voltage
|D - D|
V
CC
- V
EE
w
2.8 V
V
CC
- V
EE
<
2.8 V
2.8
|V
CC
- V
EE
|
V
V
I
out
Output Current
Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range
16 FCBGA
16 QFN
-40 to +70
-40 to +85
C
T
stg
Storage Temperature Range
-65 to +150
C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 6)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
C/W
C/W
C/W
C/W
q
JC
Thermal Resistance (Junction-to-Case)
1S2P (Note 6)
2S2P (Note 7)
16 FCBGA
16 QFN
5.0
4.0
C/W
C/W
T
sol
Wave Solder
< 15 Seconds
225
C
5. Maximum Ratings are those values beyond which device damage may occur.
6. JEDEC standard multilayer board - 1S2P (1 signal, 2 power).
7. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 8)
-40
C
25
C
70
C(BGA)/85
C(QFN)**
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
45
60
75
45
60
75
45
60
75
mA
V
OH
Output HIGH Voltage (Note 9)
1450
1530
1575
1525
1565
1600
1550
1590
1625
mV
V
OUTPP
Output Amplitude Voltage
350
410
525
350
410
525
350
410
525
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Note 11)
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
V
IL
Input LOW Voltage (Single-Ended)
(Note 12)
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150 mV
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150
mV
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150
mV
V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
1.2
2.5
1.2
2.5
1.2
2.5
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@ V
IH
, V
IHMAX
)
80
150
80
150
80
150
m
A
I
IL
Input LOW Current (@ V
IL
, V
ILMIN
)
25
100
25
100
25
100
m
A
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
8. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to -0.965 V.
9. All loading with 50
W
to V
CC
- 2.0 V. V
OH
/V
OL
measured at V
IH
/V
IL
.
10. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
11. V
IH
cannot exceed V
CC
.
12. V
IL
always
V
EE
.
*Typicals used for testing purposes.
**The device packaged in FCBGA-16 have maximum temperature specification of 70
C and devices packaged in QFN-16 have maximum
temperature specification of 85
C.
NBSG11
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5
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT
V
CC
= 3.3 V; V
EE
= 0 V (Note 13)
-40
C
25
C
70
C(BGA)/85
C(QFN)**
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
45
60
75
45
60
75
45
60
75
mA
V
OH
Output HIGH Voltage (Note 14)
2250
2330
2375
2325
2365
2400
2350
2390
2425
mV
V
OUTPP
Output Amplitude Voltage
350
410
525
350
410
525
350
410
525
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Note 16)
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
V
IL
Input LOW Voltage (Single-Ended)
(Note 17)
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150
mV
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150
mV
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150
mV
V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Note 15)
(Differential Configuration)
1.2
3.3
1.2
3.3
1.2
3.3
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@ V
IH
, V
IHMAX
)
80
150
80
150
80
150
m
A
I
IL
Input LOW Current (@ V
IL
, V
ILMIN
)
25
100
25
100
25
100
m
A
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
13. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to -0.165 V.
14. All loading with 50
W
to V
CC
- 2.0 V. V
OH
/V
OL
measured at V
IH
/V
IL
.
15. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
16. V
IH
cannot exceed V
CC
.
17. V
IL
always
V
EE
.
*Typicals used for testing purposes.
**The device packaged in FCBGA-16 have maximum temperature specification of 70
C and devices packaged in QFN-16 have maximum
temperature specification of 85
C.
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6
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V (Note 18)
-40
C
25
C
70
C(BGA)/85
C(QFN)**
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
45
60
75
45
60
75
45
60
75
mA
VOH
Output HIGH Voltage (Note 19)
-1050
-970
-925
-975
-935
-900
-950
-910
-875
mV
V
OUTPP
Output Amplitude Voltage
350
410
525
350
410
525
350
410
525
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Note 21)
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
CC
-
1435
mV
V
CC
-
1000
mV*
V
CC
V
V
IL
Input LOW Voltage (Single-Ended) (Note 22)
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150
mV
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150
mV
V
IH
-
2.5 V
V
CC
-
1400
mV*
V
IH
-
150
mV
V
V
IHCMR
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 20)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@ V
IH
, V
IHMAX
)
80
150
80
150
80
150
m
A
I
IL
Input LOW Current (@ V
IL
, V
ILMIN
)
25
100
25
100
25
100
m
A
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
18. Input and output parameters vary 1:1 with V
CC
.
19. All loading with 50
W
to V
CC
- 2.0 V. V
OH
/V
OL
measured at V
IH
/V
IL
.
20. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
21. V
IH
cannot exceed V
CC
.
22. V
IL
always
V
EE
.
*Typicals used for testing purposes.
**The device packaged in FCBGA-16 have maximum temperature specification of 70
C and devices packaged in QFN-16 have maximum
temperature specification of 85
C.
Table 8. AC CHARACTERISTICS for FCBGA-16
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
-40
C
25
C
70
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figure 4. F
max
/JITTER) (Note 23)
10.709
12
10.709
12
10.709
12
GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
t
SKEW
Duty Cycle Skew (Note 24)
Within-Device Skew (Note 25)
Device-to-Device Skew (Note 26)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
ps
t
JITTER
RMS Random Clock Jitter
f
in
< 10 GHz
Peak-to-Peak Data Dependent Jitter
f
in
< 10 Gb/s
0.2
TBD
1
0.2
TBD
1
0.2
TBD
1
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times
Q, Q
(20% - 80%) @ 1 GHz
20
30
55
20
30
55
20
30
55
ps
23. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50
W
to V
CC
-2.0 V. For minimum f
max
value of 10.709 GHz,
output amplitude is approximately 200 mV (as shown in Figure 4, where output P-P spec is shown as a minimum/guarantee of around
150 mV). Input edge rates 40 ps (20% - 80%).
24. See Figure 5. t
SKEW
= |t
PLH
- t
PHL
| for a nominal 50% Differential Clock Input Waveform.
25. Within-Device skew is defined as identical transitions on similar paths through a device.
26. Device-to-device skew for identical transitions at identical V
CC
levels.
27. V
INPP
(MAX) cannot exceed V
CC
- V
EE
.
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7
Table 9. AC CHARACTERISTICS for QFN-16
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
-40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figure 4. F
max
/JITTER) (Note 28)
10.5
12
10.5
12
10.5
12
GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
t
SKEW
Duty Cycle Skew (Note 29)
Within-Device Skew (Note 30)
Device-to-Device Skew (Note 31)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
ps
t
JITTER
RMS Random Clock Jitter
f
in
< 10 GHz
Peak-to-Peak Data Dependent Jitter
f
in
< 10 Gb/s
0.2
TBD
1
0.2
TBD
1
0.2
TBD
1
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 32)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times
Q, Q
(20% - 80%) @ 1 GHz
15
30
55
20
30
55
20
30
55
ps
28. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50
W
to V
CC
-2.0 V. For minimum f
max
value of 10.5 GHz,
output amplitude is approximately 200 mV (as shown in Figure 4, where output P-P spec is shown as a minimum/guarantee of around
150 mV). Input edge rates 40 ps (20% - 80%).
29. See Figure 5. t
SKEW
= |t
PLH
- t
PHL
| for a nominal 50% Differential Clock Input Waveform.
30. Within-Device skew is defined as identical transitions on similar paths through a device.
31. Device-to-device skew for identical transitions at identical V
CC
levels.
32. V
INPP
(MAX) cannot exceed V
CC
- V
EE
.
SSS
SSS
SSS
SSS
0
100
200
300
400
500
600
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
-0.5
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
Figure 4. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) at Ambient Temperature (Typical)
OUTPUT VOL
T
AGE AMPLITUDE
(mV)
JITTERout ps (RMS)
OUTPUT AMP.
OUTPUT P-P SPEC
RMS JITTER
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8
t
PHL
Figure 5. AC Reference Measurement
CLK
CLK
Q
Q
t
PLH
V
INPP
= V
IH
(CLK) - V
IL
(CLK)
V
OUTPP
= V
OH
(Q) - V
OL
(Q)
Receiver
Device
Driver
Device
Q
Q
D
D
50
W
50
W
V
TT
Figure 6. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices)
V
TT
= V
CC
- 2.0 V
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9
PACKAGE DIMENSIONS
FCBGA-16
BA SUFFIX
PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE
CASE 489-01
ISSUE O
0.20
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
D
E
M
A1
A2
A
0.10 Z
0.15 Z
ROTATED 90 CLOCKWISE
DETAIL K
_
5
VIEW M-M
e
3 X
S
M
X
0.15
Y
Z
0.08
Z
3
b
16 X
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
4
3
2
1
A
B
C
D
4
16 X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
DIM
MIN
MAX
MILLIMETERS
A
1.40 MAX
A1
0.25
0.35
A2
1.20 REF
b
0.30
0.50
D
4.00 BSC
E
4.00 BSC
e
1.00 BSC
S
0.50 BSC
K
-X-
-Y-
M
M
-Z-
NBSG11
http://onsemi.com
10
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE O
X
M
0.10 (0.004)
T
-T-
-X-
NOTE 3
SEATING
PLANE
L
A
M
-Y-
B
N
0.25 (0.010) T
0.25 (0.010) T
J
C
K
R
0.08 (0.003) T
G
E
H
F
P
D
Y
1
4
5
8
12
9
16
13
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
3.00 BSC
0.118 BSC
B
3.00 BSC
0.118 BSC
C
0.80
1.00
0.031
0.039
D
0.23
0.28
0.009
0.011
G
0.50 BSC
0.020 BSC
H
0.875
0.925
0.034
0.036
J
0.20 REF
0.008 REF
K
0.00
0.05
0.000
0.002
L
0.35
0.45
0.014
0.018
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
E
1.75
1.85
0.069
0.073
F
1.75
1.85
0.069
0.073
M
1.50 BSC
0.059 BSC
N
1.50 BSC
0.059 BSC
P
0.875
0.925
0.034
0.036
R
0.60
0.80
0.024
0.031
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