Semiconductor Components Industries, LLC, 2004

April, 2004 - Rev. 3

Publication Order Number:

NBSG16M/D

NBSG16M

2.5V/3.3V Multilevel Input

to CML Clock/Data

Receiver/Driver/Translator

Buffer

The NBSG16M is a differential current mode logic (CML)

receiver/driver/translator buffer. The device is functionally equivalent
to the EP16, LVEP16, or SG16 devices with CML output structure and
lower EMI capabilities.

Inputs incorporate internal 50

W termination resistors and accept

LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL,
LVCMOS, CML, or LVDS. The CML output structure contains
internal 50

W source termination resistor to V

. The device

generates 400 mV output amplitude with 50

W receiver resistor to

The V

pin is internally generated voltage supply available to this

device only. For all single-ended input conditions, the unused
complementary differential input is connected to V

as a switching

reference voltage. V

may also rebias AC coupled inputs. When

used, decouple V

via a 0.01

mF capacitor and limit current sourcing

or sinking to 0.5 mA. When not used, V

output should be left open.

Maximum Input Clock Frequency > 10 GHz Typical

Maximum Input Data Rate > 10 Gb/s Typical

120 ps Typical Propagation Delay

35 ps Typical Rise and Fall Times

Positive CML Output with Operating Range: V

= 2.375 V to

3.465 V with V

= 0 V

Negative CML Output with RSNECL or NECL Inputs with

Operating Range: V

= 0 V with V

= -2.375 V to -3.465 V

CML Output Level; 400 mV Peak-to-Peak Output with

W Receiver Resistor to V

W Internal Input and Output Termination Resistors

Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL

and SG Devices

Reference Voltage Output

*For additional marking information, refer to

Application Note AND8002/D.

MARKING

DIAGRAM*

Device

Package

Shipping

ORDERING INFORMATION

http://onsemi.com

= Assembly Location

= Wafer Lot

= Year

= Work Week

16M

ALYW

QFN-16

MN SUFFIX

CASE 485G

NBSG16MMN

3x3 mm

QFN-16

123 Units / Rail

NBSG16MMNR2

3x3 mm

QFN-16

3000/Tape & Reel

For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

NBSG16M

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VTD

NBSG16M

Exposed Pad (EP)

Figure 1. QFN-16 Pinout (Top View)

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Description

ÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

Internal 50

Termination Pin. See Table 2. (Note 3)

LVDS, CML, ECL, LVTTL,

LVCMOS Input

Inverted Differential Input (Note 3)

LVDS, CML, ECL, LVTTL,

LVCMOS Input

Noninverted Differential Input. (Note 3)

Internal 50

Termination Pin. See Table 2. (Note 3)

Positive Supply Voltage. All V

pins must be externally connected to Power Supply to guar-

antee proper operation.

No Connect (Note 1)

Negative Supply Voltage. All V

pins must be externally connected to Power Supply to guar-

antee proper operation.

Negative Supply Voltage. All V

pins must be externally connected to Power Supply to guar-

antee proper operation.

Positive Supply Voltage. All V

pins must be externally connected to Power Supply to guar-

antee proper operation.

CML Output

Noninverted CML Differential Output with Internal 50

Source Termination Resistor. (Note 2)

CML Output

Inverted CML Differential Output with Internal 50

Source Termination Resistor. (Note 2)

Positive Supply Voltage. All V

pins must be externally connected to Power Supply to guar-

antee proper operation.

Negative Supply Voltage. All V

pins must be externally connected to Power Supply to guar-

antee proper operation.

Negative Supply Voltage. All V

pins must be externally connected to Power Supply to guar-

antee proper operation.

Internally Generated ECL Reference Output Voltage

Positive Supply Voltage. All V

pins must be externally connected to Power Supply to guar-

antee proper operation.

Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must
be attached to a heat-sinking conduit.

1. The NC pins are electrically connected to the die and MUST be left open.
2. CML outputs require 50

receiver termination resistor to V

for proper operation.

3. In the differential configuration when the input termination pin (V

, V

) are connected to a common termination voltage, and if no signal

is applied then the device will be susceptible to self-oscillation.

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VTD

Figure 2. Logic Diagram

16 mA

Figure 3. CML Output Structure

Table 2. Interfacing Options

INTERFACING OPTIONS

CONNECTIONS

CML

Connect VTD and VTD to V

LVDS

Connect VTD and VTD together

AC-COUPLED

Bias VTD and VTD Inputs within (V

IHCMR

)

Common Mode Range

RSECL, PECL, NECL

Standard ECL Termination Techniques

LVTTL, LVCMOS

An external voltage should be applied to the

unused complimentary differential input.

Nominal voltage 1.5 V for LVTTL and V

/2 for

LVCMOS inputs.

Table 3. ATTRIBUTES

Characteristics

Value

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 1 kV

> 100 V

> 4 kV

Moisture Sensitivity (Note 4)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V-0 @ 0.125 in

Transistor Count

145

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.

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Table 4. MAXIMUM RATINGS

Symbol

Parameter

Condition 1

Condition 2

Rating

Unit

Positive Power Supply

= 0 V

3.6

Negative Power Supply

= 0 V

-3.6

Positive Input
Negative Input

= 0 V

3.6

-3.6

V
V

INPP

Differential Input Voltage |D - D|

- V

2.8 V

- V

< 2.8 V

2.8

- V

Input Current Through R

(50

Resistor)

Static
Surge

45
80

mA
mA

out

Output Current

Continuous
Surge

25
50

mA
mA

Sink/Source

1.0

Operating Temperature Range

-40 to +85

stg

Storage Temperature Range

-65 to +150

Thermal Resistance (Junction-to-Ambient)
(Note 5)

0 lfpm
500 lfpm

QFN-16
QFN-16

42
35

C/W

Thermal Resistance (Junction-to-Case)

1S2P (Note 5)

QFN-16

4.0

C/W

sol

Wave Solder

< 15 sec.

225

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not im-
plied, damage may occur and reliability may be affected.
5. JEDEC standard multilayer board - 1S2P (1 signal, 2 power)

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Table 5. DC CHARACTERISTICS, POSITIVE CML OUTPUT

= 2.5 V; V

= 0 V (Note 6)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Positive Power Supply Current

Output HIGH Voltage (Note 7)

Output LOW Voltage (Note 6)

400

330

400

330

400

330

Input HIGH Voltage
(Single-Ended) (Note 8)

1.275

1.0*

1.275

1.0*

1..275

1.0*

Input LOW Voltage
(Single-Ended) (Note 8)

1.4*

0.150

1.4*

0.150

1.4*

0.150

ECL Reference Voltage Output

1075

1170

1265

1075

1170

1265

1075

1170

1265

IHCMR

Input HIGH Voltage Common Mode
Range (Note 8)
(Differential Configuration)

1.2

2.5

1.2

2.5

1.2

2.5

TIN

Internal Input Termination Resistor

TOUT

Internal Output Termination
Resistor

Input HIGH Current (@ V

)

100

Input LOW Current (@ V

)

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.

6. Input and output parameters vary 1:1 with V

. V

can vary +0.125 V to -0.965 V.

7. All loading with 50

to V

8. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differen-

tial input signal.

*Typicals used for testing purposes.

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Table 6. DC CHARACTERISTICS, POSITIVE CML OUTPUT

= 3.3 V; V

= 0 V (Note 9)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Positive Power Supply Current

Output HIGH Voltage (Note 10)

Output LOW Voltage (Note 9)

400

330

400

330

400

330

Input HIGH Voltage
(Single-Ended) (Note 11)

1.275

1.0*

1.275

1.0*

1.275

1.0*

Input LOW Voltage
(Single-Ended) (Note 11)

1.4*

0.150

1.4*

0.150

1.4*

0.150

ECL Reference Voltage Output

1875

1970

2065

1875

1970

2065

1875

1970

2065

IHCMR

Input HIGH Voltage Common
Mode Range (Note 11)
(Differential Configuration)

1.2

3.3

1.2

3.3

1.2

3.3

TIN

Internal Input Termination Resistor

TOUT

Internal Output Termination
Resistor

Input HIGH Current (@ V

)

100

Input LOW Current (@ V

)

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

9. Input and output parameters vary 1:1 with V

. V

can vary +0.925 V to -0.165 V.

10. All loading with 50

to V

11. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differen-

tial input signal.

*Typicals used for testing purposes.

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Table 7. DC CHARACTERISTICS, NEGATIVE CML OUTPUT

= 0 V; V

= -3.465 to -2.375 V (Note 12)

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

Positive Power Supply Current

Output HIGH Voltage (Note 13)

Output LOW Voltage (Note 12)

400

330

400

330

400

330

Input HIGH Voltage
(Single-Ended) (Note 13)

1.275

1.0*

1.275

1.0*

1.275

1.0*

Input LOW Voltage
(Single-Ended) (Note 13)

1.4*

0.150

1.4*

0.150

1.4*

0.150

ECL Reference Voltage Output

-1425

-1330

-1235

-1425

-1330

-1235

-1425

-1330

-1235

IHCMR

Input HIGH Voltage Common
Mode Range (Note 14)
(Differential Configuration)

+1.2

TIN

Internal Input Termination Resistor

TOUT

Internal Output Termination
Resistor

Input HIGH Current (@ V

)

100

Input LOW Current (@ V

)

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

12. Input and output parameters vary 1:1 with V

13. All loading with 50

to V

14. V

IHCMR

min varies 1:1 with V

, V

IHCMR

max varies 1:1 with V

. The V

IHCMR

range is referenced to the most positive side of the differen-

tial input signal.

*Typicals used for testing purposes.

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Table 8. AC CHARACTERISTICS

= 0 V; V

= -3.465 V to -2.375 V or V

= 2.375 V to 3.465 V; V

= 0 V

-40

Symbol

Characteristic

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

OUTPP

Output Voltage Amplitude

< 7 GHz

(See Figure 4) (Note 15)

< 10 GHz

300
200

400
250

300
200

400
250

300
100

400
150

PLH

PHL

Propagation Delay to
Output Differential

110

150

100

120

150

100

125

155

SKEW

Duty Cycle Skew (Note 16)

JITTER

RMS Random Clock Jitter (Note 18)

< 10 GHz

Peak-to-Peak Data Dependent Jitter (Note 19)

< 10 Gb/s

0.2

1.0

INPP

Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 17)

2500

Output Rise/Fall Times @ 1 GHz

Q, Q

(20% - 80%)

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

15. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50

to V

. Input edge rates 40 ps (20% - 80%).

16. See Figure 5 t

skew

= |t

PLH

- t

PHL

| for a nominal 50% differential clock input waveform.

17. V

INPP(max)

cannot exceed V

- V

. (Applicable only when V

- V

< 2500 mV). Input voltage swing is a single-ended measurement

operating in differential mode.

18. Additive RMS jitter with 50% duty cycle clock signal at 10GHz.
19. Additive Peak-to-Peak data dependent jitter with NRZ PRBS2

-1 data rate at 10 Gb/s.

Figure 4. Output Voltage Amplitude (V

OUTPP

) versus

Input Clock Frequency (f

) at Ambient Temperature (Typical)

100

150

200

250

300

350

400

450

500

FREQUENCY (GHz)

OUTPUT

VOL

AGE

AMPLITUDE (mV)

- V

= 3.3 V

- V

= 2.5 V

NBSG16M

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Application Information

All inputs can accept PECL, CML, and LVDS signal

levels. The input voltage can range from V

to 1.2 V.

Examples interfaces are illustrated below in a 50

environment (Z = 50

W).

SG16M

Figure 7. CML to CML Interface

Figure 8. LVDS to CML Receiver Interface

LVDS

Driver

SG16M

Figure 9. PECL to CML Receiver Interface

PECL
Driver

SG16M

Bias

5.0 V 290

3.3 V 150

2.5 V

Recommended R

Values

Bias

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PACKAGE DIMENSIONS

QFN-16

MN SUFFIX

CASE 485G-01

ISSUE A

0.10 (0.004)

-T-

-X-

NOTE 3

SEATING

PLANE

-Y-

0.25 (0.010) T

0.08 (0.003) T

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

3.00 BSC

0.118 BSC

3.00 BSC

0.118 BSC

0.80

1.00

0.031

0.039

0.23

0.28

0.009

0.011

0.50 BSC

0.020 BSC

0.875

0.925

0.034

0.036

0.20 REF

0.008 REF

0.00

0.05

0.000

0.002

0.35

0.45

0.014

0.018

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

1.75

1.85

0.069

0.073

1.75

1.85

0.069

0.073

1.50 BSC

0.059 BSC

1.50 BSC

0.059 BSC

0.875

0.925

0.034

0.036

0.60

0.80

0.024

0.031

inches

SCALE 10:1

0.50
0.02

0.575
0.022

1.50

0.059

3.25

0.128

QFN-16, 3x3 mm,

EP 2x2 mm

0.30

0.012

3.25

0.128

0.30

0.012

SOLDERING FOOTPRINT

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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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Phone: 81-3-5773-3850

NBSG16M/D

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