Semiconductor Components Industries, LLC, 2004
March, 2004 - Rev. 5
1
Publication Order Number:
NBSG53A/D
NBSG53A
2.5V/3.3V SiGe Selectable
Differential Clock and Data
D Flip-Flop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi-function differential D flip-flop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaComm
TM
family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16-pin
Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS, reset, and select
inputs. Differential inputs incorporate internal 50
W termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to
program the peak-to-peak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single-ended and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 4, 6, 8, 10, and 11)
Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
(See Figures 5, 7, 9, 10, and 11)
210 ps Typical Propagation Delay (OLS = FLOAT)
45 ps Typical Rise and Fall Times (OLS = FLOAT)
DIV/2 Mode (Active with Select Low)
DFF Mode (Active with Select High)
Selectable Swing PECL Output with Operating Range: V
CC
= 2.375 V
to 3.465 V with V
EE
= 0 V
Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= -2.375 V to -3.465 V
Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak-to-Peak Output)
50
W Internal Input Termination Resistors on all Differential Inputs
*Output Level Select
**For further details, refer to Application
Note AND8002/D
FCBGA-16
BA SUFFIX
CASE 489
MARKING
DIAGRAM**
SG
53A
LYW
Board
Description
NBSG53ABAEVB
NBSG53ABA Evaluation Board
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A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
SG53A
ALYW
QFN-16
MN SUFFIX
CASE 485G
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
ORDERING INFORMATION
NBSG53A
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2
VTD
CLK
CLK
VTCLK
V
CC
R
VTCLK
D
D
VTD
V
CC
V
EE
SEL
OLS
Q
Q
A
B
C
D
1
2
3
4
Figure 1. BGA-16 Pinout (Top View)
VTD
D
D
VTD
V
CC
R
SEL OLS
V
EE
Q
Q
V
CC
VTCLK
CLK
CLK
VTCLK
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG53A
Exposed Pad
(EP)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
Description
C2
1
VTCLK
-
Internal 50
W
Termination Pin. See Table 4.
C1
2
CLK
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input.
B1
3
CLK
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input.
B2
4
VTCLK
-
Internal 50
W
Termination Pin. See Table 4.
A1
5
VTD
-
Internal 50
W
termination pin. See Table 4.
A2
6
D
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Inverted Differential Input.
A3
7
D
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Noninverted Differential Input.
A4
8
VTD
-
Internal 50
W
Termination Pin. See Table 4.
D1,B3
9,16
V
CC
-
Positive Supply Voltage
B4
10
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50
W
Resistor to
V
TT
= V
CC
- 2 V.
C4
11
Q
RSECL Output
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to
V
TT
= V
CC
- 2 V.
C3
12
V
EE
-
Negative Supply Voltage
D4
13
OLS*
Input
Input Pin for the Output Level Select (OLS). See Table 2.
D3
14
SEL
LVECL,
LVCMOS,
LVTTL Input
Select Logic Input. Internal 75 k
W
to V
EE
.
D2
15
R
LVECL,
LVCMOS,
LVTTL Input
Reset D Flip-Flop. Internal 75 k
W
to V
EE
.
N/A
-
EP
Exposed Pad. (Note 1)
1. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heat-sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination volt-
age, and if no signal is applied then the device will be susceptible to self-oscillation.
3. When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, 2K
W
resistor should be connected from OLS pin to V
EE
.
NBSG53A
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3
Figure 3. Simplified Logic Diagram
D
D
SEL
CLK
CLK
VTD
V
CC
Q
Q
Flip-Flop
(DIV/2)
Flip-Flop
(DFF)
R
D
D
VTD
OLS
R
Q
Q
V
EE
VTCLK
VTCLK
R
75 k
W
75 k
W
50
W
50
W
50
W
50
W
0
1
2
2
2
2
2
2
2
Table 2. OUTPUT LEVEL SELECT (OLS)
OLS
Q/Q VPP
OLS Sensitivity
V
CC
800 mV
OLS - 75 mV
V
CC
- 0.4 V
200 mV
OLS
$
150 mV
V
CC
- 0.8 V
600 mV
OLS
$
100 mV
V
CC
- 1.2 V
0
OLS
$
75 mV
V
EE
(Note 4)
400 mV
OLS + 100 mV
Float
600 mV
N/A
4. When an output level of 400 mV is desired and
V
CC
- V
EE
> 3.0 V, 2.0 k
W
resistor should be connected from
OLS to V
EE
.
Table 3. TRUTH TABLE
R
SEL
D
CLK
Q
Function
H
x
x
x
L
Reset
L
H
L
Z
L
DFF
L
H
H
Z
H
DFF
L
L
x
Z
Q
DIV/2
Z = LOW to HIGH Transition
Table 4. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTCLK, VTD and VTCLK, VTD to V
CC
LVDS
Connect VTCLK, VTD and VTCLK, VTD Together
AC-COUPLED
Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (V
IHCMR
)
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An External Voltage (V
THR
) should be Applied to the Unused Complementary Differential Input. Nominal
V
THR
is 1.5 V for LVTTL and V
CC
/2 for LVCMOS Inputs. This Voltage must be within the V
THR
Specification.
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4
Table 5. ATTRIBUTES
Characteristics
Value
Positive Operating Voltage Range for V
CC
(V
EE
= 0 V)
2.375 V to 3.465 V
Negative Operating Voltage Range for V
EE
(V
CC
= 0 V)
-2.375 V to -3.465 V
Internal Input Pulldown Resistor (R, SEL)
75 k
W
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1.5 kV
> 50 V
> 4 kV
Moisture Sensitivity (Note 5)
16-FCBGA
16-QFN
Level 3
Level 1
Flammability Rating
UL 94 V-0 @ 0.125 in
Oxygen Index
28 to 34
Transistor Count
482
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
5. For additional information, refer to Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
CC
Positive Power Supply
V
EE
= 0 V
3.6
V
V
EE
Negative Power Supply
V
CC
= 0 V
-3.6
V
V
I
Positive Input
Negative Input
V
EE
= 0 V
V
CC
= 0 V
V
I
v
V
CC
V
I
w
V
EE
3.6
-3.6
V
V
V
INPP
Differential Input Voltage
|D - D|
V
CC
- V
EE
w
2.8 V
V
CC
- V
EE
<
2.8 V
2.8
|V
CC
- V
EE
|
V
V
I
IN
Input Current Through R
T
(50
W
Resistor)
Static
Surge
45
80
mA
mA
I
OUT
Output Current
Continuous
Surge
25
50
mA
mA
T
A
Operating Temperature Range
16 FCBGA
16 QFN
-40 to +70
-40 to +85
C
T
stg
Storage Temperature Range
-65 to +150
C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 6)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
C/W
C/W
C/W
C/W
q
JC
Thermal Resistance (Junction-to-Case)
2S2P (Note 6)
2S2P (Note 7)
16 FCBGA
16 QFN
5.0
4.0
C/W
C/W
T
sol
Wave Solder
< 15 Seconds
225
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
6. JEDEC standard 51-6, multilayer board - 2S2P (2 signal, 2 power).
7. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NBSG53A
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5
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 8)
-40
C
25
C
70
C(BGA)/85
C(QFN)**
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
33
45
57
33
45
57
33
45
57
mA
V
OH
Output HIGH Voltage (Note 9)
1460
1510
1560
1490
1540
1590
1515
1565
1615
mV
V
OL
Output LOW Voltage (Note 9)
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
555
1235
775
1455
1005
705
1295
895
1505
1095
855
1355
1015
1555
1185
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1390
1050
1590
1220
625
1295
840
1510
1065
775
1355
960
1560
1155
925
1415
1080
1610
1245
mV
V
OUTPP
Output Voltage Amplitude
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
715
125
525
0
325
805
215
615
5
415
705
120
520
0
320
795
210
610
0
410
700
120
515
0
320
790
210
605
5
410
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Notes 11 and 13)
CLK, CLK, D, D
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single-Ended)
(Notes 12 and 13)
CLK, CLK, D, D
V
EE
V
CC
-
1400*
V
IH
-
150
V
EE
V
CC
-
1400*
V
IH
-
150
V
EE
V
CC
-
1400*
V
IH
-
150
mV
V
IH
Input High Voltage (Single-Ended)
R, SEL
1290
V
CC
1355
V
CC
1415
V
CC
mV
V
IL
Input Low Voltage (Single-Ended)
R, SEL
V
EE
890
V
EE
955
V
EE
1015
mV
V
THR
Input Threshold Voltage (Single-Ended)
(Note 13)
V
EE
+
1125
V
CC
-
75
V
EE
+
1125
V
CC
-
75
V
EE
+
1125
V
CC
-
75
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
1.2
2.5
1.2
2.5
1.2
2.5
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@V
IH
)
R, SEL
CLK, CLK, D, D
35
5
100
50
35
5
100
50
35
5
100
50
m
A
I
IL
Input LOW Current (@V
IL
)
R, SEL
CLK, CLK, D, D
20
5
100
50
20
5
100
50
20
5
100
50
m
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to -0.965 V.
9. All outputs loaded with 50
W
to V
CC
- 2.0 V.
10. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
11. V
IH
cannot exceed V
CC
. |V
IH
- V
THR
| < 2600 mV.
12. V
IL
always
w
V
EE
. |V
IL
- V
THR
| < 2600 mV.
13. V
THR
is the voltage applied to one input when running in single-ended mode.
*Typicals used for testing purposes.
**The device packaged in FCBGA-16 have maximum ambient temperature specification of 70
C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85
C.
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6
Table 8. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT
V
CC
= 3.3 V; V
EE
= 0 V (Note 14)
-40
C
25
C
70
C(BGA)/85
C(QFN)***
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
35
47
59
35
47
59
35
47
59
mA
V
OH
Output HIGH Voltage (Note 15)
2260
2310
2360
2290
2340
2390
2315
2365
2415
mV
V
OL
Output LOW Voltage (Note 15)
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
**(OLS = V
EE
)
1320
2030
1550
2260
1785
1470
2090
1670
2310
1875
1620
2150
1790
2360
1965
1360
2065
1585
2290
1820
1510
2125
1705
2340
1910
1660
2185
1825
2390
2000
1390
2090
1615
2315
1850
1540
2150
1735
2365
1940
1690
2210
1855
2415
2030
mV
V
OUTPP
Output Amplitude Voltage
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
**(OLS = V
EE
)
750
130
550
0
345
840
220
640
0
435
740
125
545
0
340
830
215
635
0
430
735
125
540
0
335
825
215
630
0
425
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Notes 17 and 19)
CLK, CLK, D, D
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single-Ended)
(Notes 18 and 19)
CLK, CLK, D, D
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
mV
V
IH
Input High Voltage (Single-Ended)
R, SEL
2090
V
CC
2155
V
CC
2215
V
CC
mV
V
IL
Input Low Voltage (Single-Ended)
R, SEL
V
EE
1690
V
EE
1755
V
EE
1815
mV
V
THR
Input Threshold Voltage
(Single-Ended) (Note 19)
V
EE
+
1125
V
CC
-
75
V
EE
+
1125
V
CC
-
75
V
EE
+
1125
V
CC
-
75
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
1.2
3.3
1.2
3.3
1.2
3.3
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@V
IH
)
R, SEL
CLK, CLK, D, D
35
5
100
50
35
5
100
50
35
5
100
50
m
A
I
IL
Input LOW Current (@V
IL
)
R, SEL
CLK, CLK, D, D
20
5
100
50
20
5
100
50
20
5
100
50
m
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
14. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to -0.165 V.
15. All outputs loaded with 50
W
to V
CC
- 2.0 V.
16. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
17. V
IH
cannot exceed V
CC
. |V
IH
- V
THR
| < 2600 mV.
18. V
IL
always
w
V
EE
. |V
IL
- V
THR
| < 2600 mV.
19. V
THR
is the voltage applied to one input when running in single-ended mode.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70
C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85
C.
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Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V (Note 20)
-40
C
25
C
70
C(BGA)/85
C(QFN)***
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
35
47
59
35
47
59
35
47
59
mA
V
OH
Output HIGH Voltage (Note 21)
-1040
-990
-940
-1010
-960
-910
-985
-935
-885
mV
V
OL
Output LOW Voltage (Note 21)
-3.465 V
v
V
EE
v
-3.0 V
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS =FLOAT)
(OLS = V
CC
- 1.2 V)
**(OLS = V
EE
)
-3.0 V < V
EE
v
-2.375 V
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS =FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
-1980
-1270
-1750
-1040
-1515
-1945
-1265
-1725
-1045
-1495
-1830
-1210
-1630
-990
-1425
-1795
-1205
-1605
-995
-1405
-1680
-1150
-1510
-940
-1335
-1645
-1145
-1485
-945
-1315
-1940
-1235
-1715
-1010
-1480
-1905
-1230
-1690
-1010
-1460
-1790
-1175
-1595
-960
-1390
-1755
-1170
-1570
-960
-1370
-1640
-1115
-1475
-910
-1300
-1605
-1110
-1450
-910
-1280
-1910
-1210
-1685
-985
-1450
-1875
-1205
-1660
-990
-1435
-1760
-1150
-1565
-935
-1360
-1725
-1145
-1540
-940
-1345
-1610
-1090
-1445
-885
-1270
-1575
-1085
-1420
-890
-1255
mV
V
OUTPP
Output Voltage Amplitude
-3.465 V
v
V
EE
v
-3.0 V
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
**(OLS = V
EE
)
-3.0 V < V
EE
v
-2.375 V
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS =FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
750
130
550
0
345
715
125
525
0
325
840
220
640
0
435
805
215
615
5
415
740
125
545
0
340
705
120
520
0
320
830
215
635
0
430
795
210
610
0
410
735
125
540
0
335
700
120
515
0
320
825
215
630
0
425
790
210
605
5
410
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Notes 23 and 25) CLK, CLK, D, D
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single-Ended)
(Notes 24 and 25) CLK, CLK, D, D
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
mV
V
IH
Input High Voltage
(Single-Ended)
R, SEL
-1210
V
CC
-1145
V
CC
-1085
V
CC
mV
V
IL
Input Low Voltage (Single-Ended)
R, SEL
V
EE
-1610
V
EE
-1545
V
EE
-1485
mV
V
THR
Input Threshold Voltage
(Single-Ended) (Note 25)
V
EE
+
1125
V
CC
-
75
V
EE
+
1125
V
CC
-
75
V
EE
+
1125
V
CC
-
75
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
20. Input and output parameters vary 1:1 with V
CC
.
21. All outputs loaded with 50
W
to V
CC
- 2.0 V.
22. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
23. V
IH
cannot exceed V
CC
. |V
IH
- V
THR
| < 2600 mV.
24. V
IL
always
w
V
EE
. |V
IL
- V
THR
| < 2600 mV.
25. V
THR
is the voltage applied to one input when running in single-ended mode.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70
C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85
C.
NBSG53A
http://onsemi.com
8
Table 9. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V (Note 20) (continued)
Symbol
Unit
70
C(BGA)/85
C(QFN)***
25
C
-40
C
Characteristic
Symbol
Unit
Max
Typ
Min
Max
Typ
Min
Max
Typ
Min
Characteristic
V
IHCMR
Input HIGH Voltage Common
Mode Range
(Differential Configuration)
(Note 22)
V
EE
+ 1.2
0.0
V
EE
+ 1.2
0.0
V
EE
+ 1.2
0.0
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@V
IH
)
R, SEL
CLK, CLK, D, D
35
5
100
50
35
5
100
50
35
5
100
50
m
A
I
IL
Input LOW Current (@V
IL
)
R, SEL
CLK, CLK, D, D
20
5
100
50
20
5
100
50
20
5
100
50
m
A
I
OLS
OLS Input Current (See Figure
12)
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS =
FLOAT)
(OLS = V
CC
- 1.2 V)
-3.465 V
v
V
EE
v
-3.0 V
*(OLS = V
EE
)
-3.0 V < V
EE
v
-2.375 V
(OLS = V
EE
)
-300
-1500
-1000
300
100
5
-100
-600
-400
900
300
100
-300
-1500
-1000
300
100
5
-100
-600
-400
900
300
100
-300
-1500
-1000
300
100
5
-100
-600
-400
900
300
100
m
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
20. Input and output parameters vary 1:1 with V
CC
.
21. All outputs loaded with 50
W
to V
CC
- 2.0 V.
22. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
23. V
IH
cannot exceed V
CC
. |V
IH
- V
THR
| < 2600 mV.
24. V
IL
always
w
V
EE
. |V
IL
- V
THR
| < 2600 mV.
25. V
THR
is the voltage applied to one input when running in single-ended mode.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70
C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85
C.
NBSG53A
http://onsemi.com
9
Table 10. AC CHARACTERISTICS for FCBGA-16
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
-40
C
25
C
70
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figures 4, 6, 8, 10, and 11)
DFF
(See Figures 5, 7, 9, 10, and 11)
(Note 26)
DIV/2
8
10
8
10
8
10
GHz
t
PLH
,
t
PHL
Propagation Delay to Output Differential
CLK
Q, Q
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
**(OLS = V
EE
)
160
150
155
155
210
200
205
205
260
250
255
255
160
155
160
160
215
205
210
210
270
255
260
260
165
160
160
160
220
210
215
215
275
260
270
270
ps
SEL
Q, Q
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
**(OLS = V
EE
)
165
160
160
160
220
210
215
210
275
260
270
260
170
160
165
160
225
210
220
215
280
260
275
270
170
160
165
165
225
210
220
220
280
260
275
275
R
Q, Q
(OLS = V
CC
) DIV/2
(OLS = V
CC
) DFF
(OLS = V
CC
- 0.4 V) DIV/2
(OLS = V
CC
- 0.4 V) DFF
(OLS = V
CC
-0.8 V, OLS = FLOAT) DIV/2
(OLS = V
CC
- 0.8 V, OLS = FLOAT) DFF
**(OLS = V
EE
) DIV/2
**(OLS = V
EE
) DFF
220
200
215
195
220
200
215
195
295
270
285
260
290
265
285
260
370
340
355
325
360
330
355
325
225
205
220
200
220
200
220
200
300
275
290
265
295
270
290
265
375
345
360
330
370
340
360
330
225
205
220
200
220
200
220
200
300
275
290
265
295
270
290
265
375
345
360
330
370
340
360
330
t
SKEW
Duty Cycle Skew (Notes 27 and 29)
DFF
5
20
5
20
5
20
ps
t
JITTER
RMS Random Clock Jitter
f
in
v
8 GHz
(See Figures 4 and 6) (Note 26)
Peak-to-Peak Data Dependent Jitter
f
in
= 8 Gb/s
0.5
1.5
0.5
TBD
1.5
0.5
1.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times (20% - 80%)
@ 1 GHz
Q, Q
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
**(OLS = V
EE
)
30
20
25
25
50
40
45
45
65
60
65
65
30
20
25
25
50
40
45
45
65
60
65
65
30
20
25
25
50
40
45
45
65
60
65
65
ps
t
s
Setup Time
D
CLK
30
14
30
10
30
13
ps
t
h
Hold Time
D
CLK
25
12
25
7
25
9
ps
t
rr
Reset Recovery
DFF, DIV/2
40
9
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50
W
to
V
CC
- 2.0 V. Input edge rates is 40 ps (20% - 80%).
27. See Figure 14. t
SKEW
= |t
PLH
- t
PHL
| for a nominal 50% differential clock input waveform.
28. V
INPP
(MAX) cannot exceed V
CC
- V
EE
(Applicable only when V
CC
- V
EE
< 2600 mV).
29. See Figure 10. Duty Cycle % vs. Frequency.
**When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
NBSG53A
http://onsemi.com
10
Table 11. AC CHARACTERISTICS for QFN-16
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
-40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figures 4, 6, 8, 10, and 11)
DFF
(See Figures 5, 7, 9, 10, and 11)
(Note 30)
DIV/2
8
10
8
10
8
10
GHz
t
PLH
,
t
PHL
Propagation Delay to Output Differential
(Note 34)
CLK
Q, Q
SEL
Q, Q
R
Q, Q D
IN
/2
DFF
150
160
215
195
215
190
280
270
285
280
375
345
150
160
215
195
215
190
280
270
285
280
375
345
150
160
215
195
215
190
280
270
285
280
375
345
ps
t
SKEW
Duty Cycle Skew (Notes 31 and 33) DFF
5
20
5
20
5
20
ps
t
JITTER
RMS Random Clock Jitter
f
in
v
8 GHz
(See Figures 4 and 6) (Note 30)
Peak-to-Peak Data Dependent Jitter
f
in
= 8 Gb/s
0.5
TBD
1
0.5
TBD
1
0.5
TBD
1
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 32)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times (20% - 80%)
@ 1 GHz
Q, Q
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
**(OLS = V
EE
)
28
15
25
20
40
40
35
35
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
28
15
25
20
40
40
35
35
65
65
65
65
ps
t
s
Setup Time
D
CLK
30
14
30
10
30
13
ps
t
h
Hold Time
D
CLK
25
12
25
7
25
0
ps
t
rr
Reset Recovery
DFF, DIV/2
40
9
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
30. Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50
W
to
V
CC
- 2.0 V. Input edge rates is 40 ps (20% - 80%).
31. See Figure 14. t
SKEW
= |t
PLH
- t
PHL
| for a nominal 50% differential clock input waveform.
32. V
INPP
(MAX) cannot exceed V
CC
- V
EE
(Applicable only when V
CC
- V
EE
< 2600 mV).
33. See Figure 10. Duty Cycle % vs. Frequency.
34. For all OLS Configuration.
**When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70
C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85
C.
NBSG53A
http://onsemi.com
11
Figure 4. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) for DFF Mode (V
CC
- V
EE
= 3.3 V @ 25
5
C; Repetitive 1010 Input Data Pattern)
RMS JITTER
INPUT FREQUENCY (GHz)
OUTPUT VOL
T
AGE AMPLITUDE
JITTER
OUT
ps (RMS)
0
100
200
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
9
10
11
12
0
1
2
3
4
5
6
7
8
9
OLS = V
CC
0
OLS = V
CC
- 0.4 V
*OLS = V
EE
OLS = V
CC
- 0.8 V, OLS = FLOAT
INPUT FREQUENCY (GHz)
OUTPUT VOL
T
AGE AMPLITUDE
0
100
200
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
9
10
11
12
OLS = V
CC
0
OLS = V
CC
- 0.4 V
*OLS = V
EE
OLS = V
CC
- 0.8 V, OLS = FLOAT
Figure 5. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) for DIV/2 Mode (V
CC
- V
EE
= 3.3 V @ 25
5
C)
*When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
NBSG53A
http://onsemi.com
12
Figure 6. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) for DFF Mode (V
CC
- V
EE
= 2.5 V @ 25
5
C; Repetitive 1010 Input Data Pattern)
RMS JITTER
INPUT FREQUENCY (GHz)
OUTPUT VOL
T
AGE AMPLITUDE
JITTER
OUT
ps (RMS)
0
100
200
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
9
10
11
12
0
1
2
3
4
5
6
7
8
9
OLS = V
CC
0
OLS = V
CC
- 0.4 V
*OLS = V
EE
OLS = V
CC
- 0.8 V, OLS = FLOAT
INPUT FREQUENCY (GHz)
OUTPUT VOL
T
AGE AMPLITUDE
0
100
200
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
9
10
11
12
OLS = V
CC
0
OLS = V
CC
- 0.4 V
OLS = V
EE
*OLS = V
CC
- 0.8 V, OLS = FLOAT
Figure 7. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) for DIV/2 Mode (V
CC
- V
EE
= 2.5 V @ 25
5
C)
*When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
NBSG53A
http://onsemi.com
13
INPUT FREQUENCY (GHz)
V
OH
/V
OL
(mV)
0
100
200
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
9
10
11
12
0
V
OH
(Q)
V
OH
(Q)
V
OL
(Q)
V
OL
(Q)
1000
1100
1200
INPUT FREQUENCY (GHz)
V
OH
/V
OL
(mV)
0
100
200
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
9
10
11
12
0
V
OH
(Q)
V
OH
(Q)
V
OL
(Q)
V
OL
(Q)
1000
1100
1200
Figure 8. V
OH
/V
OL
(Q/Q) vs. Input Frequency (f
in
) for DFF Mode
(V
CC
- V
EE
= 3.3 V @ 25
5
C and OLS = V
CC
- 0.8 V, OLS = FLOAT)
Figure 9. V
OH
/V
OL
(Q/Q) vs. Input Frequency (f
in
) for DIV/2 Mode
(V
CC
- V
EE
= 3.3 V @ 25
5
C and OLS = V
CC
- 0.8 V, OLS = FLOAT)
NBSG53A
http://onsemi.com
14
70
0
10
20
30
40
50
60
80
90
100
0
1
3
4
5
6
7
8
9
10
11
12
2
INPUT FREQUENCY (GHz)
DUTY CYCLE (%)
DFF Mode
DIV/2 Mode
70
0
10
20
30
40
50
60
80
90
100
0
1
3
4
5
6
7
8
9
10
11
12
2
INPUT FREQUENCY (GHz)
DUTY CYCLE (%)
DFF Mode
DIV/2 Mode
Figure 10. Duty Cycle % vs. Input Frequency (f
in
)
(V
CC
- V
EE
= 3.3 V @ 25
5
C)
Figure 11. Duty Cycle % vs. Input Frequency (f
in
)
(V
CC
- V
EE
= 2.5 V @ 70
5
C)
NBSG53A
http://onsemi.com
15
I
OLS
(
m
A)
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
Figure 12. Typical OLS Input Current vs. OLS Input Voltage
(V
CC
- V
EE
= 3.3 V @ 25
5
C)
V
OLS
(mV)
V
outpp
(mV)
0
200
400
600
800
1000
OLS (mV)
Figure 13. OLS Operating Area
V
EE
V
CC
V
CC
- 400
V
CC
- 800
V
CC
- 1200
V
EE
V
CC
V
CC
- 400
V
CC
- 800
V
CC
- 1200
V
CC
- 75
V
CC
- 250
V
CC
- 550
V
CC
- 700
V
CC
- 900
V
CC
- 1125
V
CC
- 1275
V
EE
+ 100
NBSG53A
http://onsemi.com
16
Figure 14. AC Reference Measurement
CLK
CLK
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(CLK) - V
IL
(CLK)
Figure 15. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020/D - Termination of ECL Logic Devices)
V
OUTPP
= V
OH
(Q) - V
OL
(Q)
Driver
Device
Receiver
Device
Q
D
Q
D
Z
o
= 50
W
Z
o
= 50
W
50
W
50
W
V
TT
V
TT
= V
CC
- 2.0 V
ORDERING INFORMATION
Device
Package Type
Shipping
NBSG53ABA
4x4 mm
FCBGA-16
100 Units / Tray
NBSG53ABAR2
4x4 mm
FCBGA-16
500 / Tape & Reel
NBSG53AMN
3x3 mm
QFN-16
123 Units / Rail
NBSG53AMNR2
3x3 mm
QFN-16
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifi-
cations Brochure, BRD8011/D.
NBSG53A
http://onsemi.com
17
PACKAGE DIMENSIONS
FCBGA-16
BA SUFFIX
PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE
CASE 489-01
ISSUE O
0.20
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
D
E
M
A1
A2
A
0.10 Z
0.15 Z
ROTATED 90 CLOCKWISE
DETAIL K
_
5
VIEW M-M
e
3 X
S
M
X
0.15
Y
Z
0.08
Z
3
b
16 X
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
4
3
2
1
A
B
C
D
4
16 X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
DIM
MIN
MAX
MILLIMETERS
A
1.40 MAX
A1
0.25
0.35
A2
1.20 REF
b
0.30
0.50
D
4.00 BSC
E
4.00 BSC
e
1.00 BSC
S
0.50 BSC
K
-X-
-Y-
M
M
-Z-
NBSG53A
http://onsemi.com
18
PACKAGE DIMENSIONS
QFN-16
MN SUFFIX
CASE 485G-01
ISSUE O
X
M
0.10 (0.004)
T
-T-
-X-
NOTE 3
SEATING
PLANE
L
A
M
-Y-
B
N
0.25 (0.010) T
0.25 (0.010) T
J
C
K
R
0.08 (0.003) T
G
E
H
F
P
D
Y
1
4
5
8
12
9
16
13
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
3.00 BSC
0.118 BSC
B
3.00 BSC
0.118 BSC
C
0.80
1.00
0.031
0.039
D
0.23
0.28
0.009
0.011
G
0.50 BSC
0.020 BSC
H
0.875
0.925
0.034
0.036
J
0.20 REF
0.008 REF
K
0.00
0.05
0.000
0.002
L
0.35
0.45
0.014
0.018
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
E
1.75
1.85
0.069
0.073
F
1.75
1.85
0.069
0.073
M
1.50 BSC
0.059 BSC
N
1.50 BSC
0.059 BSC
P
0.875
0.925
0.034
0.036
R
0.60
0.80
0.024
0.031
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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PUBLICATION ORDERING INFORMATION
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Phone: 81-3-5773-3850
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For additional information, please contact your local
Sales Representative.
NBSG53A/D
GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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