Semiconductor Components Industries, LLC, 2004
May, 2004 - Rev. 8
1
Publication Order Number:
NBSG86A/D
NBSG86A
2.5V/3.3V SiGe Differential
Smart Gate with Output
Level Select
The NBSG86A is a multi-function differential Logic Gate which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaComm
TM
family of high
performance Silicon Germanium products. The device is housed in a
low profile 4x4 mm, 16-pin, flip-chip BGA or a 3x3 mm 16 pin QFN
package.
Differential inputs incorporate internal 50
W termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS input is used to
program the peak-to-peak output amplitude between 0 and 800 mV
in five discrete steps.
The NBSG86A employs input default circuitry so that under open
input conditions (D
x
, D
x
, VTD
x
, VTD
x,
VTSEL) the outputs of the
device will remain stable.
Maximum Input Clock Frequency > 8 GHz Typical
Maximum Input Data Rate > 8 Gb/s Typical
165 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
Selectable Swing PECL Output with Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= -2.375 V to -3.465 V
Selectable Output Level (0 V, 200 mV, 400 mV,
600 mV, or 800 mV Peak-to-Peak Output)
50
W Internal Input Termination Resistors
*For further details, refer to Application Note
AND8002/D
FCBGA-16
BA SUFFIX
CASE 489
MARKING
DIAGRAM*
SG
86A
Device
Package
Shipping
ORDERING INFORMATION
NBSG86ABA
4x4 mm
FCBGA-16
100 Units/Tray
NBSG86ABAR2
4x4 mm
FCBGA-16
500/
Tape & Reel
LYW
Board
Description
NBSG86ABAEVB NBSG86ABA Evaluation Board
http://onsemi.com
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
SG86A
ALYW
QFN-16
MN SUFFIX
CASE 485G
NBSG86AMN
3x3 mm
QFN-16
123 Units/Rail
NBSG86AMNR2
3x3 mm
QFN-16
3000/
Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
NBSG86A
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2
VTD1
SEL
SEL
OLS
VTD0
D0
VTSEL
D1
D1
VTD1
V
CC
V
EE
D0
VTD0
Q
Q
A
B
C
D
1
2
3
4
Figure 1. BGA-16 Pinout (Top View)
VTD1
D1
D1 VTD1
VTD0 D0
D0
VTD0
V
EE
Q
Q
V
CC
OLS
SEL
SEL
VTSEL
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
NBSG86A
Exposed Pad
(EP)
Figure 2. QFN-16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
QFN
Name
I/O
Description
C2
1
OLS
(Note 3)
Input
Input Pin for the Output Level Select (OLS). See Table 2.
C1
2
SEL
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Select Logic Input.
B1
3
SEL
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Select Logic Input.
B2
4
VTSEL
-
Common Internal 50
W
Termination Pin for SEL/SEL. See Table 7. (Note 1)
A1
5
VTD1
-
Internal 50
W
termination pin. See Table 7. (Note 1)
A2
6
D1
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input 1. Internal 75 k
W
to V
EE
.
A3
7
D1
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input 1. Internal 75 k
W
to V
EE
and 36.5 k
W
to V
CC
.
A4
8
VTD1
-
Internal 50
W
Termination Pin. See Table 7. (Note 1)
B3
9
V
CC
-
Positive Supply Voltage (Note 2)
B4
10
Q
RSECL Output
Noninverted Differential Output. Typically Terminated with 50
W
Resistor to
V
TT
= V
CC
- 2 V.
C4
11
Q
RSECL Output
Inverted Differential Output. Typically Terminated with 50
W
Resistor to
V
TT
= V
CC
- 2 V
C3
12
V
EE
-
Negative Supply Voltage (Note 2)
D4
13
VTD0
-
Internal 50
W
Termination Pin. See Table 7. (Note 1)
D3
14
D0
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input 0. Internal 75 k
W
to V
EE
and 36.5 k
W
to V
CC
.
D2
15
D0
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input 0. Internal 75 k
W
to V
EE
.
D1
16
VTD0
-
Internal 50
W
Termination Pin. See Table 7. (Note 1)
N/A
-
EP
-
Exposed Pad. The thermally exposed pad on package bottom (see case drawing)
must be attached to a heat-sinking conduit.
1. In the differential configuration when the input termination pins (VTDx, VTDx, VTSEL) are connected to a common termination voltage,
and if no signal is applied then the device will be susceptible to self-oscillation.
2. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation.
3. When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, 2 k
W
resistor should be connected from OLS pin to V
EE
.
NBSG86A
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3
Table 2. OUTPUT LEVEL SELECT OLS
OLS
Q/Q VPP
OLS Sensitivity
V
CC
800 mV
OLS - 75 mV
V
CC
- 0.4 V
200 mV
OLS
$
150 mV
V
CC
- 0.8 V
600 mV
OLS
$
100 mV
V
CC
- 1.2 V
0
OLS
$
75 mV
V
EE
(Note 4)
400 mV
OLS
$
100 mV
Float
600 mV
N/A
4. When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, 2.0 k
W
resistor should be
connected from OLS to V
EE
.
Figure 3. Logic Diagram
D0
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
D0
D1
VTD1
VTD1
50
W
50
W
D1
50
W
50
W
VTSEL
R
1
R
2
R
1
R
1
R
2
R
1
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
VTD1
VTD1
50
W
50
W
50
W
50
W
VTSEL
Figure 4. Configuration for AND/NAND Function
V
CC
VT or
V
BB
b
m
D0
D0
D1
D1
V
EE
V
CC
Table 3. AND/NAND TRUTH TABLE
(Note 5)
m
b
m
*
b
D0
D1
SEL
Q
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
5. D0, D1, SEL are inverse of D0, D1, SEL unless specified other-
wise.
NBSG86A
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4
Figure 5. Configuration for OR/NOR Function
Table 4. OR/NOR TRUTH TABLE**
0
0
1
1
D0
m
1
1
1
1
D1
b
0
1
0
1
SEL
m
or
b
0
1
1
1
Q
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
VTD1
VTD1
50
W
50
W
50
W
50
W
VTSEL
V
CC
VT or V
BB
b
m
D0
D0
D1
D1
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
VTD1
VTD1
50
W
50
W
50
W
50
W
VTSEL
b
m
D0
D0
D1
D1
Figure 6. Configuration for XOR/XNOR Function
1
0
0
D1
0
1
0
1
SEL
m
XOR
b
0
1
1
0
Q
Table 5. XOR/XNOR TRUTH TABLE**
0
0
1
1
D0
m
1
b
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
D0
Q
SEL
VTD0
Q
SEL
VTD0
50
W
50
W
D0
D1
VTD1
VTD1
50
W
50
W
D1
50
W
50
W
VTSEL
Figure 7. Configuration for 2:1 MUX Function
D1
D0
Q
Table 6. 2:1 MUX TRUTH TABLE**
1
0
SEL
** D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
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5
Table 7. Interfacing Options
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTD0, VTD1, VTSEL and VTD0, VTD1 to V
CC
LVDS
Connect VTD0, VTD1, VTD0 and VTD1 together. Leave VTSEL open.
AC-COUPLED
Bias VTD0, VTD1, VTSEL and VTD0, VTD1 Inputs within (VIHCMR) Common Mode Range
RSECL, PECL, NECL
Standard ECL Termination Techniques
LVTTL, LVCMOS
An external voltage should be applied to the unused complementary differential input.
Nominal voltage 1.5 V for LVTTL and V
CC
/2 for LVCMOS inputs.
Table 8. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistors
(R
1
)
75 k
W
Internal Input Pullup Resistor
(R
2
)
37.5 k
W
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 1 KV
> 50 V
> 4 KV
Moisture Sensitivity (Note 6)
16-FCBGA
16-QFN
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V-0 @ 0.125 in
Transistor Count
364
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
Table 9. MAXIMUM RATINGS
(Note 7)
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
V
CC
Positive Power Supply
V
EE
= 0 V
3.6
V
V
EE
Negative Power Supply
V
CC
= 0 V
-3.6
V
V
I
Positive Input
Negative Input
V
EE
= 0 V
V
CC
= 0 V
V
I
v
V
CC
V
I
w
V
EE
3.6
-3.6
V
V
V
INPP
Differential Input Voltage |D
n
- D
n
|
V
CC
- V
EE
w
2.8 V
V
CC
- V
EE
< 2.8 V
2.8
|V
CC
- V
EE
|
V
V
I
IN
Input Current Through R
T
(50
W
Resistor)
Static
Surge
45
80
mA
mA
I
out
Output Current
Continuous
Surge
25
50
mA
mA
TA
Operating Temperature Range
16-FCBGA
16-QFN
-40 to +70
-40 to +85
C
C
T
stg
Storage Temperature Range
-65 to +150
C
q
JA
Thermal Resistance (Junction-to-Ambient)
(Note 8)
0 LFPM
500 LFPM
0 LFPM
500 LFPM
16 FCBGA
16 FCBGA
16 QFN
16 QFN
108
86
41.6
35.2
C/W
C/W
C/W
C/W
q
JC
Thermal Resistance (Junction-to-Case)
2S2P (Note 8)
2S2P (Note 9)
16 FCBGA
16 QFN
5.0
4.0
C/W
C/W
T
sol
Wave Solder
t
15 Sec.
225
C
7. Maximum Ratings are those values beyond which device damage may occur.
8. JEDEC standard multilayer board - 2S2P (2 signal, 2 power).
9. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NBSG86A
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6
Table 10. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 10)
-40
C
25
C
70
C(BGA)/85
C(QFN)**
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
23
30
39
23
30
39
23
30
39
mA
V
OH
Output HIGH Voltage (Note 11)
1460
1510
1560
1490
1540
1590
1515
1565
1615
mV
V
OL
Output LOW Voltage (Note 11)
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
555
1235
775
1455
1005
705
1295
895
1505
1095
855
1355
1015
1555
1185
595
1270
810
1490
1040
745
1330
930
1540
1130
895
1390
1050
1590
1220
625
1295
840
1510
1065
775
1355
960
1560
1155
925
1415
1080
1610
1245
mV
V
OUTPP
Output Voltage Amplitude
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
715
125
525
0
325
805
215
615
5
415
705
120
520
0
320
795
210
610
0
410
700
120
515
0
320
790
210
605
5
410
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Note 13)
D, D
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single-Ended)
(Note 14)
D, D
V
EE
V
CC
-
1400*
V
IH
-
150
V
EE
V
CC
-
1400*
V
IH
-
150
V
EE
V
CC
-
1400*
V
IH
-
150
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
1.2
2.5
1.2
2.5
1.2
2.5
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@V
IH
)
D, D
SEL
30
5
100
50
30
5
100
50
30
5
100
50
m
A
I
IL
Input LOW Current (@V
IL
)
D, D
SEL
20
5
100
50
20
5
100
50
20
5
100
50
m
A
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to -0.965 V.
11. All loading with 50
W
to V
CC
- 2.0 V.
12. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
13. V
IH
cannot exceed V
CC
.
14. V
IL
always
w
V
EE
.
*Typicals used for testing purposes.
**The device packaged in FCBGA-16 have maximum ambient temperature specification of 70
C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85
C.
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Table 11. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT
V
CC
= 3.3 V; V
EE
= 0 V (Note 15)
-40
C
25
C
70
C(BGA)/85
C(QFN)***
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
23
30
39
23
30
39
23
30
39
mA
V
OH
Output HIGH Voltage (Note 16)
2260
2310
2360
2290
2340
2390
2315
2365
2415
mV
V
OL
Output LOW Voltage (Note 16)
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
**(OLS = V
EE
)
1320
2030
1550
2260
1785
1470
2090
1670
2310
1875
1620
2150
1790
2360
1965
1360
2065
1585
2290
1820
1510
2125
1705
2340
1910
1660
2185
1825
2390
2000
1390
2090
1615
2315
1850
1540
2150
1735
2365
1940
1690
2210
1855
2415
2030
mV
V
OUTPP
Output Voltage Amplitude
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
**(OLS = V
EE
)
750
130
550
0
345
840
220
640
0
435
740
125
545
0
340
830
215
635
0
430
735
125
540
0
335
825
215
630
0
425
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Note 18)
D, D
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single-Ended)
(Note 19)
D, D
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 17)
1.2
3.3
1.2
3.3
1.2
3.3
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@V
IH
)
D, D
SEL
30
5
100
50
30
5
100
50
30
5
100
50
m
A
I
IL
Input LOW Current (@V
IL
)
D, D
SEL
20
5
100
50
20
5
100
50
20
5
100
50
m
A
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to -0.165 V.
16. All loading with 50
W
to V
CC
- 2.0 V.
17. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
18. V
IH
cannot exceed V
CC
.
19. V
IL
always
w
V
EE
.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70
C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85
C.
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8
Table 12. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V (Note 20)
-40
C
25
C
70
C(BGA)/85
C(QFN)***
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Negative Power Supply Current
23
30
39
23
30
39
23
30
39
mA
V
OH
Output HIGH Voltage (Note 21)
-1040
-990
-940
-1010
-960
-910
-985
-935
-885
mV
V
OL
Output LOW Voltage (Note 21)
-3.465 V
v
V
EE
v
-3.0 V
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
**(OLS = V
EE
)
-3.0 V < V
EE
v
-2.375 V
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
-1980
-1270
-1750
-1040
-1515
-1945
-1265
-1725
-1045
-1495
-1830
-1210
-1630
-990
-1425
-1795
-1205
-1605
-995
-1405
-1680
-1150
-1510
-940
-1335
-1645
-1145
-1485
-945
-1315
-1940
-1235
-1715
-1010
-1480
-1905
-1230
-1690
-1010
-1460
-1790
-1175
-1595
-960
-1390
-1755
-1170
-1570
-960
-1370
-1640
-1115
-1475
-910
-1300
-1605
-1110
-1450
-910
-1280
-1910
-1210
-1685
-985
-1450
-1875
-1205
-1660
-990
-1435
-1760
-1150
-1565
-935
-1360
-1725
-1145
-1540
-940
-1345
-1610
-1090
-1445
-885
-1270
-1575
-1085
-1420
-890
-1255
mV
V
OUTPP
Output Voltage Amplitude
-3.465 V
v
V
EE
v
-3.0 V
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
**(OLS = V
EE
)
-3.0 V < V
EE
v
-2.375 V
(OLS = V
CC
)
(OLS = V
CC
- 0.4 V)
(OLS = V
CC
- 0.8 V, OLS = FLOAT)
(OLS = V
CC
- 1.2 V)
(OLS = V
EE
)
750
130
550
0
345
715
125
525
0
325
840
220
640
0
435
805
215
615
5
415
740
125
545
0
340
705
120
520
0
320
830
215
635
0
430
795
210
610
0
410
735
125
540
0
335
700
120
515
0
320
825
215
630
0
425
790
210
605
5
410
mV
V
IH
Input HIGH Voltage (Single-Ended)
(Note 23)
D, D
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
V
EE
+
1275
V
CC
-
1000*
V
CC
mV
V
IL
Input LOW Voltage (Single-Ended)
(Note 24)
D, D
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
V
IH
-
2600
V
CC
-
1400*
V
IH
-
150
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 22)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
I
IH
Input HIGH Current (@V
IH
)
D, D
SEL
30
5
100
50
30
5
100
50
30
5
100
50
m
A
I
IL
Input LOW Current (@V
IL
)
D, D
SEL
20
5
100
50
20
5
100
50
20
5
100
50
m
A
NOTE: GigaComm circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
20. Input and output parameters vary 1:1 with V
CC
.
21. All loading with 50
W
to V
CC
- 2.0 V.
22. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
23. V
IH
cannot exceed V
CC
.
24. V
IL
always
w
V
EE
.
*Typicals used for testing purposes.
**When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
***The device packaged in FCBGA-16 have maximum ambient temperature specification of 70
C and devices packaged in QFN-16 have
maximum ambient temperature specification of 85
C.
NBSG86A
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9
Table 13. AC CHARACTERISTICS for FCBGA-16
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
-40
C
25
C
70
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figure 8) (Note 25)
7
8
7
8
7
8
GHz
V
OUTPP
Output Voltage Amplitude
(OLS = V
CC
)
f
in
v
7 GHz
550
740
500
720
450
700
mV
t
PLH
,
t
PHL
Propagation Delay to Output Differential
D/SEL
Q
110
160
210
115
165
215
120
170
220
ps
t
SKEW
Duty Cycle Skew (Note 26)
5
15
5
15
5
15
ps
t
SKEW
Channel Skew
Q
D/SEL
5
20
5
20
5
20
ps
t
JITTER
RMS Random Clock Jitter
(See Figure 8) (Note 25)
f
in
v
7 GHz
Peak-to-Peak Data Dependent Jitter
f
in
v
7 Gb/s
0.5
12
1.5
0.5
12
1.5
0.5
12
1.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times (20% - 80%)
(Q, Q)
@ 1 GHz
20
40
65
20
40
65
20
40
65
ps
25. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50
W
to V
CC
- 2.0 V. Input edge rates 40 ps (20% - 80%).
26. t
SKEW
= |t
PLH
- t
PHL
| for a nominal 50% differential clock input waveform. See Figure 12.
27. V
INPP
(max) cannot exceed V
CC
- V
EE
.
Table 14. AC CHARACTERISTICS for QFN-16
V
CC
= 0 V; V
EE
= -3.465 V to -2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
-40
C
25
C
85
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figure 8) (Note 28)
7
8
7
8
7
8
GHz
V
OUTPP
Output Voltage Amplitude
f
in
v
7 GHz
(OLS = V
CC
)
f
in
= 8 GHz
590
270
730
440
470
230
720
420
540
180
700
390
mV
mV
t
PLH
,
t
PHL
Propagation Delay to Output Differential
D/SEL
Q
110
160
210
115
165
215
120
170
220
ps
t
SKEW
Duty Cycle Skew (Note 29)
5
15
5
15
5
15
ps
t
SKEW
Channel Skew
Q
D/SEL
5
20
5
20
5
20
ps
t
JITTER
RMS Random Clock Jitter
(See Figure 8) (Note 31)
f
in
v
7 GHz
Peak-to-Peak Data Dependent Jitter
(Note 32)
f
in
v
7 Gb/s
0.5
12
1.5
0.5
12
1.5
0.5
12
1.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 30)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times (20% - 80%)
(Q, Q)
t
r
@ 1 GHz
t
f
30
17
45
35
60
65
30
17
45
35
60
65
30
17
45
35
60
65
ps
28. Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50
W
to V
CC
- 2.0 V. Input edge rates 40 ps (20% - 80%).
29. t
SKEW
= |t
PLH
- t
PHL
| for a nominal 50% differential clock input waveform. See Figure 12.
30. V
INPP
(max) cannot exceed V
CC
- V
EE
.
31. Additive RMS jitter with 50% duty cycle clock signal at 7 GHz.
32. Additive Peak-to-Peak data dependent jitter with NRZ PRBS 2
31
-1 data rate at 7 Gb/s.
NBSG86A
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10
RMS JITTER
INPUT FREQUENCY (GHz)
OUTPUT VOL
T
AGE AMPLITUDE (mV)
JITTER
OUT
ps (RMS)
0
100
200
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
OLS = V
CC
0
OLS = V
CC
- 0.4 V
*OLS = V
EE
OLS = V
CC
- 0.8 V
OLS = FLOAT
RMS JITTER
INPUT FREQUENCY (GHz)
OUTPUT VOL
T
AGE AMPLITUDE (mV)
JITTER
OUT
ps (RMS)
0
100
200
300
400
500
600
700
800
900
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
OLS = V
CC
0
OLS = V
CC
- 0.4 V
*OLS = V
EE
OLS = V
CC
- 0.8 V,
OLS = FLOAT
Figure 8. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) for 2:1 MUX Mode (V
CC
- V
EE
= 2.5 V @ 25
5
C; Repetitive 1010 Input Data Pattern)
Figure 9. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs.
Input Frequency (f
in
) for 2:1 MUX Mode (V
CC
- V
EE
= 3.3 V @ 25
5
C; Repetitive 1010 Input Data Pattern)
*When an output level of 400 mV is desired and V
CC
- V
EE
> 3.0 V, a 2 k
W
resistor should be connected from OLS to V
EE
.
NBSG86A
http://onsemi.com
11
I
OLS
(
m
A)
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
Figure 10. Typical OLS Input Current vs. OLS Input Voltage
(V
CC
- V
EE
= 3.3 V @ 25
5
C)
V
OLS
(mV)
V
OUTPP
(mV)
0
200
400
600
800
1000
OLS (mV)
Figure 11. OLS Operating Area
V
EE
V
CC
V
CC
- 400
V
CC
- 800
V
CC
- 1200
V
EE
V
CC
V
CC
- 400
V
CC
- 800
V
CC
- 1200
V
CC
- 75
V
CC
- 250
V
CC
- 550
V
CC
- 700
V
CC
- 900
V
CC
- 1125
V
CC
- 1275
V
EE
+ 100
NBSG86A
http://onsemi.com
12
Figure 12. AC Reference Measurement
D
D
Q
Q
t
PHL
t
PLH
V
INPP
(D) = V
IH
(D) - V
IL
(D)
V
OUTPP
(Q) = V
OH
(Q) - V
OL
(Q)
V
INPP
(D) = V
IH
(D) - V
IL
(D)
V
OUTPP
(Q) = V
OH
(Q) - V
OL
(Q)
D
V TT = V CC - 2.0 V
W
Driver
Device
Receiver
Device
Q
D
50
W
50
V TT
Figure 13. Typical Termination for Output Driver and Device Evaluation
(Refer to Application Note AND8020 - Termination of ECL Logic Devices)
Q
Z = 50
W
Z = 50
W
NBSG86A
http://onsemi.com
13
PACKAGE DIMENSIONS
FCBGA-16
BA SUFFIX
PLASTIC 4 X 4 (mm) BGA FLIP CHIP PACKAGE
CASE 489-01
ISSUE O
0.20
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
D
E
M
A1
A2
A
0.10 Z
0.15 Z
ROTATED 90 CLOCKWISE
DETAIL K
_
5
VIEW M-M
e
3 X
S
M
X
0.15
Y
Z
0.08
Z
3
b
16 X
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
4
3
2
1
A
B
C
D
4
16 X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
DIM
MIN
MAX
MILLIMETERS
A
1.40 MAX
A1
0.25
0.35
A2
1.20 REF
b
0.30
0.50
D
4.00 BSC
E
4.00 BSC
e
1.00 BSC
S
0.50 BSC
K
-X-
-Y-
M
M
-Z-
NBSG86A
http://onsemi.com
14
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE O
X
M
0.10 (0.004)
T
-T-
-X-
NOTE 3
SEATING
PLANE
L
A
M
-Y-
B
N
0.25 (0.010) T
0.25 (0.010) T
J
C
K
R
0.08 (0.003) T
G
E
H
F
P
D
Y
1
4
5
8
12
9
16
13
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
3.00 BSC
0.118 BSC
B
3.00 BSC
0.118 BSC
C
0.80
1.00
0.031
0.039
D
0.23
0.28
0.009
0.011
G
0.50 BSC
0.020 BSC
H
0.875
0.925
0.034
0.036
J
0.20 REF
0.008 REF
K
0.00
0.05
0.000
0.002
L
0.35
0.45
0.014
0.018
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION D APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
E
1.75
1.85
0.069
0.073
F
1.75
1.85
0.069
0.073
M
1.50 BSC
0.059 BSC
N
1.50 BSC
0.059 BSC
P
0.875
0.925
0.034
0.036
R
0.60
0.80
0.024
0.031
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
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For additional information, please contact your local
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GigaComm
is a trademark of Semiconductor Components Industries, LLC.
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