Semiconductor Components Industries, LLC, 2003

June, 2003 - Rev. 2

Publication Order Number:

NCN6004A/D

NCN6004A

Dual SAM/SIM Interface
Integrated Circuit

The NCN6004A is an interface IC dedicated for Secured Access

Module reader/writer applications. It allows the management of two
external ISO/EMV cards thanks to a simple and flexible
microcontroller interface. Several NCN6004A interfaces can share a
single data bus, assuming the external MPU provides the right Chip
Select signals to identify each IC connected on the bus. A built in
accurate protection system guarantees timely and controlled shutdown
in the case of external error conditions.

On top of that, the NCN6004A can independently handle the power

supply, in the range 2.7 V to 5.0 V input voltage, provided to each
external Smart Card. The interface monitors the current flowing into
each Smart Card, a flag being set in the case of overload.

Features

Separated, Built-in DC/DC Converters Supply V

Power to

External Cards

100% Compatible with ISO 7816-3, EMV and GIE-CB Standards

Fully GSM Compliant

Individually Programmable ISO/EMV Clock Generator

Built-in Programmable CRD_CLK Stop Function Handles Run or

High/Low State

Programmable CRD_CLK Slopes to Cope with Wide Operating

Frequency Range

Programmable Independent V

Supply for Each Smart Card

Support up to 65 mA V

Supply to Each ISO/EMV Card

Multiple NCN6004A Parallel Operation on a Shared Bus

8 kV/Human Model ESD Protection on Each Interface Pin

Provides C4/C8 Channels

Provides 1.80 V, 3.0 V or 5.0 V Card Supply Voltages

Typical Applications

Set Top Box Decoder

ATM Multi Systems, POS, Handheld Terminals

Internet E-commerce PC Interface

Multiple Self Serve Automatic Machines

Wireless Phone Payment Interface

Automotive Operating Time Controller

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MARKING
DIAGRAM

Device

Package

Shipping

ORDERING INFORMATION

NCN6004AFTBR2

TQFP48

2000 Tape & Reel

TQFP48

CASE 932F

PLASTIC

NCN6004A

AWLYYWW

= Assembly Location

WL = Wafer Lot
YY = Year
WW = Work Week

NCN6004A

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CRD_IO_A

CRD_RST_A

CRD_CLK_A

CRD_VCC_A

CRD_C4_A

CRD_C8_A

CRD_DET_A

CRD_IO_B

CRD_RST_

CRD_CLK_B

CRD_VCC_B

CRD_C8_B

CRD_C4_B

CRD_DET_

PWR_ON

TUS

RESET_A

I/O_A

CLOCK_IN_A

C4_A

C8_A

PWR_VCC_A

PWR_GND

L1b

L2b

L2a

L1a

ANLG_GND

ANLG_VCC

PWR_VCC_B

CARD_SEL

EN_RPU

I/O_B

RESET_B

CLOCK_IN_B

C4_B

C8_B

ANLG_GND

PWR_GND

ANLG_GND

MUX_MODE

PGM

INT

Figure 1. Pin Diagram

GND

POR

T#A

POR

T#B

MPU BUS

MICRO CONTROLLER

PWR_ON

STATUS

CARD_SEL

5
6

I/O_A

RESET_A

C4_A

C8_A

CLK_IN_A

EN_RPU

MUX_MODE

ANLG_GND

ANLG_VCC

ANLG_GND

CLK_IN_B

C8_B

C4_B

RESET_B

I/O_B

C1
10

DET

RST

CLK

I/O

VPP

GND

DET

SMARTCARD # A

DET

SMARTCARD # B

GND

PWR_VCC_A

PWR_GND

CRD_DET_A

CRD_VCC_A

CRD_CLK_A

CRD_IO_A

CRD_DET_B

CRD_VCC_B

CRD_CLK_B

CRD_IO_B

CRD_RST_A

CRD_RST_B

CRD_C4_A

CRD_C8_A

CRD_C4_B

CRD_C8_B

PWR_VCC_B

PWR_GND

GND

PGM
CS

INT

100 nF

L1a

L2a

L2b

L1b

Figure 2. Typical Application

RST

CLK

I/O

VPP

GND

44
45

CHIP SELECT

IRQ

C2
10

GND

NCN6004A

NCN6004A

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L1b

L2b

CARD#A DETECTION

CARD#B DETECTION

I/O#A

I/O#B

CLK#A

CLK#B

CLK#A

CLK#B

DET#B

GND

CRD_C4A

CRD_C8A

CRD_C8B

CRD_C4B

CRD_IOA

CRD_IOB

CRD_CLKA

PWR_GND

CRD_VCCA

CRD_VCCB

CRD_CLKB

CRD_RSTA

CRD_RSTB

C4A

C8A

C4B

C8B

PWR_VCCA

PWR_VCCB

CRD_DETB

CRD_DETA

RESET_A

CLK_A

CLK_B

GND

Figure 3. Block Diagram

100 k

INPUT VOLTAGE

ANLG_VCC

PWR_ON

CLK_INA

CLK_INB

AGND

CARD_SEL

GND

INT

PGM

MONITOR

IO_A

RST_A

C4A

C8A

IO_B

RST_B

C4B

C8B

CNTL

50 k

DC/DC CONVER

TER

CARD #A

DC/DC CONVER

TER

PINS DRIVERS

CARD#A

CARD#B

CARD#A

SEQUENCER

CARD#B SEQUENCER

INTERRUPT BLOCK

CLOCK#A

CLOCK#B

DIGIT

BLOCK

DET#B

DET#A

I/O_A

I/O_B

C4A

C8A

C4B

C8B

RESET_A

EN_RPU

MUX_MODE

26 k

100 k

RESET_B

DIVIDER

IO_A

C4A

C8A

IO_B

C4B

C8B

CONTROL

ANALOG & DIGIT

MUL

TIPLEX

100 k

26 k

100 k

RST_A

RST_B

NOTE:

An internal active pull down device forces all the
smart card pins to zero when the chip is deactivated.

DET#A

RESET_A

L1a

L2a

STATUS

50 k

NCN6004A

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PIN DESCRIPTION

Pin

Symbol

Type

Description

INPUT

This pin is combined with CS, A1, A2, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by
the internal STATUS register (Table 1).

INPUT

This pin is combined with CS, A0, A2, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by
the internal STATUS register (Table 1).

INPUT

This pin is combined with CS, A0, A1, A3, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by
the internal STATUS register (Table 1).

INPUT

This pin is combined with CS, A0, A1, A2, CARD_SEL and PGM to program the chip
mode of operation, the CRD_VCC voltage value, and to read the data provided by
the internal STATUS register (Table 1).

CARD_SEL

INPUT

This pin provides logic identification of the Card #A/Card #B external smart card.
The logic signal is set up by the external microcontroller.

CARD_SEL = High

selection of the Smart Card A connected to pins 20, 21, 22,

23, 24, 29 and 30 (respectively CRD_DET_A, CRD_C8_A, CRD_C4_A,
CRD_RST_A, CRD_IO_A, CRD_VCC_A and CRD_CLK_A).

CARD_SEL = Low

selection of the Smart Card B connected to pins 41, 39, 40,

31, 38, 37, and 32 (respectively CRD_DET_B, CRD_C4_B, CRD_C8_B,
CRD_CLK_B, CRD_RST_B, CRD_IO_B, and CRD_VCC_B).

ÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

PGM

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

DIGITAL INPUT

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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin is combined with CS, A0, A1, A2, A3, and CARD_SEL to program the chip
mode of operation and to read the data provided by the internal STATUS register
(Figure 4 and Table 1).

PGM = H

the NCN6004A is under normal operation and all the data with the exter-

nal card can be exchanged using any of the Smart Card A or Smart Card B Lines

PGM = Low

the NCN6004A runs the programming mode and related parameters

can be re programmed according to a given need. In this case, the related card side
logic signals are latched in their previous states and no transaction can occurs.

The programmed states are latched upon the PGM rising slope (Figure 4).

ÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

ÁÁÁÁ

ÁÁÁÁÁÁ

DIGITAL INPUT

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

This pin provides the Chip Select Function for the NCN6004A device.

CS = High

Pins A0, A1, A2, A3, CARD_SEL, PGM, PWR_ON, RESET_A, RE-

SET_B, C4_A, C4_B, C8_A, C8_B, I/O_A and I/O_B are disabled, the pre activated
CRD_VCC maintains it's currently programmed value.

CS = Low

Pins A0, A1, A2, A3, CARD_SEL, PGM, PWR_ON, RESET_A, RE-

SET_B, C4_A, C4_B, C8_A, C8_B, I/O_A and I/O_B are activated, all the functions
being available.An internal pull up resistor, connected to V

, provides a logic bias

when the external

P is in the high impedance state.

PWR_ON

DIGITAL INPUT

This pin activates or deactivates the DC/DC converter selected by CARD_SEL upon
positive/negative going transient.

PWR_ON = Positive going High

DC/DC Activated

PWR_ON = Negative going L

DC/DC switched Off, no power is applied to the

associated output CRD_VCC pin.

Since uncontrolled action could take place during the rise voltage of the related
CRD_VCC_x output, care must be observed to avoid a PWR_ON negative going
transient during this period of time. To avoid any logical latch up, using a minimum
1.0 ms delay is recommended prior to power down the related DC/DC converter
following a power up command (Figure 12).

I/O_A

INPUT/OUTPUT

This pin carries the data transmission between an external microcontroller and the
external smart card #A.

A built-in bi-directional level translator adapts the signal flowing between the card
and the MCU. The level translator is enabled when CS = Low. Since a dedicated line
is used to communicate the data between the MPU and the smart card, the user can
activate the two channels simultaneously, assuming the

P provides a pair of I/O

lines.

When MUX_MODE = High, this pin provides an access to either card A or B I/O by
means of CARD_SEL selection bit. On the other hand, the internal pull up resistor is
automatically disconnected when MUX_MODE = High, avoiding a current overload
on the I/O line, regardless of the EN_RPU logic level.

This pull up resistor is under the EN_RPU control when MUX_MODE = Low.

NCN6004A

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PIN DESCRIPTION (continued)

Pin

Description

Type

Symbol

RESET_A

INPUT

The signal present on this pin is translated to the RST pin of the external smart card
#A. The CS signal must be Low to validate the RESET function, regardless of the
selected card.

Assuming the

P provides two independent lines to control the RESET pins, the

NCN6004A can control two cards simultaneously.

When MUX_MODE = High, this pin provides an access to either card A or B Reset
by means of CARD_SEL selection bit.

The associated pull up resistor is either connected to V

(EN_RPU = H) or discon-

nected when EN_RPU = Low.

C4_A

INPUT

This pin controls the card #A C4 contact The signal can be either de-multiplexed, at
MPU level, or is multiplexed with C4_B, depending upon the MUX_MODE logic
state.

When MUX_MODE = High, this pin provides an access to either card A or B C4
channel by means of CARD_SEL selection bit.

The associated pull up resistor is either connected to V

(EN_RPU = H) or discon-

nected when EN_RPU = Low.

C8_A

INPUT

This pin controls the card #A C8 contact. The signal can be either de-multiplexed, at
MPU level, or is multiplexed with C8_B, depending upon the MUX_MODE logic
state.

When MUX_MODE = High, this pin provides an access to either card A or B C8
channel by means of CARD_SEL selection bit.

The associated pull up resistor is either connected to V

(EN_RPU = H) or discon-

nected when EN_RPU = Low.

CLOCK_IN_A

Clock Input,

High Impedance

The signal present on this pin comes from either the MCU master clock, or from any
signal fulfilling the logic level and frequency specifications. This signal is fed to the
internal clock selection circuit prior to be connected to the external smart card #A.
Each of the external card can have different division ratio, depending upon the state
of the CRD_SEL pin and associated programming bits. The built-in circuit can be
programmed to 1/1, 1/2, 1/4 or 1/8 frequency division ratio.

This input is valid and routed to either CRD_CLK_A _DIVIDER or CRD_CLK_B_DI-
VIDER regardless of the MUX_MODE state, depending upon the CLK_D_A/
CRD_D_B and CARD_SEL programmed states (Table 1).

Although this input supports the signal coming from a crystal oscillator, care must be
observed to avoid digital levels outside the specified V

range. Similarly, the

input clock signal shall have rise and fall times compatible with the operating fre-
quency.

ANLG_GND

POWER

This pin is the ground reference for both analog and digital signals and must be con-
nected to the system Ground. Care must be observed to provide a copper PCB lay-
out designed to avoid small signals and power transients sharing the same track.
Good high frequency techniques are strongly recommended.

CLOCK_IN_B

Clock Input,

High Impedance

The signal present on this pin comes from either the MCU master clock, or from any
signal fulfilling the logic level and frequency specifications. This signal is fed to the
internal clock selection circuit prior to be connected to the external smart card #B.
Each of the external card can have different division ratio, depending upon the state
of the CRD_SEL pin and associated programming bits. The built-in circuit can be
programmed to 1/1, 1/2, 1/4, or 1/8 frequency division ratio.

This input is valid and routed to either CRD_CLK_B_DIVIDER or CRD_CLK_A_DI-
VIDER regardless of the MUX_MODE state, depending upon the
CRD_D_B/CRD_D_A and CARD_SEL programmed states (Table 1).

Although this input supports the signal coming from a crystal oscillator, care must be
observed to avoid digital levels outside the specified V

range. Similarly, the

input clock signal shall have rise and fall times compatible with the operating fre-
quency.

C8_B

INPUT

This pin controls the card #B C8 contact. The signal can be either de -multiplexed,
at MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic
state.

When MUX_MODE = High, this pin is internally disable, a pull up resistor is con-
nected to V

(regardless of the logic state of EN_RPU is), and the access to card B

takes place by C8_A associated with CARD_SEL selection bit.

The associated pull up resistor is either connected to V

(EN_RPU = H) or discon-

nected when EN_RPU = Low.

NCN6004A

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PIN DESCRIPTION (continued)

Pin

Description

Type

Symbol

C4_B

INPUT

This pin controls the card #B C4 contact. The signal can be either de -multiplexed,
at MPU level, or is multiplexed with C8_A, depending upon the MUX_MODE logic
state.

When MUX_MODE = High, this pin is internally disable, a pull up resistor is con-
nected to V

, (regardless of the logic state of EN_RPU), and the access to card B

takes place by C4_A associated with CARD_SEL selection bit.

The associated pull up resistor is either connected to V

(EN_RPU = H) or discon-

nected when EN_RPU = Low.

RESET_B

INPUT

The signal present on this pin is translated to the RST pin of the external smart card
#B. The CS signal must be Low to valid the RESET function, regardless of the se-
lected card. Assuming the

P provides two independent lines to control the RESET

pins, and MUX_MODE = Low, the NCN6004A can control two cards simultaneously.

When MUX_MODE = High, this pin is internally disable, a pull up resistor is con-
nected to V

, (regardless of the logic state of EN_RPU), and the access to card B

takes place by RESET_A associated with CARD_SEL selection bit.

The associated pull up resistor is either connected to V

(EN_RPU = H) or discon-

nected when EN_RPU = Low.

I/O_B

INPUT/OUTPUT

This pin carries the data transmission between an external microcontroller and the
external smart card #B.

A built-in bi-directional level translator adapts the signal flowing between the card
and the MCU. The level translator is enabled when CS = Low. The signal present on
this pin is latched when CS = High. Since a dedicated line is used to communicate
the data between the

P and the smart card, (assuming MUX_MODE = Low) the

user can activate the two channels simultaneously, assuming the

P provides a pair

of I/O lines. When MUX_MODE = High, this pin is internally disable, the pull up re-
sistor is connected to V

, (regardless of the logic state of EN_RPU), and the ac-

cess to card B takes place by I/O_A associated with CARD_SEL selection bit.

CRD_DET_A

INPUT

This pin senses the signal coming from the external smart card connector to detect
the presence of card #A. The polarity of the signal is programmable as Normally
Open or Normally Close switch. The logic signal will be activated when the level is
either Low or High, with respect to the polarity defined previously. By default, the
input is Normally Open. A built-in circuit prevents uncontrolled short pulses to gen-
erate an INT signal. The digital filter eliminates pulse width below 50

s (see spec).

CRD_C8_A

OUTPUT

This pin controls the card #A C8 contact, according to the ISO7816 specifications. A
built-in level shifter is used to adapt the card and the

C, regardless of the power

supply voltage of each signals.

The signal present at this pin is latched upon either CARD_SEL =L, or CS = H or
PGM = L, and resume to a transparent mode when card #A is selected and operates
in the transfer mode.The pin is hardwired to zero, the bias being provided by the
V

supply, when either the V

voltage drops below 2.7 V, or during the

CRD_VCC_A start-up time.

CRD_C4_A

OUTPUT

This pin controls the card #A C4 contact, according to the ISO7816 specifications. A
built-in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.

The signal present at this pin is latched upon either CARD_SEL = L, or CS = H, or
PGM = L, and resume to a transparent mode when card #A is selected and operates
in the transfer mode.

The pin is hardwired to zero, the bias being provided by the V

supply, when either

the V

voltage drops below 2.7 V, or during the CRD_VCC_A start-up time.

CRD_RST_A

OUTPUT

This pin is connected to the external smart card #A to support the RESET signal. A
built-in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.

The signal present at this pin is latched upon either CARD_SEL = Low, or when CS
or PGM returns to a High, and resume to a transparent mode when card #A is se-
lected. The pin is hardwired to zero, the bias being provided by the V

supply,

when either the V

voltage drops below 2.7 V, or during the CRD_VCC_A start-up

time.

NCN6004A

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PIN DESCRIPTION (continued)

Pin

Description

Type

Symbol

CRD_IO_A

INPUT/OUTPUT

This pin carries the data serial connection between the external smart card #A and
the microcontroller. A built-in bidirectional level shifter is used to adapt the card and
the MCU, regardless of the power supply voltage of each signals.

This pin is biased by a pull up resistor connected to CRD_VCC_A. When CS = High,
the CRD_IO_A holds the previous I/O logic state and resume to a normal operation
when this pin is reactivated.

The pin is hardwired to zero, the bias being provided by the V

supply, when either

the V

voltage drops below 2.7 V, or during the CRD_VCC_A start-up time.

PWR_GND

POWER

This pin carries the power current flow coming from the built in DC/DC converters. It
is associated with the external card # A. It must be connected to the system Ground
and care must be observed at PCB layout level to avoid the risk of spike voltages on
the logic lines.

L2_A

POWER

Connects one side of the external DC/DC converter inductor #A (Note 1)

L1_A

POWER

Connects one side of the external DC/DC converter inductor #A (Note 1).

PWR_VCC_A

POWER

This pin is connected to the positive external power supply. The device sustains any
voltage from +2.7 V to +5.5 V. This voltage supplies the NCN6004A internal circuits
and is regulated by the internal DC/DC converter to provide the DC voltage to the
external card. A high quality capacitor must be connected across pin 28 and
PWR_GND, 10

F/6.0 V ceramic X7R or X5R type is recommended.

Note: The voltage present at pin 28 and 33 must be equal to the voltage present at
pin 42.

CRD_VCC_A

POWER

This pin provides the power supply to the external smart card #A. The V

voltage is

defined by programming the NCN6004A accordingly. Since the cards have indepen-
dent DC/DC converter, the output voltage can have any value independently from
CARD_B.

A high quality, low ESR capacitor is mandatory to achieve the V

specifications.

Using two 4.7

F/6.0 V ceramic X7R or X5R capacitors in parallel is recommended.

CRD_CLK_A

OUTPUT

This pin is connected to the CLK external smart card #A pin. The signal comes from
the built- in frequency divider dedicated to the #A card. The clock is selected and con-
trolled by setting the logic inputs according to Table 1. The slope of the output clock can
be selected between one of the two programmable mode: SLOW or FAST (Table 8).
The pin is hardwired to zero, the bias being provided by the V

supply, when either

the V

voltage drops below 2.7 V, or during the CRD_VCC_A start- up time.

CRD_CLK_B

OUTPUT

This pin is connected to the CLK external smart card #B pin. The signal comes from
the built- in frequency divider dedicated to the #B card. The clock is selected and con-
trolled by setting the logic inputs according to Table 1. The slope of the output clock can
be selected between one of the two programmable mode: SLOW or FAST (Table 8).
The pin is hardwired to zero, the bias being provided by the V

supply, when either

the V

voltage drops below 2.7 V, or during the CRD_VCC_B start- up time.

CRD_VCC_B

POWER

This pin provides the power supply to the external smart card #B. The V

voltage is

defined by programming the NCN6004A accordingly. Since the cards have indepen-
dent DC/DC converter, the output voltage can have any value independently from
CARD_A.

A high quality, low ESR capacitor is mandatory to achieve the V

specifications.

Using two 4.7

F/6.0 V ceramic X7R or X5R capacitors in parallel is recommended.

PWR_VCC_B

POWER

This pin is connected to the positive external power supply. The device sustains any
voltage from +2.7 V to +6.0 V. This voltage supplies the NCN6004A internal circuits
and is regulated by the internal DC/DC converter to provide the DC voltage to the
external card. A high quality capacitor must be connected across pin 33 and
PWR_GND, 10

F/6.0 V ceramic X7R type is recommended.

Note: The voltage present on pin 28 and 33 must be equal to the voltage present on
pin 42

L2b

POWER

Connects one side of the external DC/DC converter inductor #B (Note 1).

L1b

POWER

Connects one side of the external DC/DC converter inductor #B (Note 1).

PWR_GND

POWER

This pin carries the power current flow coming from the built in DC/DC converters. It
is associated with the external card # B. It must be connected to the system Ground
and care must be observed at PCB layout level to avoid the risk of spike voltages on
the logic lines.

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ

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1. The external inductors shall preferably have the same values. Depending upon the power absorbed by the load, the inductor can range

from 10

H to 47

H. To achieve the highest yield, the inductor shall have an ESR < 1.0

NCN6004A

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PIN DESCRIPTION (continued)

Pin

Description

Type

Symbol

CRD_IO_B

INPUT/OUTPUT

This pin carries the data serial connection between the external smart card #B and
the microcontroller. A built-in bi-directional level shifter is used to adapt the card
and the MCU, regardless of the power supply voltage of each signals.

This pin is biased by a pull up resistor connected to CRD_VCC_A. When CS = High,
the CRD_IO_A holds the previous I/O logic state and resume to a normal operation
when this pin is reactivated.

The pin is hardwired to zero, the bias being provided by the V

supply, when either

the V

voltage drops below 2.7 V, or during the CRD_VCC_B start-up time.

CRD_RST_B

OUTPUT

This pin is connected to the external smart card #B to support the RESET signal. A
built-in level shifter is used to adapt the card and the MCU, regardless of the power
supply voltage of each signals.

The signal present at this pin is latched upon either CARD_SEL or CS or PGM posi-
tive going transient and resume to a transparent mode when card #B is selected.

The pin is hardwired to zero, the bias being provided by the V

supply, when either

the V

voltage drops below 2.7 V, or during the CRD_VCC_B start-up time.

CRD_C4_B

OUTPUT

This pin controls the card #B C4 contact, according to the ISO specification. A built-
in level shifter is used to adapt the card and the MCU, regardless of the power sup-
ply voltage of each signals. The signal present at this pin is latched upon either
CARD_SEL or CS or PGM

positive going transient and resume to a transparent

mode when card #B is selected.

The pin is hardwired to zero, the bias being provided by the V

supply, when either

the V

voltage drops below 2.7 V, or during the CRD_VCC_B start-up time.

CRD_C8_B

OUTPUT

This pin controls the card #B C8 contact, according to the ISO specification. A built-
in level shifter is used to adapt the card and the MCU, regardless of the power sup-
ply voltage of each signals. The signal present at this pin is latched upon either
CARD_SEL or CS or PGM positive going transient and resume to a transparent
mode when card #B is selected.

The pin is hardwired to zero, the bias being provided by the V

supply, when either

the V

voltage drops below 2.7 V, or during the CRD_VCC_B start-up time.

CRD_DET_B

INPUT

This pin senses the signal coming from the external smart card connector to detect
the presence of card #B. The polarity of the signal is programmable as Normally
Open or Normally Close switch. The logic signal will be activated when the level is
either Low or High, with respect to the polarity defined previously. By default, the
input is Normally Open. A built-in circuit prevents uncontrolled short pulses to gen-
erate an INT signal. The digital filter eliminates pulse width below 50

ANLG_VCC

POWER

This pin is connected to the positive external power supply. The device sustains any
voltage from +2.7 V to +5.5 V. This voltage supplies the NCN6004A internal Analog
and Logic circuits. A high quality capacitor must be connected across this pin and
ANLG_GND, 10

F/6 V is recommended. A set of extra pins (28 and 33) are pro-

vided to connect the power supply to the internal DC/DC converter.

Note: The voltage present at pin 28 and 33 must be equal to the voltage present at
pin 42

ANLG_GND

GROUND

MUX_MODE

INPUT

This pin selects the mode of operation of the card signals from the MPU side. When
MUX_MODE = Low, all the card signals are fully de-multiplexed and data transfers
can take place with both cards simultaneously. On top of that, both cards can be
accessed during the programming sequence, assuming the external microcontroller
is capable to run multi tasks software.

When MUX_MODE = High, all the card signals are multiplexed and the communica-
tions with the cards shall take place in a sequential mode. The card is selected by
setting CARD_SEL high or Low. The internal logic will disable the CARD_B inputs
and use CARD_SEL inputs as a single channel to controls both output smart cards
sequentially when MUX_MODE = H.

Moreover, when MUX_MODE = High, all the B channel

P dedicated pins, except

CLOCK_IN_B, pin 15, are forced to a high level by means of internal pull up resis-
tors. It is not necessary to connect these pins (16, 17, 18 and 19) to an external bias
voltage, but it is mandatory to avoid any connections to ground. On the other hand,
in this case the internal pull up resistor connected across I/O_A, pin 9 and V

automatically disconnected to avoid a current overload on the I/O line.

NCN6004A

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PIN DESCRIPTION (continued)

Pin

Description

Type

Symbol

EN_RPU

INPUT

This pin provides a logic input to valid or not the internal pull up resistors connected
across each I/O, RESET, C4 and C8 lines and ANLG_VCC.

When EN_RPU = High, the pull up resistors are connected

When EN_RPU = Low, the pull up resistors are disconnected and it is up to the de-
signer to set up the external resistor to cope with the ISO/EMV specifications.

The logic signal must be set up prior to apply the ANLG_VCC supply. Once the logic
mode has been acknowledged by the internal Power On reset, it cannot be changed
until a new start-up sequence is launched.

STATUS

OUTPUT

This pin provides a logic state related to the card [A or B] insertion, the VCC_OK,
the CRD_VCC value and the current overflow powered to either card [A or B]. The
internal register can be read when PGM = High. The logic level is forced to High
when the input voltage drops below the V

bat

min (2.0 V), thus reducing the stand by

current, assuming the STATUS pin is not pulled down externally.

The associated pull up resistor is either connected to V

(EN_RPU = H) or discon-

nected when EN_RPU = Low.

INT

OUTPUT

This pin is activated LOW when a card has been inserted and detected in either of
the external ports. The signal is reset by either a positive going transition on pin CS,
or by a High level on pin PWR_ON combined with CS = Low.

Similarly, an interrupt is generated when either one of the CRD_VCC output is over-
loaded.

On the other hand, the pin is forced to a logic High when the input voltage V

drops below 2.0 V min.

The associated pull up resistor is either connected to V

(EN_RPU = H) or discon-

nected when EN_RPU = Low.

ANLG_GND

GROUND

MAXIMUM RATINGS

(Note 2)

Rating

Symbol

Value

Unit

Power Supply Input Supply Voltage

Digital Input Pins

-0.5 V < V

< V

+0.5 V,

but < 6.0 V

Power Supply Input Current

500

Digital Input Pins

-0.5 < V

or V

< 5.5

Digital Output Pins

out

-0.5 < V

or V

< 5.5

Card Interface Pins

card

-0.5V < V

card

< CRD_VCC +0.5V

15 mA (internally limited)

ESD Capability, Human Body Model (Note 3)

Standard Pins
Card Interface Pins (Card A or B)

ESD

2
8

kV
kV

TQFP48

Power Dissipation @ Tab = +85

Thermal Resistance Junction-to-Air

800

C/W

Operating Ambient Temperature Range

-40 to +85

Operating Junction Temperature Range

-40 to +125

Maximum Junction Temperature (Note 4)

Jmax

+150

Storage Temperature Range

Tag

-65 to +150

2. Maximum Electrical Ratings are defined as those values beyond which damage(s) to the device may occur at T

= +25

3. Human Body Model, R = 1500

, C = 100 pF.

4. Absolute Maximum Rating beyond which damage(s) to the device may occur.

NCN6004A

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POWER SUPPLY SECTION

General test conditions, unless otherwise specified: Operating temperature: -25

C < T

< +85

= +3.0 V, CRD_VCC_A = CRD_VCC_B = +5.0 V.

Rating

Symbol

Pin

Min

Typ

Max

Unit

out

= 2 x 65 mA (both external cards running simultaneously)

@ 3.0 V < V

< 5.5 V

CRD_VCC

29, 32

4.6

5.4

out

= 2 x 55 mA per pin (both external cards running)

out

defined @ CRD_VCC = 3.0 V @ 3.0 V < V

< 5.5 V

CRD_VCC

29, 32

2.7

3.3

out

= 2 x 35 mA per pin (both external cards running)

out

defined @ CRD_VCC = 1.80 V @ 3.0 V < V

< 5.5 V

CRD_VCC

29, 32

1.65

1.95

Output Card Supply Voltage Ripple (per CRD_VCC outputs) @ :
L

out

= 22

H, L

ESR

< 2.0

, C

out

= 10

F per CRD_VCC (Note 5)

out

= 35 mA, V

out

= 1.80 V

out

= 55 mA, V

out

= 3.0 V

out

= 65 mA, V

out

= 5.0 V

ORA

ORB

29
32

-
-
-

50
50
50

DC/DC Dynamic Inductor Peak Current @ V

bat

= 5.0 V, L

out

= 22

out

= 10

CRD_VCC = 1.8 V
CRD_VCC = 3.0 V
CRD_VCC = 5.0 V

ccov

29, 32

-
-
-

200
280
430

-
-
-

Standby Supply Current Conditions (Note 5):

ANLG_VCC = PWR_VCC = 3.0 V

PWR_ON = H, STATUS = H, CS = H
Card A and Card B CLOCK_IN = H, I/O = H, RESET = H
All Logic Inputs = H, Temperature range = 0

C to +50

ANLG_VCC = PWR_VCC = 5.0 V

Temperature range 25

C to +85

All other test conditions identical

ANLG_VCC = PWR_VCC = 1.8 V

Temperature range 25

C to +50

All other test conditions identical

Note: This parameter is guaranteed by design, not production tested.

42, 28,

-
-
-

-
-

5.0

Operating Supply Current

ANLG_VCC = PWR_VCC

= 5.5 V

@ CRD_VCC_A/B = 5.0 V
@ CRD_VCC_ A/B = 3.0 V
@ CRD_VCC_ A/B = 1.85 V

ANLG_VCC = PWR_VCC = 3.3 V

@ CRD_VCC_A/B = 5.0 V
@ CRD_VCC_ A/B = 3.0 V
@ CRD_VCC_ A/B = 1.85 V

PWR_ON = H, CS = H, CLK_A = CLK_B = Low, all card pins unloaded

DDop

42, 28,

0.7
0.7
0.7

0.2
0.2
0.2

bat

Under Voltage Detection Positive Going Slope

bat

Under Voltage Detection Negative Going Slope

bat

Under Voltage Detection Hysteresis

Note: The voltage present in pins 28 and 33 must be equal to or

Note:

lower than the voltage present in pin 42.

batLH

batLL

batHY

2.1
2.0

-
-

100

2.7
2.6

V
V

Output Continuous Current Card A or Card B (both cards can be
operating simultaneously) @ 3.0 < V

< 5.5 V

Output Voltage = 1.85 V
Output Voltage = 3.0 V
Output Voltage = 5.0 V

ccp

31, 42

35
55
65

Output Over Current Limit (A or B)

bat

= 3.3 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V

bat

= 5.0 V, CRD_VCC = 1.8 V, 3.0 V or 5.0 V

ccov

31, 42

100
150

Output Over Current Time Out Per Card

tdoff

31, 42

4.0

Output Card Supply Turn On Time @

out

= 22

F, C

out

= 10

F Ceramic.

= 2.7 V, CRD_VCC = 5.0 V (A or B)

CCTON

31, 42

500

5. Assuming ANLG_VCC and PWR_VCC pins are connected to the same power supply.

NCN6004A

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POWER SUPPLY SECTION

General test conditions, unless otherwise specified: Operating temperature: -25

C < T

< +85

= +3.0 V, CRD_VCC_A = CRD_VCC_B = +5.0 V. (continued)

Rating

Unit

Max

Typ

Min

Pin

Symbol

Output Card Supply Shut Off Time @

out

= 10

F, ceramic.

= 2.7 V, CRD_VCC = 5.0 V, V

CCOFF

< 0.4 V (A or B)

CCTOFF

31, 42

100

250

DC/DC Converter Operating Frequency (A or B)

31, 42

600

kHz

5. Assuming ANLG_VCC and PWR_VCC pins are connected to the same power supply.

DIGITAL INPUT/OUTPUT SECTION

2.70 < V

< 5.50 V, Normal Operating Mode (-25

C to +85

C ambient temperature, unless otherwise noted)

Rating

Symbol

Pin

Min

Typ

Max

Unit

A0, A1, A2, A3, CARD_SEL, PWR_ON, PGM, CS, MUX_MODE,
EN_RPU, RESET_A, RESET_B, C4_A, C8_A, C4_B, C8_B

High Level Input Voltage
Low Level Input Voltage
Input Capacitance

1, 2, 3,
4, 5, 6,

7, 8,

44, 45,
10, 18,

11, 12,

16, 17

0.7 * V

bat

0.3 * V

bat

V
V

STATUS, INT

Output High Voltage @ I

= -10

Output Low Voltage @ I

= 200

46, 47

bat

1.0 V

0.40

STATUS, INT

Output Rise Time @ C

out

= 30 pF

Output Fall Time @ C

out

= 30 pF

trsta, trint

tfsta, tfint

100

CLOCK_A Asynchronous Input Clock @ DC = 50%

CLKINA

MHz

CLOCK_B Asynchronous Input Clock @ DC = 50%

CLKINB

MHz

I/O_A, I/O_B, both directions @ C

out

= 30 pF

I/O Rise Time
I/O Fall Time

rioA

, t

rioB

fioA

, t

fioB

9, 19

0.8
0.8

STATUS Pull Up Resistance

STA

INT Pull Up Resistance

INT

I/O_A Pull Up Resistance

IOA

I/O_B Pull Up Resistance

IOB

RESET_A Pull Up Resistance

RSTA

100

RESET_B Pull Up Resistance

RSTB

100

C4_A Pull Up Resistance

C4A

100

C8_A Pull Up Resistance

C8A

100

C4_B Pull Up Resistance

C4B

100

C8_B Pull Up Resistance

C8B

100

CS Pull Up Resistance

100

CRD_DET_A and CRD_DET_B Pull Up Resistance

DETA

DETB

20
41

500
500

NCN6004A

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CARD INTERFACE SECTION

@ 2.70 < V

< 5.50 V, Normal Operating Mode (-25

C to +85

C ambient temperature, unless

otherwise noted) CRD_VCC_A = CRD_VCC_B = 1.8 V or 3.0 V or 5.0 V

Rating

Symbol

Pin

Min

Typ

Max

Unit

CRD_RST_A, CRD_RST_B Output Voltage

Output RST High Level @ Irst = -200

Output RST Low Level @ Irst = 200

CRD_RST_A, CRD_RST_B Rise and Fall time

RST Rise Time @ C

out

= 30 pF

RST Fall Time @ C

out

= 30 pF

trrst
tfrst

23, 38
23, 38

CRD_VCC-0.5

CRD_VCC

0.4

100
100

V
V

ns
ns

CRD_CLK_A, CRD_CLK_B Output Clock

Output Operating Clock Card A and Card B
Output Operating Clock DC, Card A and Card B
(Input DC = 50%,

1%)

Note: This parameter is guaranteed by design, functionality 100%
tested at production.
Output Operating Clock Rise Time SLOW Mode

Card A and Card B

Output Operating Clock Fall Time SLOW Mode

Card A and Card B

Output Operating Clock Rise Time FAST Mode

Card A and Card B

Output Operating Clock Fall Time FAST Mode

Card A and Card B

Output Clock High Level, Card A and Card B, @ Iclk = -200

Output Clock Low Level, Card A and Card B, @ Iclkc = 200

clkA

, F

clkB

trclka, trclkb

tfclka, tfclkb

trclka, trclkb

tfclka, tfclkb

30, 31

CRD_VCC-0.5

20
55

CRD_VCC

0.4

MHz

V
V

CRD_IO_A, CRD_IO_B Data Transfer
Data Transfer Frequency, Card A and Card B
Data Rise Time, Card A and Card B, @ C

out

= 30 pF

Data Fall Time, Card A and Card B, @ C

out

= 30 pF

Data Output High Level, Card A and Card B @ Icrd_io = -20

Data Output Low Level, Card A and Card B @ Icrd_io = 20

IOA

, F

IOB

rioa,

riob

fioa,

fiob

24, 37

CRD_VCC-0.5

400

0.8
0.8

CRD_VCC

0.4

kHz

V
V

CRD_IO_A and CRD_IO_B Output Voltages

I/O_A = I/O_B = 0, I

= 500

24, 37

0.40

CRD_C4_A, CRD_C4_B Output Voltages

Output C4 High Level @ Irst = -200

Output C4 Low Level @ Irst = 200

CRD_C4_A, CRD_C4_B Rise and Fall time

C4 Rise Time @ C

out

= 30 pF

C4 Fall Time @ C

out

= 30 pF

trc

tfc

22, 39

CRD_VCC-0.5

CRD_VCC

0.4

100
100

V
V

ns
ns

CRD_C8_A, CRD_C8_B Output Voltages

Output C4 High Level @ Irst = -200

Output C4 Low Level @ Irst = 200

CRD_C8_A, CRD_C8_B Rise and Fall Time

C8 Rise Time @ C

out

= 30 pF

C8 RST Fall Time @ C

out

= 30 pF

trc

tfc

21, 40

CRD_VCC-0.5

CRD_VCC

0.4

100
100

V
V

Pull Up resistance, CS = Low, PWR_ON = High

CRD_IO_A
CRD_IO_B

OLA

OLB

24
37

14
14

20
20

35
35

Card Detection Bias Pull Up Current, Card A or Card B
CRD_DET_A, CRD_DET_B

DETA

DETB

20
41

15
15

Card Insertion/Extraction Negative Going Input Low Voltage

ILDETA

ILDETB

20
41

0
0

0.30 * V

bat

0.30 * V

bat

Card Detection Insertion/Extraction Digital Filtering Delay

CRD_DET_A
CRD_DET_B

dcina

dcinb

20
41

50
50

CARD_A or CARD_B short circuit current:

CRD_IO, CRD_RST, CRD_C4, CRD_C8
CRD_CLK

(According to ISO and EMV specifications)

Ishort

Ishortclk

15
70

NCN6004A

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DIGITAL DYNAMIC SECTION NORMAL OPERATING MODE

Rating

Symbol

Pin

Min

Typ

Max

Unit

Card Signal Sequence Interval, CRD_VCC_A and CRD_VCC_B:

CRD_IO_A, CRD_RST_A, CRD_CLK_A, CRD_C4_A, CRD_C8_A
CRD_IO_B, CRD_RST_B, CRD_CLK_B, CRD_C4_B, CRD_C8_B

seq

24, 23,
30, 37,

38, 31

0.5
0.5

2
2

Internal RESET Delay

reset

1.0

Internal STATUS Delay Time

ready

1.0

PWR_ON Low State Pulse Width (Figure 11), Assuming CRD_VCC
reservoir capacitor = 10

pwrlow

PWR_ON High State Pulse Width (Figure 11)

pwrset

200

PWR_ON Preset Delay (Figure 11)

pwrpre

5, 7, 8

300

PWR_ON Programming Hold Time (Figure 11)

pwrhold

5, 7, 8

100

PWR_ON to CARD_SEL Change Delay Time (Figure 12)

cseldly

5, 6, 8

100

PGM to PWR_ON Delay Time (Figure 12)

tpgmdly

5, 6, 8

300

PWR_ON internal Set/Reset Pulses Width (Figure 12)

tpwrp

DIGITAL DYNAMIC SECTION PROGRAMMING MODE

Rating

Symbol

Pin

Min

Typ

Max

Unit

Data Set-up Time, Time Reference = PGM, A0, A1, A2, A3, CARD_SEL,
and CS.

Data Signal Rise and Fall Time

smod

smodtr

8, 46, 1, 2,

3, 4, 5, 6

100

Data Hold Time, Time Reference = PGM, A0, A1, A2, A3, CARD_SEL,
and CS.

smod

smodtr

8, 46, 1, 2,

3, 4, 5, 6

100

ns
ns

Chip Select CS Low State Pulse Width
CS Signal Rise and Fall Time

wcs

rfcs

300

ns
ns

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PROGRAMMING AND STATUS FUNCTIONS

The NCN6004A includes a programming interface and a

status interface. Figure 4 illustrates the sequence one must
follow to enter and exit the programming mode. Table 1 and
Table 2 provide the logical functions associated with the

input and output signals. The parameters are latched upon
the rising edge of the PGM signal, the CS pin being held low.
Any number of programming sequences can be performed
while the CS pin is Low, but the minimum timings must be
observed.

CARD_SEL

Parameters are latched upon PGM rise slope

Figure 4. Programming Sequence

ÉÉÉÉÉÉ

ÉÉÉÉÉ

ÉÉÉÉ

ÉÉÉÉÉÉ

ÉÉÉÉÉ

ÉÉÉÉ

ÉÉÉÉÉÉ

ÉÉÉÉÉ

ÉÉÉÉ

ÉÉÉÉÉÉ

ÉÉÉÉÉ

ÉÉÉÉ

ÉÉÉÉÉÉ

ÉÉÉÉÉ

ÉÉÉÉ

sprg

wcs

hprg

PGM

Example:
Set CRD_VCC_A = 3.0 V

Example:
Set CRD_CLK_B = 1/8

On the other hand, since the programming data are latched

upon the rising edge of the PGM signal, the most up to date
selected card (using CARD_SEL = H or L) is used to
activate the associated card. Consequently, when both cards
must be updated with the same programmed content, a dual
PGM sequence must be carried out, changing the
CARD_SEL signal during the High level state of the PGM
pin.

Although selecting a card in possible during the same

Chip Select sequence (as depicted here above), the user must

make sure that no data will be present to a card not ready for
such a function. As a matter of fact, all the card signals are
routed to the selected card immediately after a CARD_SEL
change, the NCN6004A taking no further logic control prior
to activate the swap. To avoid any risk, one can run a
sequence with the selected card, return CS to High, change
the CARD_SEL according to the expected card selection,
and pull CS to Low to activate the selected card.

Table 1. Programming and Reading Basic Functions

Pin

Name

Select #A

Select V

ON/OFF

Program

CLOCK_IN

Poll Card Status

#A or #B

Poll I

Overload

#A or #B

ANLG_VCC

Input Voltage OK

STATUS

READ

0/1

CARD_SEL

0/1

PGM

0/1

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Table 2. Programming Functions

(Conditions at start-up are in Bold)

(HEX)

PGM

CARD_SEL

CRD_VCC

CRD_CLK

CRD_DET

CLOCK

SLOPE

1.80 V

3.0 V

5.0 V

SLOW

1.80 V

3.0 V

5.0 V

SLOW

1/1

1/2

1/4

1/8

1/1

1/2

1/4

1/8

START

STOPL

STOPH

FAST

START

STOPL

STOPH

FAST

CLK_D_A

CLK_D_B

CLK_D_B

CLK_D_A

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Table 3. Status Pins Data

STATE

(HEX)

PGM

CARD_SEL

STATUS #A

STATUS #B

Vcc_V

bat

_OK Pass = Low

VCC_OK Fail = High

CRD_VCC_A In Range
Pass = High Fail =Low

CRD_VCCA Overloaded
Pass = High Fail = Low

CRD_DET_A
Card Present = High

VCC_OK Pass = Low
VCC_OK Fail = High

CRD_VCC_B In Range
Pass = High Fail =Low

CRD_VCC_B Overloaded
Pass = High Fail = Low

CRD_DET_A
Card Present = High

*The STATUS register is not affected when the NCN6004A operates in any of the programming mode.

Initialized conditions upon start-up are depicted by bold characters in Table 2 and Table 4.

Vbat

2.10 V
2.00 V

2.70 V

3.30 V

Vbat_OK

Vbat STATUS

Max. ANLG_VCC Under Voltage

Min. ANLG_VCC Under Voltage

Typical ANLG_VCC Operating Voltage

The input power supply voltage monitoring applies to the card selected.

Figure 5. Reading ANLG_VCC Status (monitoring ANLG_VCC input voltage)

SYSTEM STATES UPON UPON START-UP

Table 4. Operating Conditions Upon Start-up

CRD_VCC_A

3.0 V

CRD_VCC_B

3.0 V

CRD_CLK_A

1/1 Ratio

CRD_CLK_B

1/1 Ratio

CRD_CLK_A

START (clock is valid)

CRD_CLK_B

START (clock is valid)

CRD_CLK_A

Low Speed Slope

CRD_CLK_B

Low Speed Slope

CLOCK Route

Direct (CLK_A

A, CLK_B

Depending upon the logic state at turn on present on

44, the system will run into a parallel mode

(MUX_MODE

L) or a multiplexed mode

(MUX_MODE = H). It is not possible to change the logic
state once the system is running.

Similarly, depending upon the logic state present pin 45,

the internal pull up resistors (I/O_A and I/O_B line) will be
either connected to ANLG_VCC voltage (EN_RPU = H) or
disconnected (EN_RPU = L). It is not possible to change this
operating condition once the system is running.

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PARALLEL/MULITPLEXED OPERATION MODES

The logic input MUX_MODE, pin 44, provides a way to

select the operation mode of the NCN6004A. Depending
upon the logic level, the device operates either in a parallel
mode (all the card pins, on the

mP side, are fully independent)

or in multiplexed mode (all the logic card pins, on the

side, share a common bus). Figure 6 shows a simplified
schematic of the multiplex circuit built in the NCN6004A
chip.

Figure 6. Simplified MUX_MODE Logic and Multiplex Circuit

11
12

RESET_A

C4_A

C8_A

CLK_IN_A

I/O_A

I/O_B

C8_B

C4_B

REST_B

CLK_IN_B

MUX_MODE

CARD_SEL

CARD_A

TING

BUFFERS

BUFFER

CARD_B

TING

I/O_A

BUFFER

I/O_B

CARD_B

CARD_A

CLK_A

CLK_B

CLOCK DIVIDERS

MULTIPLEXER

& MULTIPLEXER

In both case, the device is programmed by means of the

common logic controls pins (A0, A1, A2, A3, PGM,
PWR_ON, CARD_SEL and CS). On the other hand, the
logic status returned by the interface (STATUS pin 46) is
shared by the two channels and can be read independently
by setting CARD_SEL accordingly.

The card related signals connected on the

mC side are

multiplexed or independent, depending upon the
MUX_MODE state as described here below.

MUX_MODE = Low

PARALLEL MODE

When pin 44 is low, the device operates in the parallel

mode. The transfer gate Q4 and the multiplexer circuit are
disconnected and all the data will be carried out through their
respective paths. The switches Q1, Q2 and Q3 are flipped to
the B position, thus providing a direct connection from port
B control signals to CARD_B

All the CARD_A and CARD_B signals are independent

and both cards can operate simultaneously, the data

transaction can take place at the same time and processed
independently. Of course, the microcontroller must have the
right data bus available to handle this process.

However, it is not possible to change the operating mode

once the system has been started. If such a function is
needed, one must pull down the related NCN6004A power
supply, change the MUX_MODE logic level, and re-start
the interface.

MUX_MODE = High

MULTIPLEXED MODE

When pin 44 is High, the device operates in a multiplexed

mode and all the card signals are shared between CARD_A
and CARD_B, except the input clocks which are
independent at any time. The RST_B, C4_B and C8_B pins
are preferably left open at PCB level. The I/O_B pin must be
left open and cannot be connected to any external signal or
bias voltages.

The transfer gate Q4 is switched ON and, depending upon

the CARD_SEL logic level, the I/O data will be transferred

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to either CARD_A or CARD_B. It is neither possible to
connect directly I/O_A to I/O_B nor to connect the I/O_B
pin to ground or voltage supply.

The multiplexer is activated and the CARD_SEL signal is

used to select the card in use for a given transaction. The
switches Q1, Q2 and Q3 and swapped to the A position, thus
providing a path for the control signals applied to the
CARD_A side.

When the CARD_SEL signal flips from one card to the

other, the previous logic states of the on going card are
latched in the chip and the related output card pin are
maintained at the appropriate levels. When the system
resumes to the previous card, the latches return to the
transparent operation and the signals presented by the

take priority over the previously latched states.

On the other hand, the input clocks (CLK_IN_A and

CLK_IN_B) are maintained independent and can be routed
to either CARD_A or CARD_B according to the
programming functions given in Table 2.

CARD POWER SUPPLY TIMING

When the PWR_ON signal is high, the associated

CRD_VCC_A or CRD_VCC_B power supply rise time
depends upon the current capability of the DC/DC converter
together with the external inductors L1/L2 and the reservoir
capacitor connected across each card power supply pin and
GROUND.

On the other hand, at turn off, the CRD_VCC_A and

CRD_VCC_B fall times depend upon the external reservoir
capacitor and the peak current absorbed by the internal
NMOS device built across each CRD_VCC_A/
CRD_VCC_B

and GROUND. These behaviors are depicted

by Figure 7, assuming a 10

mF output capacitor.

Since none of these parameters can have infinite values,

the designer must take care of these limits if the t

or the

OFF

provided by the data sheets does not meet his

requirement.

CRD_VCC = 5 V

CRD_VCC = 4.75 V

CRD_VCC = 0.40 V

Turn ON

Shut OFF

500

s Max

250

s Max

Figure 7. Card Power Supply Turn ON and Shut

OFF Typical Timings

POWER DOWN OPERATION

The power down mode can be initiated by either the

external MPU or by the internal error condition. The
communication session is terminated immediately,
according to the ISO7816-3 sequence. On the other hand,
the MPU can run the Stand By mode by forcing CS = H,
leaving the chip in the previous operating mode.

When the card is extracted, the interface will detect the

operation and will automatically run the Power Down
Sequence of the related card as described by the ISO/CEI
7816-3 sequence depicted in Figure 8 and illustrated by the
oscillogram in Figure 9.

CRD_VCC

CRD_RST

CRD_CLK

CRD_IO

CARD EXTRACTION DETECTED

CRD_C4

CRD_C8

CRD_DET

Internal Delay
400 ns typ.

Figure 8. Card Power Down Sequence

Force RST to Low
Force CLK to Low, unless it is already in this state
Force C4 and C8 to Low
Force CRD_IO to Low
Shut Off the CRD_VCC Supply

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CARD DETECTION

The card detector circuit provides a constant low current to
bias the CRD_DET_A and CRD_DET_B pins, yielding a
logic High when no card is present and the external switch is
Normally Open type. The internal logic associated with pins
20 and 41 provides a programmable selection of the slope
card detection. The transition is filtered out by the internal
digital filter circuit, avoiding false interrupt. In addition to
the typical 50

ms delay, the MPU shall provide an additional

delay to cope with the mechanical stabilization of the card
interface (typically 1 ms), prior to valid the CRD_VCC_A or
CRD_VCC_B supply.

When a card is inserted, the detector circuit asserts

INT = Low as depicted before, the external

mP being

responsible to clear the interrupt signal, taking the
necessaries actions. When the NCN6004A detects a card
extraction, the power down sequence is automatically
activated for the related interface section, regardless of the
PWR_ON state, and the INT pin is asserted Low. It is up to
the external MPU to clear this interrupt by pulsing the CS
pin.

CRD_DET_A

STATUS

INTERRUPT

CARD IDENTIFICATION

CLEAR INTERRUPT
CARD PRESENT: STATUS = 1

CARD NOT PRESENT: STATUS = 0

CARD EXTRACTED

s < T < 150

High

s < T < 150

CLEAR INTERRUPT

CARD_SEL

High = Card A

IRRELEVANT

Figure 11. Typical Interrupt Sequence

PGM

INT

ACKNOWLEDGE

& PROCESSING

The interrupt signal can be cleared either by a positive

going slope on the Chip Select pin as depicted in Figure 11,
or by forcing the PWR_ON signal High (keeping CS = Low)
for the related card.

The polarity of the card detection switch can be either
Normally Open or Normally Close and is software
controlled as defined here below and in Table 2.

Table 5. Card Detection Polarity

PGM

CARD_SEL

CRD_DET_A

CRD_DET_B

Qn -1

Normally Open

Qn -1

Normally Close

Qn -1

Normally Open

Bn -1

Normally Close

*The polarity change is validated upon the next positive PGM transient.

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POWER MANAGEMENT

The main purpose of the power management is to provides

the necessary output voltages to drive the 1.80 V, 3.0 V or
5.0 V smart card types. On top of that, the DC/DC converter
efficiency must absorb a minimum current on the V

bat

supply.

Beside the power conversion, in the Stand by mode

(PWR_ON = L), the power management provides energy to
the card detection circuit only. All the card interface pins are
forced to ground potential, saving as much current as
possible out of the battery supply.

In the event of a power up request coming from the

external MPU (CARD_SEL =H/L, PWR_ON = H, CS = L),
the power manager starts the DC/DC converter related to the
selected interface section.

When the selected section (either CRD_VCC_A or

CRD_VCC_B) voltage reaches the programmed value
(1.8 V, 3.0 V or 5.0 V), the circuit activates the card signals
according to the following sequence:

CRD_VCC_x

CRD_IO_x

CRD_C4_x

CRD_C8_x

CRD_CLK_x

CRD_RST_x

The logic level of the data lines are asserted High or Low,

depending upon the state forced by the external MPU, when

the start-up sequence is completed. Under no situation the
NCN6004A shall automatically launch a smart card ATR
sequence.

At the end of the transaction, asserted by the MPU

(CARD_SEL = H/L, PWR_ON = L, CS = L), or under a card
extraction, the ISO7816-3 power down sequence takes
place:

CRD_RST_x

CRD_CLK_x

CRD_C4_x

CRD_C8_x

CRD_IO_x

CRD_VCC_x

When CS = H, the bi-directional I/O lines (pins 9 and 19)

are forced into the High impedance mode to avoid signal
collision with any data coming from the external MPU.

OUTPUT VOLTAGE PROGRAMMING

The internal logic provides a reliable circuit to activate

any of the DC/DC converters safely. In particular, the Turn
On/Turn Off of these converters is edge sensitive and
controlled by the rising/falling edges of the PWR_ON signal
applied with Chip Select pin Low. The CARD_SEL signal
is used to select either CRD_VCC_A or CRD_VCC_B as
defined by the functions programming in Table 2.

PWR_ON

CRD_VCC Rise Time

CRD_VCC No Change

CRD_VCC_A PWR DOWN

VCCtoff

CARD_SEL

CRD_VCC_A

CRD_VCC_B

SET

RESET

VCCton

see note

Note : minimum 1 ms delay before to send a power Off command to the same

selected output is recommended.

Figure 12. Card Power Supply Controls

Although it is possible to change the output voltage

straightly from 5.0 V to 1.80 V, care must be observed as the
stabilization time will be relatively long if no current is
absorbed from the related output pin.

According to the typical sequence depicted, it is not

possible to program simultaneously the two DC/DC

converters, but two separate sequences must take place. On
top of that, since the circuit is edge sensitive, the PWR_ON
signal must present such a transient when a given state is
expected for the converter. The PWR_ON and CS timings
definitions are given in Figure 13.

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PWR_ON

tpwrhold

tpwrlow

CARD_SEL

SET

RESET

tpwrpre

tpwrset

tpwrp

NOTE:

tpwrset: This delay is necessary to latchup the PWR_ON condition
and does not represent the CRD_VCC output voltage rise time.
tpwrlow: This delay includes the internal ISO7816-3 power down
sequence to make sure the DC/DC converter is fully deactivated.

Figure 13. Power On Sequence Timings

PWR_ON

tpgmdly

CARD_SEL

tcseldly

tpwrw

Programming

Chip Selected

tpwrhold

NOTE:

tpwrw: This delay represents the minimum pulse width needed
to write the PWR_ON status into the associated DC/DC latch

Figure 14. Power On and CARD_SEL Sequence Timings

Sequence

PGM

DC/DC CONVERTER

The power conversion is carried out either in step up or

step down mode. The operation is fully automatic and,
beside the output voltage programming, does not need any
further adjustments.

The simplified DC/DC converter, given in Figure 15, is

based on a full bridge structure capable to handle either step
up or step down power supply using an external inductor.
This structure brings the capability to operate from a wide
range of input voltage, while providing the accurate 1.80 V,
3.0 V or 5.0 V requested by the smart cards. Beside the
accuracy, the major aim of this structure is the high
efficiency necessary to save energy taken from the battery.
On the other hand, using two independent converters
provides a high flexibility and prevent a total system crash
in the event of a failure on one of the card connected to the
interface.

OPERATION

NOTE:

Described operation makes reference to
CARD_A and can be applied to CARD_B.

The system operates with a two cycles concept:

1. Cycle 1: Q15 and Q4 are switched ON and the

inductor L1 is charged by the energy supplied by
the external battery. During this phase, the pairs
Q1/Q16 and Q2/Q3 are switched OFF.
The current flowing into the two MOSFET Q1 and
Q4 is internally monitored and will be switched OFF
when the Ipeak value (depending upon the
programmed output voltage value) is reached. At
this point, Cycle 1 is completed and Cycle 2 takes
place. The ON time is a function of the battery
voltage and the value of the inductor network (L and
Zr) connected across pins 26/27 and 34/35.
A 4

ms time out structure makes sure the system does

run in a continuous Cycle 1 loop.

2. Cycle 2: Q1 and Q16 are switched ON and the

energy stored into the inductor L1 is dumped into
the external load through Q16. During this phase,
the pair Q15/Q4 and the pair Q2/Q3 are switched
OFF.
The current flow period is constant (900 ns typical)
and Cycle 1 repeats after this time if the CRD_VCC
voltage is below the specified value.

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When the output voltage reaches the specified value
(1.80 V or 3.0 V or 5.0 V), Q1 and Q16 are switched
OFF immediately to avoid over voltage on the output
load. In the mean time, the two extra NMOS Q2 and
Q3 are switched ON to fully discharge any current
stored into the inductor, avoiding ringing and
voltage spikes over the system. Figure 16 illustrates
the theoretical basic waveforms present in the
DC/DC converter.

The control block gives the logic states according to the

bits provided by the external

mP. These controls bits are

applied to the selected DC/DC converter to generate the
programmed output voltage. The MOS drive block includes
the biases necessaries to drive the NMOS and PMOS
devices as depicted in the block diagram given Figure 15.

Vref

LOGIC CONTROL

PWR_ON

Overload

VCC_OK

Voltage Regulation

GND

Vcc

Vref_1.8/3/5 V

PGM

CARD_SEL

DC/DC MUL

TIPLEXED CONTROLS

PWR_ON

Q15

Q16

Vcc

PWR_GND

CRD_VCC_A

GND

MIXED LOGIC /

ANALOG BLOCK

G_Q1

G_Q2

G_Q3

G_Q4

G_HIZ

GND

G_Q7

out

5.0 V

GND

Figure 15. Basic DC/DC Converter Diagram

GND

Vref

LOGIC CONTROL

PWR_ON

Overload

VCC_OK

Voltage Regulation

GND

Vcc

Vref_1.8/3/5 V

Q11

Q17

Q18

Vcc

PWR_GND

CRD_VCC

GND

MIXED LOGIC /

ANALOG BLOCK

G_Q1

G_Q2

G_Q3

G_Q4

G_HIZ

GND

G_Q7

Q10

Q12

out

Q14

Q13

3.0 V

5.0 V

GND

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Since the output inductor L1 and the reservoir capacitor

C1 carry relative high peak current, low ESR devices must
be used to prevent the system from poor output voltage
ripple and low efficiency. Using ceramic capacitors, X5R or
X7R type, are recommended, splitting the 10

mF in two

separate parts when there is a relative long distance between

the CRD_VCC_x output pin and the card VCC input. On the
other hand, the inductor shall have an ESR below 1.0

W to

achieve the high efficiency over the full temperature range.
However, inductor with 2.0

ESR can be used when a slight

decrease of the efficiency is acceptable at system level.

Ton Toff

CRD_VCC Charged

Charge CRD_VCC

Next CRD_VCC Charge

Q1 / Q4

Q2 / Q3

(Time is not to scale)

CRD_VCC

CRD_VCC Voltage Regulated

Ipeak

ripple

Q5/Q6

Figure 16. Theoretical DC/DC Operating

When the CRD_VCC is programmed to zero volt, or when

the card is extracted from the socket, the active pull down Q5
rapidly discharges the output reservoir capacitor, making
sure the output voltage is below 0.40 V when the card slides
across the contacts.

Based on the experiments carried out during the

NCN6004A characterization, the best comprise, at time of
printing this document, is to use two
4.7

mF/10 V/ceramic/X7R capacitor in parallel to achieve

the CRD_VCC filtering. The ESR will not extend 50 m

over the temperature range and the combination of standard
parts provide an acceptable 20% to +20% tolerance,
together with a low cost. Table 6 shows a quick comparison
between the most common type of capacitors. Obviously,
the capacitor must be SMD type to achieve the extremely
low ESR and ESL necessary for this application.

Figure 17 illustrates the CRD_VCC ripple observed in the

NCN6004A demo board running with X7R ceramic
capacitors.

Table 6. Ceramic/Electrolytic Capacitors Comparison

Manufacturer

Type/Series

Format

Max Value

Tolerance

Typ. Z @ 500 kHz

MURATA

CERAMIC/GRM225

0805

F/6.3 V

-20% /+20%

30 m

MURATA

CERAMIC/GRM225

0805

4.7

F/6.3 V

-20% /+20%

30 m

VISHAY

Tantalum/594C/593C

1206

F/16 V

450 m

VISHAY

Electrolytic/94SV

1812

F/10 V

-20%/+20%

400 m

Miscellaneous

Electrolytic Low Cost

1812

F/10 V

-35%/+50%

2.0

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CLOCK DIVIDER

The main purpose of the built in clock generator is four
folds:

1. Adapts the voltage level shifter to cope with the

different voltages that might exist between the
MPU and the Smart Card

2. Provides a frequency division to adapt the Smart

Card operating frequency from the external clock
source.

3. Control the clock state according to the smart card

specification.

4. Provides an input clock re-routing to route the

CLOCK_IN_A and CLOCK_IN_B signals to
either CRD_CLK_A or CRD_CLK_B output pins.

In addition, the NCN6004A adjusts the signal coming

from the microprocessor to get the Duty Cycle window as
defined by the ISO7816-3 specification.

The logic input pins CARD_SEL, A0, A1, PGM, I/O and

RESET fulfill the programming functions when both PGM
and CS are Low. The clock input stage (CLOCK_IN) can
handle a 40 MHz frequency maximum, the divider being
capable to provide an 1:8 ratio. Of course, the ratio must be
defined by the engineer to cope with the Smart Card
considered in a given application and, in any case, the output
clock (CRD_CLK_A and CRD_CLK_B) shall be limited to
20 MHz maximum when the system is considered to operate
over the full temperature range.

PGM

CLOCK_IN_B

CRD_CLK_A

LEVEL SHIFTER

& CONTROL

CRD_VCC_A

CARD_A & CARD_B CLOCK

CRD_VCC_A

CARD_SEL

CRD_CLK_B

LEVEL SHIFTER

& CONTROL

CRD_VCC_B

CARD_A

CARD_B

DC/DC BLOCK_A

CRD_VCC_B

DC/DC BLOCK_B

CLOCK_IN_A

CLOCK_A

DIVIDER

CLOCK_AB DIVIDER

MUX_A&B

LOGIC

CONTROL

Figure 24. Simplified Frequency Divider and Programming Functions

In order to avoid any duty cycle out of the frequency smart

card ISO7816-3 and EMV specifications, the clock divider
is synchronized by the last flip flop, thus yielding a constant
50% duty cycle, regardless of the divider ratio.

Consequently, the output CRD_CLK_A or CRD_CLK_B
frequency division can be delayed by eight CLOCK_IN
pulses and the microcontroller software must take this delay
into account prior to launch a new data transaction.

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The input clock A and B can be re routed to either

CRD_CLK_A or CRD_CLK_B output pins by using the
programming function as defined in Table 2 and Table 7. The
clock signals can have any frequency value necessary to
handle a given type of card (asynchronous or synchronous).

These clock signals can be multiplexed at any time, but the
system must be locked in a safe state prior to make such a
change. In particular, the designer must make sure that A and
B cards can support such a hot change prior to change the
related clocks.

Table 7. Programming Clock Routing

STATE

PGM

CARD_SEL

CRD_CLK_A

CRD_CLK_B

CLK_D_A

Default

CLK_D_B

CLK_D_B

Default

CLK_D_A

On the other hand, the slope of the CRD_CLK_x signal

can be set to either FAST or SLOW, depending upon the

frequency of the output clock. This selection is achieved by
programming the chip according to Table 8.

Table 8. Output Clock Slope Selection

STATE

PGM

CARD_SEL

CLOCK SLOPE

$03

SLOW

Default

$0B

FAST

$03

SLOW

Default

$0B

FAST

Figure 30. Typical Rise and Fall Time in Fast and

Slow Operating Mode

PARALLEL OPERATION

When two or more NCN6004A parts operate in parallel on

a common digital bus, the Chip Select pin allows the
selection of one chip from the bank of the paralleled devices.
Of course, the external MPU shall provide one unique CS
line for each of the NCN6004A considered interface. When
a given interface is selected by CS = L, all the logic inputs
becomes active, the chip can be programmed or/and the
external card can be accessed. When CS = H, all the input
logic pins are in the high impedance state, thus leaving the
bus available for other purpose.
The pull up resistors connected on each logic input lines on
the MPU side (see block diagram in Figure 30), can be either
activated (connected to V

) or disconnected, depending

upon the logic state present at EN_RPU, pin 45. When these
resistors are disconnected, it is the system responsibility to
set up the external pull up resistors according to the
application's requirements.

When the device operates in the multiplexed mode

(MUX_MODE = High), the internal card #B pull up
resistors are connected to V

, regardless of the EN_RPU

logic state.

On the other hand, when CS = H, the CRD_IO and

CRD_RST hold the previous I/O and RESET logic state, the
CRD_CLK being either active or stopped and the
CRD_VCC output voltage will maintain is previous value,
according to the programmed state forced by the MPU.

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Figure 31. Parallel Operation Wiring

MUX_MODE = Low

RESET_A

C4_A

C8_A

CLK_IN_A

I/O_A

I/O_B

C8_B

C4_B

RESET_B

CLK_IN_B

MUX_MODE

CARD_SEL

BUFFERS

BUFFER

I/O_A

BUFFER

I/O_B

CARD_B

CARD_A

CLK_A

CLK_B

CLOCK GEN.

MULTIPLEX &

CLOCK DIVIDER

CARD

GND

LOGIC

CONTROL

POR

CTL

MICRO CONTROLLER

When the chip operates in the parallel mode, all the logic

signals must be independently controlled by the
microcontroller as depicted in Figure 31. The MUX_MODE
pin must be hardwired to VCC and it cannot be changed

during an operation of the chip. Beside this parameter, the
user must select to force or not the internal pull up resistors
as defined by the EN_RPU logic state.

Figure 32. Multiplexed Operation Wiring

MUX_MODE = High

RESET_A

C4_A

C8_A

CLK_IN_A

I/O_A

I/O_B

C8_B

C4_B

RESET_B

CLK_IN_B

MUX_MODE

CARD_SEL

BUFFERS

BUFFER

I/O_A

BUFFER

I/O_B

CARD_B

CARD_A

CLK_A

CLK_B

CLOCK GEN.

POR

CTL

MICRO CONTROLLER

MULTIPLEX &

CLOCK DIVIDER

CARD

VCC

LOGIC

CONTROL

In the multiplexed mode, the microprocessor CARD_B

side pins are not connected, the logic signals and the I/O line
being shared with CARD_A associated with the CRD_SEL
control bit: Figure 32. A key point is to make sure there is no
connection associated with the I/O_B pin since this pin is
internally shared with the I/O line transaction. The
CLK_IN_A and CLK_IN_B signals are independent and
can be routed to any of the card thanks to the built-in clock
multiplexer.

DATA I/O LEVEL SHIFTER

The built in structure provides a level shifter on each card

output signals, the I/O line being driven differently as
depicted in Figure 33. Since the NCN6004A can operate in

either a multiplexed or parallel mode, provisions have been
made to route the I/O_A input pin to either CARD_A or
CARD_B.

In both case, the I/O pins are driven by an open drain

structure with a 20 k

W pull up resistor as shown Figure 33.

To achieve the 0.80

ms maximum rise time requested by the

EMV specifications, an accelerator circuit is added on both
side of each I/O line. These pulsed circuits yield boost
current to charge the stray capacitance, thus accelerating the
positive going slope of the I/O signal. On the other hand, the
active pull down NMOS device Q5 provides a low
impedance to ground during the battery up and DC/DC
start-up phase, avoiding any uncontrolled voltage spikes on
the I/O lines.

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MUX_MODE = Low

PARALLEL OPERATION

The bi-directional switch Q9 is OFF and the I/O signals

are routed straightforward to their appropriate outputs. The
two I/O lines can operate simultaneously, depending upon
the

mP capabilities, regardless of the CARD_SEL signal

logic level.

The pull up resistors, on the

mP side of each I/O line, can

be connected or not as defined by the EN_RPU signal.

MUX_MODE = High

MULTIPLEXED OPERATION

The bi-directional switch Q9 is ON and the I/O_A pin is

used to handle data for CARD_A and CARD_B. The signal

is routed to the appropriate card by means of the
CARD_SEL logic signal. In this mode, the I/O_B pin 19
must be left open since the internal data signal will be
present on this pin.

Moreover, since R1 and R3 are in parallel, the pull up

resistor R1 is automatically disconnected to maintain the I/O
line impedance to 20 k

W (typical), what ever be the

EN_RPU logic level. This feature makes sure the current
flowing trough the external card is limited to 500

mA during

a low level state.

CRD_I/O_A

BI-DIRECTIONNAL DATA TRANSFERT

ANLG_VCC

CRD_VCC_A

I/O_A

I/O_B

CRD_I/O_B

GND

CONTROL LOGIC

BI-DIRECTIONNAL DATA TRANSFERT

Q11

Q10

CONTROL LOGIC

CARD_SEL

PWR_ON

CRD_VCC_B

MUX_MODE

EN_RPU

Q10

Q11

& Level Shifter

CRD_VCC_A

ANLG_VCC

Figure 33. Dual Bi-directional I/O Line Level Shifter and Multiplex

GND

CRD_VCC_B

ANLG_VCC

PGM

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NOTE:

Both sides of the interface run with open drain load
(worst case condition)

Figure 34. Typical I/O Rise and Fall Time

ESD Protection

The NCN6004A includes silicon devices to protect the

pins against the ESD spikes voltages. To cope with the
different ESD voltages developed across these pins, the built
in structures have been designed to handle either 2 kV, when
related to the microcontroller side, or 8 kV when connected
with the external contacts. Practically, the CRD_RST,
CRD_CLK, CRD_IO, CRD_C4 and CRD_C8 (both A and
B sections) pins can sustain 8 kV, the maximum short circuit
current being limited to 15 mA. The CRD_VCC_A and
CRD_VCC_B pins have the same ESD protection, but can
source up to 65 mA continuously each, the absolute
maximum current being 150 mA per section.

Security Features

In order to protect both the interface and the external smart

card, the NCN6004A provides security features to prevent
catastrophic failures as depicted here after.

Pin Current Limitation: in case of a short circuit to

ground, the current forced by the device is limited to 10 mA
for any pins, except CRD_CLK_A and CRD_CLK_B pins

which are both limited to 70 mA. No feedback is provided
to the external MPU.

DC/DC Operation: The internal circuit continuously

senses the CRD_VCC_A and CRD_VCC_B voltages and,
in the case of either over or under voltage situation, update
the STATUS register accordingly. This register can be read
out by the MPU but no interrupts are activated.

DC/DC Overload: When an overload is sensed across the

CRD_VCC_A or CRD_VCC_B output, during either the
power on sequence or when the system was previously
running, the NCN6004A generates an interrupt by pulling
down the INT pin. It is up to the microcontroller to identify
the origin of the overload by reading the STATUS pin
accordingly.

Battery Voltage: Both the Positive going and the

Negative going voltage are detected by the NCN6004A, a
POWER_DOWN sequence and the STATUS register being
updated accordingly. The external MPU can read the
STATUS pin to take whatever is appropriate to cope with the
situation. The NCN6004A does not provide any further
internal voltage regulation.

NCN6004A

http://onsemi.com

TEST BOARD SCHEMATIC DIAGRAM

TP1

Det_B

4.7 k

SWITCH

CLK_A

CLK_B

TP6

RST_B

TP2

CLK_B

TP3

C4_B

TP4

C8_B

TP5

IO_B

TP12

Det_A

TP7

RST_A

TP8

CLK_A

TP10

C8_A

TP9

C4_A

TP11

IO_A

C12

PWR_ON

ST
A

TUS

CARD_SEL

PGM

I/O_A

RESET_A

C4_A

C8_A

CLK_IN_A

PWR_VCC_A

PWR_GND

CRD_DET_A

CRD_VCC_A

CRD_CLK_A

CRD_IO_A

CRD_DET_B

CRD_VCC_B

CRD_CLK_B

CRD_IO_B

CRD_RST_A

CRD_RST_B

L2a

L1a

L1b

L2b

EN_RPU

CRD_C4_A

CRD_C8_A

CRD_C4_B

CRD_C8_B

PWR_VCC_B

PWR_GND

MUX_MODE

INT

ANLG_GND

ANLG_VCC

ANLG_GND

CLK_IN_B

C8_B

C4_B

RESET_B

I/O_B

NCN6004

I/O 7

Swa 10

Swb

C4 4

CLK 3

RST 2

Vcc 1

GND 5

VPP

ISO7816

SMARTCARD_B

I/O

Swa

Swb

4 CLK

3 RST

Vcc

GND

VPP

ISO7816

J12

SMARTCARD_A

C11

100 nF, X7R

4.7uF, X7R

+ C6

R15

10 k

R12

1.5 k

R11

1.5 k

R14

10 k

R13

1.5 k

R10

1.5 k

R16

C10

C_CLK_B

R17

C13

220 nF

C14

220 nF

TP20

TP21

TP19

TP18

TP17

Card_Sel

TP16

PGM

TP15

TP23

Status

TP24

INT

TP22

PWR_ON

CONTROL & I/O

1.5k

VCC

GND

VCC

GND

VCC

8x10k

GND

MPU_CLK

EXT_CLK

GND

MPU_CLK

EXT_CLK

GND

VCC

LED

GND

CARD_A_INS

J10

CRD_VCC_A

2N2222

GND

CRD_VCC_A

CRD_VCC_B

GND

CRD_B_INS

GND

2N2222

CRD_VCC_B

CARD_SEL

PGM

PWR_ON

MUX_MODE

EN_RPU

ST
A

TUS

INT

I/O_A

RESET_A

C4_A

C8_A

CLK_IN_A

CLK_IN_B

C8_B

C4_B

RESET_B

I/O_B

IO_A

VCC_A

RST_A

CLK_A

J13

GROUND

1
2

J14

GROUND

J11 GROUND

100 nF

GND

VCC

VCC_B

TP13

I/O_A

TP14

I/O_B

ST
A

TUS

CLK_IN

IO_B

GND

Figure 35. Test Board Schematic Diagram

4.7

F, X7R

4.7

F, X7R

4.7

F, X7R

GND

NCN6004A

http://onsemi.com

PIN FUNCTIONS AND DESCRIPTION

. . . . . . .

POWER SUPPLY SECTION

. . . . . . . . . . . . . . . .

DIGITAL INPUT SECTION @ 2.70 < V

< 5.50V,

Normal Operating Mode

. . . . . . . . . . . . . . . . . . .

CARD INTERFACE SECTION @ 2.70 < V

< 5.50V,

Normal Operating Mode

. . . . . . . . . . . . . . . . . . .

DIGITAL DYNAMIC SECTION NORMAL OPERATING
MODE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DIGITAL DYNAMIC SECTION PROGRAMMING MODE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PROGRAMMING AND STATUS FUNCTIONS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSTEM STATES UPON START UP

. . . . . . . .

PARALLEL/MULTIPLEXED OPERATION MODES

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CARD POWER SUPPLY TIMING

. . . . . . . . . . .

POWER DOWN OPERATION

. . . . . . . . . . . . . .

CARD DETECTION

. . . . . . . . . . . . . . . . . . . . . . .

POWER MANAGEMENT

. . . . . . . . . . . . . . . . . .

OUTPUT VOLTAGE PROGRAMMING

. . . . . . .

DC/DC CONVERTER

. . . . . . . . . . . . . . . . . . . . . .

CLOCK DIVIDER

. . . . . . . . . . . . . . . . . . . . . . . . .

PARALLEL OPERATION

. . . . . . . . . . . . . . . . . .

DATA I/O LEVEL SHIFTER

. . . . . . . . . . . . . . . . .

ESD PROTECTION

. . . . . . . . . . . . . . . . . . . . . . .

SECURITY FEATURES

. . . . . . . . . . . . . . . . . . . .

TEST BOARD SCHEMATIC DIAGRAM

. . . . . .

Figures

Figure 1: Pin Diagram

. . . . . . . . . . . . . . . . . . . .

Figure 2: Typical Applications

. . . . . . . . . . . . .

Figure 3: Block Diagram

. . . . . . . . . . . . . . . . . .

Figure 4: Programming Sequence

. . . . . . . . .

Figure 5: Reading ANLG_VCC Status

. . . . . .

Figure 6: Simplified MUX_MODE Logic and
Multiplex CIrcuit

. . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 7: Card Power Supply Turn ON and
Shut OFF Typical Sequence

. . . . . . . . . . . . . . .

Figure 8: Card Power Down Sequence

. . . . .

Figure 9: Power Down Sequence

. . . . . . . . . .

Figure 10: Power Down Sequence: Timing Details

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 11: Typical Interrupt Sequence

. . . . . .

Figure 12: Card Power Supply Controls

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 13: Power On Sequence Timing

. . . . .

Figure 14: Power On and CARD_SEL Sequence
Timings

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 15: Basic DC/DC Converter Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 16: Theoretical DC/DC Operating

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 17: Typical CRD_VCC Ripple Voltage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 18: Typical Card Voltage Turn ON and Start-up

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 19: Typical Card Supply Turn OFF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 20: CRD_VCC Efficiency as a Function of the
Input Supply Voltage

. . . . . . . . . . . . . . . . . . . . .

Figure 21: Typical Output Voltage Ripple

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 22: Output Current Limit

. . . . . . . . . . .

Figure 23: Output Current Limit as a Function of the
Temperature

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 24: Simplified Frequency Divider and
Programming Functions

. . . . . . . . . . . . . . . . . .

Figure 25: Clock Programming Timings

. . . .

Figure 26: Card Clock

Divider Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 27: Clock Divider: 8 to 1 Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 28: Clock Divider Timing Details

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 29: Clock Divider: Run to Stop High Operation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 29: Typical Rise and Fall Time in Fast and Slow
Operating Mode

. . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 30: Parallel Operation Wiring

MUX_MODE = High

. . . . . . . . . . . . . . . . . . . . . . .

Figure 31: Multiplexed Operation Wiring

MUX_MODE = Low

. . . . . . . . . . . . . . . . . . . . . . .

Figure 32: Dual Bi-directional I/O line Level Shifter
and Multiplex

. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 33: Typical I/O Rise and Fall Time

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 34: Test Board Schematic Diagram

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 35: Demo Board PCB Top Overlay

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 37: Demo Board PCB Top Layer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Figure 38: Demo Board PCB Bottom Layer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 1 :Programming and Reading Basic Functions

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 2: Programming Functions

. . . . . . . . . .

Table 3: Status Pins Data

. . . . . . . . . . . . . . . . .

Table 4: Operating Conditions Upon Start-up

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 5: Card Detection Polarity

. . . . . . . . . . .

Table 6: Ceramic/Electrolytic Capacitors Comparison

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 7: Programming Clock Routing

. . . . . .

Table 8: Output Clock Slope Selection

. . . . .

NCN6004A

http://onsemi.com

ABBREVIATIONS

L1a and L1b

DC/DC external inductor #A

CRD_VCC_A

Interface IC Card #A Power
Supply Line

L2a and L2b

DC/DC external inductor #B

CRD_CLK_A

Interface IC Card #A Clock In-
put

Cout

Output Capacitor

CRD_RST_A

Interface IC Card #A RESET
Input

CRD_VCC

Card Power Supply Input

CRD_IO_A

Interface IC Card #A Data link

VCC

MPU Power Supply Voltage

CRD_C4_A

Interface IC Card #A Data
Control

Icc

Current at card VCC pin

CRD_C8_A

Interface IC Card #A Data
Control

Class A

5 V Smart Card

CRD_DET_A

Card insertion/extraction
detection

Chip Select

CARD_SEL

Card #A/B Selection bit

CRD_CLK_B

Interface IC Card #B Clock In-
put

CRD_IO_B

Interface IC Card #B Data link

EN_RPU

Enable/Disable internal pull up

CRD_IO_B

Interface IC Card #B RESET
Input

PGM

Chip Programming Mode

EMV

Euro Card Master Card Visa

ISO

International Standards Orga-
nization

Class B

3 V Smart Card

CRD_VCC_B

Interface IC Card #B Power
Supply Line

ANLG_VCC = VCC = V

bat

Input Voltage

CRD_C4_B

Interface IC Card #B Data
Control

PWR_ON

Chip Power On bit

CRD_C8_A

Interface IC Card #B Data
Control

MUX_MODE

Card Multiplex or Parallel Op.

CRD_DET_B

Card insertion/extraction
detection

Smart Card Data transfer pro-
cedure by bytes

Smart Card Data transfer pro-
cedure by strings

Microcontroller

NCN6004A

http://onsemi.com

48 LEADS, TQFP EP

CASE 932F-01

ISSUE A

ÉÉÉÉ

ÇÇÇ

T-U

0.200

4 PL

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M,

1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD

AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD

EXITS THE PLASTIC BODY AT THE BOTTOM OF THE

PARTING LINE.

4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM

PLANE AB.

5. DIMENSIONS S AND AB TO BE DETERMINED AT

SEATING PLANE AC.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER

SIDE. DIMENSIONS A AND B DO INCLUDE MOLD

MISMATCH AND ARE DETERMINED AT DATUM PLANE

AB.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL NOT

CAUSE THE D DIMENSION TO EXCEED 0.350.

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076.

9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

DIM

MIN

MAX

MILLIMETERS

7.000 BSC

3.500 BSC

7.000 BSC

3.500 BSC

0.900

1.100

0.170

0.270

0.950

1.250

0.170

0.230

0.500 BSC

0.050

0.150

0.090

0.200

0.500

0.700

12 REF

0.090

0.160

0.250 BSC

0.150

0.250

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

T-U

0.200

4 PL

DETAIL Y

0.080

C E

TOP & BOT

0.250

GAUGE PLANE

T, U, Z

DETAIL Y

F
D

SECTION AE-AE

T-U

0.080

EXPOSED PAD

5.000 BSC

DETAIL AD

NOTE 9

SEATING PLANE

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

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2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local
Sales Representative.

NCN6004A/D

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Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NCN6004AFTBR2

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