Semiconductor Components Industries, LLC, 2004
August, 2004 - Rev. 4
1
Publication Order Number:
NCP1030/D
NCP1030, NCP1031
Low Power PWM Controller
with On-Chip Power Switch
and Startup Circuits for
48 V Telecom Systems
The NCP1030 and NCP1031 are a family of miniature high-voltage
monolithic switching regulators with on-chip Power Switch and Startup
Circuits. The NCP103x family incorporates in a single IC all the active
power, control logic and protection circuitry required to implement, with
minimal external components, several switching regulator applications,
such as a secondary side bias supply or a low power dc-dc converter.
This controller family is ideally suited for 48 V telecom, 42 V automotive
and 12 V input applications. The NCP103x can be configured in any
single-ended topology such as forward or flyback. The NCP1030 is
targeted for applications requiring up to 3 W, and the NCP1031 is
targeted for applications requiring up to 6 W.
The internal error amplifier allows the NCP103x family to be easily
configured for secondary or primary side regulation operation in
isolated and non-isolated configurations. The fixed frequency oscillator
is optimized for operation up to 1 MHz and is capable of external
frequency synchronization, providing additional design flexibility. In
addition, the NCP103x incorporates individual line undervoltage and
overvoltage detectors, cycle by cycle current limit and thermal
shutdown to protect the controller under fault conditions. The preset
current limit thresholds eliminate the need for external sensing
components.
Features
On Chip High 200 V Power Switch Circuit and Startup Circuit
Internal Startup Regulator with Auxiliary Winding Override
Operation up to 1 MHz
External Frequency Synchronization Capability
Frequency Fold-down Under Fault Conditions
Trimmed
2% Internal Reference
Line Undervoltage and Overvoltage Detectors
Cycle by Cycle Current Limit Using SENSEFET
t
Active LEB Circuit
Overtemperature Protection
Internal Error Amplifier
Typical Applications
Secondary Side Bias Supply for Isolated dc-dc Converters
Stand Alone Low Power dc-dc Converter
Low Power Bias Supply
Low Power Boost Converter
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Device
Package
Shipping
ORDERING INFORMATION
NCP1030DMR2
Micro8
t
4000/Tape & Reel
NCP1031DR2
SO-8
SO-8
D SUFFIX
CASE 751
2500/Tape & Reel
MARKING
DIAGRAMS
1030/N1031 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
Micro8
t
DM SUFFIX
CASE 846A
N1031
ALYW
1030
AYW
8
1
8
1
1
GND
2
C
T
3
V
FB
4
COMP
V
CC
V
DRAIN
OV
UV
8
7
6
5
(Top View)
PIN CONNECTIONS
8
1
8
1
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NCP1030, NCP1031
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2
Figure 1. NCP1030/31 Functional Block Diagram
Thermal
Shutdown
One Shot
Pulse
I
O
-
+
Reset
Dominant
Latch
S
R
-
+
-
+
-
+
-
+
7.5 V/10 V
10 V
6.5 V
2.5 V
-
+
LEB
Reset
Dominant
Latch
S
Q
R
50 mV
-
+
-
+
-
+
-
+
2.5 V
-
+
Internal Bias
16 V
10 V
10 V
10 V
10 V
GND
VFB
COMP
UV
OV
Disable
3.0 V/3.5 V
+
-
PWM Latch
PWM Comparator
Error Amplifier
Current Limit
Comparator
V
DRAIN
R
SENSE
10 V
V
CC
C
T
I
1
I
2
= 3I
1
Q
C
T
Ramp
-
+
-
+
2 k
W
4.5 V
I
START
FUNCTIONAL PIN DESCRIPTION
Pin
Name
Function
Description
1
GND
Ground
Ground reference pin for the circuit.
2
C
T
Oscillator Frequency
Selection
An external capacitor connected to this pin sets the oscillator frequency up to 1 MHz.
The oscillator can be synchronized to a higher frequency by charging or discharging
C
T
to trip the internal 3.0 V/3.5 V comparator. If a fault condition exists, the power
switch is disabled and the frequency is reduced by a factor of 7.
3
V
FB
Feedback Input
The regulated voltage is scaled down to 2.5 V by means of a resistor divider.
Regulation is achieved by comparing the scaled voltage to an internal 2.5 V reference.
4
COMP
Error Amplifier Compensation
Requires external compensation network between COMP and V
FB
pins. This pin is
effectively grounded if faults are present.
5
OV
Line Overvoltage Shutdown
Line voltage (V
in
) is scaled down using an external resistor divider such that the OV
voltage reaches 2.5 V when line voltage reaches its maximum operating voltage.
6
UV
Line Undervoltage Shutdown
Line voltage is scaled down using an external resistor divider such that the UV
voltage reaches 2.5 V when line voltage reaches its minimum operating voltage.
7
V
CC
Supply Voltage
This pin is connected to an external capacitor for energy storage. During Turn-On, the
startup circuit sources current to charge the capacitor connected to this pin. When the
supply voltage reaches V
CC(on)
, the startup circuit turns OFF and the power switch is
enabled if no faults are present. An external winding is used to supply power after
initial startup to reduce power dissipation. V
CC
should not exceed 16 V.
8
V
DRAIN
Power Switch and
Startup Circuits
This pin directly connects the Power Switch and Startup Circuits to one of the
transformer windings. The internal High Voltage Power Switch Circuit is connected
between this pin and ground. V
DRAIN
should not exceed 200 V.
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3
Figure 2. Pulse Width Modulation Timing Diagram
C
T
Ramp
C
T
Charge
Signal
PWM
Comparator
Output
PWM Latch
Output
Power Switch
Circuit Gate Drive
Leading Edge
Blanking Output
COMP Voltage
Current Limit
Propagation Delay
Current Limit
Threshold
Normal PWM Operating Range
Output Overload
Figure 3. Auxiliary Winding Operation with Output Overload Timing Diagram
V
CC(on)
V
CC(off)
V
CC(reset)
0 V
0 mA
I
START
0 V
0 V
V
DRAIN
V
FB
Normal Operation
Power-up &
standby Operation
Output Overload
2.5 V
V
UV
0 V
3.0 V
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4
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Switch and Startup Circuits Voltage
V
DRAIN
-0.3 to 200
V
Power Switch and Startup Circuits Input Current
- NCP1030
- NCP1031
I
DRAIN
1.0
2.0
A
V
CC
Voltage Range
V
CC
-0.3 to 16
V
All Other Inputs/Outputs Voltage Range
V
IO
-0.3 to 10
V
V
CC
and All Other Inputs/Outputs Current
I
IO
100
mA
Operating Junction Temperature
T
J
-40 to 125
C
Storage Temperature
T
stg
-55 to 150
C
Power Dissipation (T
J
= 25
C, 2.0 Oz., 1.0 Sq Inch Printed Circuit Copper Clad)
DM Suffix, Plastic Package Case 846A
D Suffix, Plastic Package Case 751
0.69
0.93
W
Thermal Resistance, Junction to Air (2.0 Oz. Printed Circuit Copper Clad)
DM Suffix, Plastic Package Case 846A
0.36 Sq. Inch
1.0 Sq. Inch
D Suffix, Plastic Package Case 751
0.36 Sq. Inch
1.0 Sq. Inch
R
q
JA
181
162
135
117
C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
A. This device contains ESD protection circuitry and exceeds the following tests:
Pins 1-7: Human Body Model 2000V per MIL-STD-883, Method 3015.
Pins 1-7:
Machine Model Method 200 V.
Pin 8 is connected to the High Voltage Startup and Power Switch Circuits and rated only to the maximum voltage rating of the part, or 200 V.
B. This device contains Latchup protection and exceeds
$
100 mA per JEDEC Standard JESD78.
NCP1030, NCP1031
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5
DC ELECTRICAL CHARACTERISTICS
(V
DRAIN
= 48 V, V
CC
= 12 V, C
T
= 560 pF, V
UV
= 3 V, V
OV
= 2 V, V
FB
= 2.3 V,
V
COMP
= 2.5 V, T
J
= -40
C to 125
C, typical values shown are for T
J
= 25
C unless otherwise noted.) (Note 1)
Characteristics
Symbol
Min
Typ
Max
Unit
STARTUP CONTROL
Startup Circuit Output Current (V
FB
= V
COMP
)
NCP1030
T
J
= 25
C
V
CC
= 0 V
V
CC
= V
CC(on)
- 0.2 V
T
J
= -40
C to 125
C
V
CC
= 0 V
V
CC
= V
CC(on)
- 0.2 V
NCP1031
T
J
= 25
C
V
CC
= 0 V
V
CC
= V
CC(on)
- 0.2 V
T
J
= -40
C to 125
C
V
CC
= 0 V
V
CC
= V
CC(on)
- 0.2 V
I
START
10
6.0
8.0
2.0
13
8.0
11
4.0
12.5
8.6
-
-
16
12
-
-
15
12
16
13
19
16
21
18
mA
V
CC
Supply Monitor (V
FB
= 2.7 V)
Startup Threshold Voltage (V
CC
Increasing)
Minimum Operating V
CC
After Turn-on (V
CC
Increasing)
Hysteresis Voltage
V
CC(on)
V
CC(off)
V
CC(hys)
9.6
7.0
-
10.2
7.6
2.6
10.6
8.0
-
V
Undervoltage Lockout Threshold Voltage, V
CC
Decreasing (V
FB
= V
COMP
)
V
CC(reset)
6.0
6.6
7.0
V
Minimum Startup Voltage (Pin 8)
I
START
= 0.5 mA, V
CC
=V
CC(on)
- 0.2 V
V
START(min)
-
16.8
18.5
V
ERROR AMPLIFIER
Reference Voltage (V
COMP
= V
FB
, Follower Mode)
T
J
= 25
C
T
J
= -40
C to 125
C
V
REF
2.45
2.40
2.5
2.5
2.55
2.60
V
Line Regulation (V
CC
= 8 V to 16 V, T
J
= 25
C)
REG
LINE
-
1.0
5.0
mV
Input Bias Current (V
FB
= 2.3 V)
I
VFB
-
0.1
1.0
m
A
COMP Source Current
I
SRC
80
110
140
m
A
COMP Sink Current (V
FB
= 2.7 V)
I
SNK
200
550
900
m
A
COMP Maximum Voltage (I
SRC
= 0
m
A)
V
C(max)
4.5
-
-
V
COMP Minimum Voltage (I
SNK
= 0
m
A, V
FB
= 2.7 V)
V
C(min)
-
-
1.0
V
Open Loop Voltage Gain
A
VOL
-
80
-
dB
Gain Bandwidth Product
GBW
-
1.0
-
MHz
LINE UNDER/OVERVOLTAGE DETECTOR
Undervoltage Lockout (V
FB
= V
COMP
)
Voltage Threshold (V
in
Increasing)
Voltage Hysteresis
Input Bias Current
V
UV
V
UV(hys)
I
UV
2.400
0.075
-
2.550
0.175
0
2.700
0.275
1.0
V
V
m
A
Overvoltage Lockout (V
FB
= V
COMP
)
Voltage Threshold (V
in
Increasing)
Voltage Hysteresis
Input Bias Current
V
OV
V
OV(hys)
I
OV
2.400
0.075
-
2.550
0.175
0
2.700
0.275
1.0
V
V
m
A
1. Production testing for NCP1030DMR2 is performed at 25
C only; limits at -40
C and 125
C are guaranteed by design.
NCP1030, NCP1031
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6
DC ELECTRICAL CHARACTERISTICS
(V
DRAIN
= 48 V, V
CC
= 12 V, C
T
= 560 pF, V
UV
= 3 V, V
OV
= 2 V, V
FB
= 2.3 V,
V
COMP
= 2.5 V, T
J
= -40
C to 125
C, typical values shown are for T
J
= 25
C unless otherwise noted.) (Note 2)
Characteristics
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Frequency (C
T
= 560 pF, Note 3)
T
J
= 25
C
T
J
= -40
C to 125
C
f
OSC1
275
260
300
-
325
325
kHz
Frequency (C
T
= 100 pF)
f
OSC2
-
800
-
kHz
Charge Current (V
CT
= 3.25 V)
I
CT(C)
-
215
-
m
A
Discharge Current (V
CT
= 3.25 V)
I
CT(D)
-
645
-
m
A
Oscillator Ramp
Peak
Valley
Vrpk
V
rvly
-
-
3.5
3.0
-
-
V
PWM COMPARATOR
Maximum Duty Cycle
DC
MAX
70
75
80
%
POWER SWITCH CIRCUIT
Power Switch Circuit On-State Resistance (I
D
= 100 mA)
NCP1030
T
J
= 25
C
T
J
= 125
C
NCP1031
T
J
= 25
C
T
J
= 125
C
R
DS(on)
-
-
-
-
4.1
6.0
2.1
3.5
7.0
12
3.0
6.0
W
Power Switch Circuit and Startup Circuit Breakdown Voltage
(I
D
= 100
m
A, T
J
= 25
C)
V
(BR)DS
200
-
-
V
Power Switch Circuit and Startup Circuit Off-State Leakage Current
(V
DRAIN
= 200 V, V
UV
= 2.0 V)
T
J
= 25
C
T
J
= -40 to 125
C
I
DS(off)
-
-
13
-
25
50
m
A
Switching Characteristics (V
DS
= 48 V, R
L
= 100
W
)
Rise Time
Fall Time
t
r
t
f
-
-
22
24
-
-
ns
CURRENT LIMIT AND OVER TEMPERATURE PROTECTION
Current Limit Threshold (T
J
= 25
C)
NCP1030 (di/dt = 0.5 A/
m
s)
NCP1031 (di/dt = 1.0 A/
m
s)
I
LIM
350
700
515
1050
680
1360
mA
Propagation Delay, Current Limit Threshold to Power Switch Circuit Output
(Leading Edge Blanking plus Current Limit Delay)
t
PLH
-
100
-
ns
Thermal Protection (Note 4)
Shutdown Threshold (T
J
Increasing)
Hysteresis
T
SHDN
T
HYS
125
-
150
45
-
-
C
TOTAL DEVICE
Supply Current After UV Turn-On
Power Switch Enabled
Power Switch Disabled
Non-Fault condition (V
FB
= 2.7 V)
Fault Condition (V
FB
= 2.7 V, V
UV
= 2.0 V)
I
CC1
I
CC2
I
CC3
2.0
-
-
3.0
1.5
0.65
4.0
2.0
1.2
mA
2. Production testing for NCP1030DMR2 is performed at 25
C only; limits at -40
C and 125
C are guaranteed by design.
3. Oscillator frequency can be externally synchronized to the maximum frequency of the device.
4. Guaranteed by design only.
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7
TYPICAL CHARACTERISTICS
V
CC
, SUPPLY VOLTAGE (V)
13.0
12.5
12.0
11.5
8.0
8.5
9.0
9.5
11.0
10.5
0
10.0
2
4
6
8
10
I
ST
AR
T
, ST
AR
TUP CURRENT (mA)
NCP1030
V
DRAIN
= 48 V
T
J
= 25
C
Figure 4. NCP1030 Startup Current vs. Supply
Voltage
20
18
16
14
0
2
4
6
12
10
8
I
ST
AR
T
, ST
AR
TUP CURRENT (mA)
NCP1030
V
DRAIN
= 48 V
-50
-25
0
25
50
150
T
J
, JUNCTION TEMPERATURE (
C)
Figure 5. NCP1031 Startup Current vs. Supply
Voltage
75
100
125
V
CC
= 0 V
V
CC
= V
CC(on)
- 0.2 V
V
DRAIN
, DRAIN VOLTAGE (V)
12
10
8
0
2
6
0
4
25
50
75
100
200
I
ST
AR
T
, ST
AR
TUP CURRENT (mA)
Figure 6. NCP1030 Startup Current vs.
Junction Temperature
125
150
175
T
J
= 25
C
V
CC
= V
CC(on)
- 0.2 V
Figure 7. NCP1031 Startup Current vs.
Junction Temperature
Figure 8. NCP1030 Startup Current vs. Drain
Voltage
Figure 9. NCP1031 Startup Current vs. Drain
Voltage
T
J
= -40
C
T
J
= 125
C
V
CC
, SUPPLY VOLTAGE (V)
20
19
18
17
10
11
12
13
16
15
0
14
2
4
6
8
10
I
ST
AR
T
, ST
AR
TUP CURRENT (mA)
NCP1031
V
DRAIN
= 48 V
T
J
= 25
C
20
18
16
14
0
2
4
6
12
10
8
I
ST
AR
T
, ST
AR
TUP CURRENT (mA)
NCP1031
V
DRAIN
= 48 V
-50
-25
0
25
50
150
T
J
, JUNCTION TEMPERATURE (
C)
75
100
125
V
CC
= 0 V
V
CC
= V
CC(on)
- 0.2 V
V
DRAIN
, DRAIN VOLTAGE (V)
12
10
8
0
2
6
0
4
25
50
75
100
200
I
ST
AR
T
, ST
AR
TUP CURRENT (mA)
125
150
175
T
J
= 25
C
T
J
= -40
C
T
J
= 125
C
NCP1030
NCP1031
20
14
18
16
V
CC
= V
CC(on)
- 0.2 V
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8
TYPICAL CHARACTERISTICS
Figure 10. Supply Voltage Thresholds vs.
Junction Temperature
Figure 11. Undervoltage Lockout Threshold
vs. Junction Temperature
Figure 12. Minimum Startup Voltage vs.
Junction Temperature
11.0
10.5
10.0
9.5
6.0
6.5
7.0
7.5
9.0
8.5
8.0
V
CC
, SUPPL
Y VOL
T
AGE (V)
-50
-25
0
50
150
T
J
, JUNCTION TEMPERATURE (
C)
Figure 13. Reference Voltage vs. Junction
Temperature
75
100
125
25
Startup Threshold
Minimum Operating Threshold
T
J
, JUNCTION TEMPERATURE (
C)
Figure 14. COMP Source Current vs. Junction
Temperature
Figure 15. COMP Sink Current vs. Junction
Temperature
-50
-25
0
25
50
150
75
100
125
6.80
6.75
6.70
6.65
6.30
6.35
6.40
6.45
6.60
6.55
6.50
V
CC(res
e
t)
, UNDER
VOL
T
AGE LOCKOUT
THRESHOLD (V)
2.70
2.65
2.60
2.55
2.20
2.25
2.30
2.35
2.50
2.45
2.40
V
REF
, REFERENCE VOL
T
AGE (V)
-25
T
J
, JUNCTION TEMPERATURE (
C)
-50
0
25
50
75
100
125
150
V
CC
= 12 V
20.0
19.5
19.0
18.5
15.0
15.5
16.0
16.5
18.0
17.5
17.0
V
ST
AR
T(
min)
, MINIMUM ST
AR
TUP VOL
T
AGE (V)
-25
T
J
, JUNCTION TEMPERATURE (
C)
-50
0
25
50
75
100
125
150
V
CC
= V
CC(on)
- 0.2 V
I
START
= 0.5 mA
V
CC
= 12 V
V
COMP
= 2.5 V
V
FB
= 2.3 V
145
140
135
130
95
100
105
110
125
120
115
I
SRC
, COMP SOURCE CURRENT (
m
A)
-25
T
J
, JUNCTION TEMPERATURE (
C)
-50
0
25
50
75
100
125 150
840
790
740
690
390
440
490
640
590
540
I
SNK
, COMP SINK CURRENT (
m
A)
340
-25
T
J
, JUNCTION TEMPERATURE (
C)
-50
0
25
50
75
100
125 150
V
CC
= 12 V
V
COMP
= 2.5 V
V
FB
= 2.7 V
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9
TYPICAL CHARACTERISTICS
Figure 16. Line Under/Overvoltage Thresholds
vs. Junction Temperature
T
J
, JUNCTION TEMPERATURE (
C)
-50
-25
0
50
150
75
100
125
25
2.600
2.575
2.550
2.525
2.350
2.375
2.400
2.425
2.500
2.475
2.450
V
UV/OV
, LINE UNDER/OVER
VOL
T
AGE THRESHOLDS (V)
200
190
180
170
120
130
160
150
140
V
UV/OV(hys)
, UNDER/OVER
VOL
T
AGE
HYSTERESIS (mV)
-25
T
J
, JUNCTION TEMPERATURE (
C)
-50
0
25
50
75
100
125
150
210
220
Figure 17. Line Under/Overvoltage Hysteresis
vs. Junction Temperature
Figure 18. Oscillator Frequency vs. Timing
Capacitor
Figure 19. Oscillator Frequency vs. Junction
Temperature
1000
900
800
700
0
100
200
300
600
500
400
f
OS
C
, OSCILLA
T
OR FREQUENCY (kHz)
C
T
, TIMING CAPACITOR (pF)
Figure 20. Maximum Duty Cycle vs. Junction
Temperature
0
200
400
600
800
1000
V
CC
= 12 V
T
J
= 25
C
T
J
, JUNCTION TEMPERATURE (
C)
Figure 21. Power Switch Circuit On Resistance
vs. Junction Temperature
V
CC
= 12 V
1100
1000
900
800
100
200
400
700
600
500
f
OS
C
, OSCILLA
T
OR FREQUENCY (kHz)
-50
-25
0
25
150
50
75
100
125
300
C
T
= 47 pF
C
T
= 220 pF
C
T
= 1000 pF
77.0
76.5
76.0
75.5
72.0
72.5
73.0
73.5
75.0
74.5
74.0
DC
MAX
, MAXIMUM DUTY CYCLE (%)
-50
-25
0
25
50
75
T
J
, JUNCTION TEMPERATURE (
C)
100
125
150
f
OSC
= 1000 kHz
f
OSC
= 200 kHz
V
CC
= 12 V
8
7
6
0
1
2
3
5
4
R
DS(on)
, POWER SWITCH CIRCUIT
ON RESIST
ANCE (
W
)
-50
-25
0
25
50
75
T
J
, JUNCTION TEMPERATURE (
C)
100
125
150
V
CC
= 12 V
I
D
= 100 mA
NCP1030
NCP1031
NCP1030, NCP1031
http://onsemi.com
10
TYPICAL CHARACTERISTICS
Figure 22. Power Switch Circuit Output
Capacitance vs. Drain Voltage
C
OUT
, OUTPUT CAP
ACIT
ANCE (pF)
Figure 23. Power Switch Circuit and Startup
Circuit Leakage Current vs. Drain Voltage
1000
10
100
Figure 24. NCP1030 Current Limit Threshold
vs. Junction Temperature
0
40
80
120
160
200
V
DRAIN
, DRAIN VOLTAGE (V)
40
35
30
0
5
10
15
25
20
I
DS(of
f
)
, POWER SWITCH AND ST
AR
TUP
CIRCUITS LEAKAGE CURRENT (
m
A)
Figure 25. NCP1031 Current Limit Threshold
vs. Junction Temperature
0
50
100
150
V
DRAIN
, DRAIN VOLTAGE (V)
200
250
300
T
J
= -40
C
T
J
= 25
C
T
J
= 125
C
V
CC
= 12 V
NCP1030
NCP1031
600
575
550
525
350
375
500
475
400
I
LIM
, CURRENT LIMIT THRESHOLD (mA)
T
J
, JUNCTION TEMPERATURE (
C)
-50
-25
0
25
50
75
T
J
= 25
C
100
125
150
425
450
600
575
550
525
350
375
500
475
400
I
LIM
, CURRENT LIMIT THRESHOLD (mA)
CURRENT SLEW RATE (mA/
m
S)
375
400
425
450
475
500
425
450
Current Slew Rate = 500 mA/
m
s
Figure 26. NCP1030 Current Limit Threshold
vs. Current Slew Rate
Figure 27. NCP1031 Current Limit Threshold
vs. Current Slew Rate
1200
1150
1100
1050
700
750
1000
950
800
I
LIM
, CURRENT LIMIT THRESHOLD (mA)
T
J
, JUNCTION TEMPERATURE (
C)
-50
-25
0
25
50
75
T
J
= 25
C
100
125
150
850
900
1200
1150
1100
1050
700
750
1000
950
800
I
LIM
, CURRENT LIMIT THRESHOLD (mA)
CURRENT SLEW RATE (mA/
m
S)
750
800
850
900
950
1000
850
900
Current Slew Rate = 1 A/
m
s
NCP1030
NCP1030
NCP1031
NCP1031
NCP1030, NCP1031
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11
TYPICAL CHARACTERISTICS
Figure 28. Operating Supply Current vs.
Supply Voltage
Figure 29. Supply Current vs. Junction
Temperature
4.1
3.9
3.3
2.5
3.1
2.7
I
CC1
, OPERA
TING SUPPL
Y CURRENT (mA)
V
CC
, SUPPLY VOLTAGE (V)
Figure 30. Operating Supply Current vs.
Oscillator Frequency
10
11
12
13
14
15
16
2.9
V
DRAIN
= 48 V
T
J
= 25
C
C
T
= 560 pF
4.0
2.5
2.0
0
1.5
0.5
I
CC
, SUPPL
Y CURRENT (mA)
T
J
, JUNCTION TEMPERATURE (
C)
-50
-25
0
25
50
75
100
1.0
V
CC
= 12 V
C
T
= 560 pF
125
150
V
UV
= 3.0 V, V
FB
= 2.3 V
V
UV
= 3.0 V, V
FB
= 2.7 V
V
UV
= 2.0 V
3.0
3.7
3.5
3.5
10
7
6
2
5
3
I
CC
, POWER SUPPL
Y CURRENT (mA)
f
OSC
, OSCILLATOR FREQUENCY (kHz)
200
300
400
500
600
700
800
4
900
1000
T
J
= 25
C
8
9
NCP1030
NCP1031
NCP1030, NCP1031
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12
Figure 31. Secondary Side Bias Supply Configuration
GND
COMP
+
V
in
-
V
BIAS
GND
SECONDARY
SIDE CONTROL
V
CC
V
DRAIN
UV
OV
C
T
V
FB
+
V
out
-
NCP103x
Figure 32. Boost Circuit Configuration
GND
COMP
V
out
V
CC
V
DRAIN
UV
OV
C
T
V
FB
+
V
in
-
+
-
NCP103x
V
CC
V
CC
NCP1030, NCP1031
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13
OPERATING DESCRIPTION
Introduction
The NCP1030 and NCP1031 are a family of miniature
monolithic voltage-mode switching regulators designed for
isolated and non-isolated bias supply applications. The
internal startup circuit and the MOSFET are rated at 200 V,
making them ideal for 48 V telecom and 42 V automotive
applications. In addition, the NCP103x family can operate
from an existing 12 V supply. This controller family is
optimized for operation up to 1 MHz.
The NCP103x family incorporates in a single IC all the
active power, control logic and protection circuitry required
to implement, with a minimum of external components,
several switching regulator applications, such as a
secondary side bias supply or a low power dc-dc converter.
The NCP1030 is available in the space saving Micro8
t
package and is targeted for applications requiring up to 3 W.
The NCP1031 is targeted for applications up to 6 W and is
available in the SO-8 package.
The NCP103x includes an extensive set of features
including over temperature protection, cycle by cycle
current limit, individual line under and overvoltage
detection comparators with hysteresis, and regulator output
undervoltage lockout with hysteresis, providing full
protection during fault conditions. A description of each of
the functional blocks is given below, and the representative
block diagram is shown in Figure 2.
Startup Circuit and Undervoltage Lockout
The NCP103x contains an internal 200 V startup regulator
that eliminates the need for external startup components.
The startup regulator consists of a constant current source
that supplies current from the input line (V
in
) to the capacitor
on the V
CC
pin (C
CC
). Once the V
CC
voltage reaches
approximately 10 V, the startup circuit is disabled and the
Power Switch Circuit is enabled if no faults are present.
During this self-bias mode, power to the NCP103x is
supplied by the V
CC
capacitor. The startup regulator turns
ON again once V
CC
reaches 7.5 V. This "7.5-10" mode of
operation is known as Dynamic Self Supply (DSS). The
NCP1030 and NCP1031 startup currents are 12 mA and 16
mA, respectively.
If V
CC
falls below 7.5 V, the device enters a re-start mode.
While in the re-start mode, the V
CC
capacitor is allowed to
discharge to 6.5 V while the Power Switch is enabled. Once
the 6.5 V threshold is reached, the Power Switch Circuit is
disabled and the startup regulator is enabled to charge the
V
CC
capacitor. The Power Switch is enabled again once the
V
CC
voltage reaches 10 V. Therefore, the external V
CC
capacitor must be sized such that a voltage greater than 7.5
V is maintained on the V
CC
capacitor while the converter
output reaches regulation. Otherwise, the converter will
enter the re-start mode. Equation (1) provides a guideline
for the selection of the V
CC
capacitor for a forward
converter;
Forward:
(eq. 1)
CCC
+
cos
-1
1
*
VOUT
@
NP
DC
@
Vin
@
NS
L
OUT
C
OUT
@
Ibias
2.6
where, I
bias
is the bias current supplied by the V
CC
capacitor
including the IC bias current (I
CC1
) and any additional
current used to bias the feedback resistors (if used).
After initial startup, the V
CC
pin should be biased above
V
CC(off)
using an auxiliary winding. This will prevent the
startup regulator from turning ON and reduce power
dissipation. Also, the load should not be directly connected
to the V
CC
capacitor. Otherwise, the load may override the
startup circuit. Figure 33 shows the recommended
configuration for a non-isolated flyback converter.
Figure 33. Non-Isolated Bias Supply Configuration
GND
COMP
+
V
in
-
V
CC
V
DRAIN
UV
OV
C
T
V
FB
NCP103x
+
V
out
-
The maximum voltage rating of the startup circuit is
200 V. Power dissipation should be observed to avoid
exceeding the maximum power dissipation of the package.
Error Amplifier
The internal error amplifier (EA) regulates the output
voltage of the bias supply. It compares a scaled output
voltage signal to an internal 2.5 V reference (V
REF
)
connected to its non-inverting input. The scaled signal is fed
into the feedback pin (
V
FB
) which is the inverting input of the
error amplifier.
The output of the error amplifier is available for frequency
compensation and connection to the PWM comparator
through the COMP pin. To insure normal operation, the EA
compensation should be selected such that the EA frequency
response crosses 0 dB below 80 kHz.
The error amplifier input bias current is less than 1
mA
over the operating range. The output source and sink
currents are typically 110
mA and 550 mA, respectively.
Under load transient conditions, COMP may need to
move from the bottom to the top of the C
T
Ramp. A large
current is required to complete the COMP swing if small
resistors or large capacitors are used to implement the
compensation network. In which case, the COMP swing will
NCP1030, NCP1031
http://onsemi.com
14
be limited by the EA sink current, typically 110
mA.
Optimum transient response is obtained if the compensation
components allow COMP to swing across its operating
range in 1 cycle.
Line Under and Overvoltage Detector
The NCP103x incorporates individual line undervoltage
(UV) and overvoltage (OV) shutdown circuits. The UV and
OV thresholds are 2.5 V. A fault is present if the UV is below
2.5 V or if the OV voltage is above 2.5 V. The UV/OV
detectors incorporate 175 mV hysteresis to prevent noise
from triggering the shutdown circuits.
The UV/OV circuits can be biased using an external
resistor divider from the input line as shown in Figure 34.
The UV/OV pins should be bypassed using a capacitor to
prevent triggering the UV or OV circuits during normal
switching operation.
Figure 34. UV/OV Resistor Divider
from the Input Line
R
1
R
2
R
3
V
in
V
UV
-
+
V
OV
-
+
The resistor divider must be sized to enable the controller
once V
in
is within the required operating range. While a UV
or OV fault is present, switching is not allowed and the
COMP pin is effectively grounded.
Either of these comparators can be used for a different
function if UV or OV functions are not needed. For example,
the UV/OV detectors can be used to implement an enable or
disable function. If positive logic is used, the enable signal
is applied to the UV pin while the OV pin is grounded. If
negative logic is used, the disable signal is applied to the OV
pin while biasing the UV pin from V
CC
using a resistor
divider.
Oscillator
The oscillator is optimized for operation up to 1 MHz and
its frequency is set by the external timing capacitor (C
T
)
connected to the C
T
pin. The oscillator has two modes of
operation, free running and synchronized (sync). While in
free running mode, an internal current source sequentially
charges and discharges C
T
generating a voltage ramp
between 3.0 V and 3.5 V. Under normal operating
conditions, the charge (I
CT(C)
) and discharge (I
CT(D)
)
currents are typically 215
mA and 645 mA, respectively. The
charge:discharge current ratio of 1:3 discharges
C
T
in 25 %
of the total period. The Power Switch is disabled while C
T
is discharging, guaranteeing a maximum duty cycle of 75 %
as shown in Figure 35.
25 %
Max
Duty Cycle
COMP
75%
Figure 35. Maximum Duty Cycle vs COMP
C
T
Ramp
Power Switch
Enabled
C
T
Charge
Signal
Figure 18 shows the relationship between the operating
frequency and C
T
. If an UV fault is present, both I
CT(C)
and
I
CT(D)
are reduced by a factor of 7, thus reducing the
operating frequency by the same factor.
The oscillator can be synchronized to a higher frequency
by capacitively coupling a synchronization pulse into the C
T
pin. In sync mode, the voltage on the
C
T
pin needs to be
driven above 3.5 V to trigger the internal comparator and
complete the C
T
charging period. However, pulsing the C
T
pin before it reaches 3.5 V will reduce the p-p amplitude of
the C
T
Ramp as shown in Figure 36.
Figure 36. External Frequency Synchronization
Waveforms
3.0 V
3.5 V
Sync Pulse
3.0 V/3.5 V
Comparator
Reset
Free Running
Mode
Sync Mode
T1 (f1)
T2 (f2)
T2 (f2)
C
T
Ramp
C
T
Voltage
Range in Sync
The oscillator frequency should be set no more that 25%
below the target sync frequency to maintain an adequate
voltage range and provide good noise immunity. A possible
circuit to synchronize the oscillator is shown in Figure 37.
2
5 V
C1
R1
R2
Figure 37. External Frequency Synchronization
Circuit.
C
T
C
T
NCP1030, NCP1031
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15
PWM Comparator and Latch
The Pulse Width Modulator (PWM) Comparator
compares the error amplifier output (COMP) to the C
T
Ramp and generates a proportional duty cycle. The Power
Switch is enabled while the C
T
Ramp is below COMP as
shown in Figure 35. Once the C
T
Ramp reaches COMP, the
Power Switch is disabled. If COMP is at the bottom of the
C
T
Ramp, the converter operates at minimum duty cycle.
While COMP increases, the duty cycle increases, until
COMP reaches the peak of the C
T
Ramp, at which point the
controller operates at maximum duty cycle.
The C
T
Charge Signal is filtered through a One Shot Pulse
Generator to set the PWM Latch and enable switching at the
beginning of each period. Switching is allowed while the C
T
Ramp is below COMP and a current limit fault is not present.
The PWM Latch and Comparator propagation delay is
typically 150 ns. If the system is designed to operate with a
minimum ON time less than 150 ns, the converter will skip
pulses. Skipping pulses is usually not a problem, unless
operating at a frequency close to the audible range. Skipping
pulses is more likely when operating at high frequencies
during high line and minimum load condition.
A series resistor is included for ESD protection between the
EA output and the COMP pin. Under normal operation, a 220
mV offset is observed between the C
T
Ramp and the COMP
crossing points. This is not a problem as the series resistor
does not interact with the error amplifier transfer function.
Current Limit Comparator and Power Switch Circuit
The NCP103x monolithically integrates a 200 V Power
Switch Circuit with control logic circuitry. The Power
Switch Circuit is designed to directly drive the converter
transformer. The characteristics of the Power Switch Circuit
are well known. Therefore, the gate drive is tailored to
control switching transitions and help limit electromagnetic
interference (EMI). The Power Switch Circuit is capable of
switching 200 V.
The Power Switch Circuit incorporates SENSEFET
TM
technology to monitor the drain current. A sense voltage is
generated by driving a sense element, R
SENSE
, with a current
proportional to the drain current. The sense voltage is
compared to an internal reference voltage on the
non-inverting
input of the Current Limit Comparator. If the
sense voltage exceeds the reference level, the comparator
resets the PWM Latch and switching is terminated. The
NCP1030 and NCP1031 drain current limit thresholds are
0.5 A and 1.0 A, respectively.
Each time the Power Switch Circuit turns ON, a narrow
voltage spike appears across R
SENSE
. The spike is due to the
Power Switch Circuit gate to source capacitance,
transformer interwinding capacitance, and output rectifier
recovery time. This spike can cause a premature reset of the
PWM Latch. A proprietary active Leading Edge Blanking
(LEB) Circuit masks the current signal to prevent the
voltage spike from resetting the PWM Latch. The active
LEB masks the current signal until the Power Switch turn
ON transition is complete. The adaptive LEB period
provides better current limit control compared to a fixed
blanking period.
The current limit propagation delay time is typically
100 ns. This time is measured from when an overcurrent
fault appears at the Power Switch Circuit drain, to the start
of the turn-off transition. Propagation delay must be
factored in the transformer design to avoid transformer
saturation.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event the maximum
junction temperature is exceeded. When activated, typically
at 150
_C, the Power Switch Circuit is disabled. Once the
junction temperature falls below 105
_C, the NCP103x is
allowed to resume normal operation. This feature is
provided to prevent catastrophic failures from accidental
device overheating. It is not intended to be used as a
substitute for proper heatsinking.
Application Considerations
A 2 W bias supply for a 48 V telecom system was designed
using the NCP1030. The bias supply generates an isolated
12 V output. The circuit schematic is shown in Figure 38.
Application Note AND8119/D describes the design of the
bias supply.
Figure 38. 2 W Isolated Bias Supply Schematic
GND
COMP
+
35-76V
-
VCC
VDRAIN
UV
OV
CT
VFB
+
-
22
MBRA160T3
MBRA160T3
2.2
1M
10
4k99
1k30
10k
0.033
680p
680p
0.01
0.01
2.2
2.2
1:2.78
45k3
34k
12V
NCP1030
0.022
100
p
MURA1
10T3
499
NCP1030, NCP1031
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16
PACKAGE DIMENSIONS
Micro8
DM SUFFIX
CASE 846A-02
ISSUE F
S
B
M
0.08 (0.003)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
2.90
3.10
0.114
0.122
B
2.90
3.10
0.114
0.122
C
---
1.10
---
0.043
D
0.25
0.40
0.010
0.016
G
0.65 BSC
0.026 BSC
H
0.05
0.15
0.002
0.006
J
0.13
0.23
0.005
0.009
K
4.75
5.05
0.187
0.199
L
0.40
0.70
0.016
0.028
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS
OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD
846A-02.
-B-
-A-
D
K
G
PIN 1 ID
8 PL
0.038 (0.0015)
-T-
SEATING
PLANE
C
H
J
L
-
8X
8X
6X
mm
inches
SCALE 8:1
1.04
0.041
0.38
0.015
5.28
0.208
4.24
0.167
3.20
0.126
0.65
0.0256
SOLDERING FOOTPRINT
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17
PACKAGE DIMENSIONS
SO-8
D SUFFIX
CASE 751-07
ISSUE AC
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE.
NEW STANDARD IS 751-07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
SOLDERING FOOTPRINT
NCP1030, NCP1031
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18
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 81-3-5773-3850
NCP1030/D
Micro8 is a trademark of International Rectifier. SENSEFET is a trademark of Semiconductor Components Industries, LLC.
The products described herein (NCP1030 and NCP1031) may be covered by one or more of the following U.S. patents: 5,418,410; 5,477,175.
There may be other patents pending.
LITERATURE FULFILLMENT:
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