Semiconductor Components Industries, LLC, 2002
April, 2002 Rev. 2
1
Publication Order Number:
NCP1205/D
NCP1205
Single Ended PWM
Controller Featuring QR
Operation and Soft
Frequency Foldback
The NCP1205 combines a true Current Mode Control modulator
and a demagnetization detector to ensure full Discontinuous
Conduction Mode in any load/line conditions and minimum drain
voltage switching (QuasiResonant operation, also called critical
conduction operation). With its inherent Variable Frequency Mode
(VFM), the controller decreases its operating frequency at constant
peak current whenever the output power demand diminishes.
Associated with automatic multiple valley switching, this unique
architecture guarantees minimum switching losses and the lowest
power drawn from the mains when operating at noload conditions.
Thus, the NCP1205 is optimal for applications targeting the newest
International Energy Agency (IEA) recommendations for standby
power.
The internal HighVoltage current source provides a reliable
charging path for the V
CC
capacitor and ensures a clean and short
startup sequence without deteriorating the efficiency once off.
The continuous feedback signal monitoring implemented with an
OverCurrent fault Protection circuitry (OCP) makes the final design
rugged and reliable. An internal Over Voltage Protection (OVP) circuit
continuously monitors the V
CC
pin and stops the IC whenever its level
exceeds 36 V. The DIP14 offers an adjustable version of the OVP
threshold via an external resistive network.
Features
Natural Drain Valley Switching for Lower EMI and QuasiResonant
Operation (QR)
Smooth Frequency Foldback for Low Standby and Minimum Ripple
at LightLoad
Adjustable Maximum Switching Frequency
Internal 200 ns Leading Edge Blanking on Current Sense
250 mA Sink and Source Driver
Wide Operating Voltages: 8.0 to 36 V
Wide UVLO Levels: 7.2 to 15 V Typical
AutoRecovery Internal ShortCircuit Protection (OCP)
Integrated 3.0 mA Typ. StartUp Source
Current Mode Control
Adjustable OverVoltage Level
Available in DIP8 and DIP14 Package
Applications
High Power AC/DC Adapters for Notebooks, etc.
Offline Battery Chargers
Power Supplies for DVD, CD Players, TVs, SetTop Boxes, etc.
Auxiliary Power Supplies (USB, Appliances, etc.)
PDIP14
P SUFFIX
CASE 646
14
MARKING
DIAGRAMS
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
1
1
14
NCP1205P2
AWLYYWW
PDIP8
N SUFFIX
CASE 626
1
8
NCP1205P
AWL
YYWW
1
1
8
Device
Package
Shipping
ORDERING INFORMATION
NCP1205P
PDIP8
50 Units/Rail
NCP1205P2
PDIP14
25 Units/Rail
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2
PIN CONNECTIONS
1
HV
14
V
CC
2
3
FB
4
Ct
13
Drive
12
Isense
11
GND
5
6
7
10
9
8
NC
OVP
NC
NC
NC
NC
PDIP14
1
HV
8 V
CC
2
Demag
3
FB
4
Ct
7 Drive
6 Isense
5 GND
PDIP8
Demag
PIN FUNCTION DESCRIPTION
Pin No.
DIP8
DIP14
Pin Name
Function
Description
1
1
HV
Startup rail
Connected to the rectified HV rail, this pin provides a charging path to
V
CC
bulk capacitor.
2
3
Demag
Zero primarycurrent
detection
This pin ensures the restart of the main switcher when operating in
freerun.
3
4
FB
Feedback signal to
control the PWM
This level modulates the peak current level in freerunning operation
and modulates the frequency in VFM operation.
4
5
Ct
Timing capacitor
By adding a capacitor from Ct to the ground, the user selects the
minimum/maximum operating frequency.
5
10
Gnd
The IC's ground
NA
6
OVP
Overvoltage input
By applying a 2.8 V typical level on this pin, the IC is permanently
latchedoff until V
CC
falls below UVLO
L
.
6
11
Isense
The primarycurrent
sensing pin
This pin senses the primary current via an external shunt resistor.
7
12
Drv
This pin drives the
external switcher
The IC is able to deliver or absorb 250 mA peak currents while
delivering a clamped driving signal.
8
13
V
CC
Powers the IC
A positive voltage up to 40 V
typical can be applied upon this pin
before the IC stops.
1. DIP14 has different pinouts. Please see Pin Connections.
2. Pin 2, 7, 8, 9 and 14 are nonconnected on DIP14.
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Figure 1. Typical Application Example for DIP8 Version
NCP1205P
1
2
3
4
8
7
6
5
+
+
+
+
4x1N4007
C1
10
F
R8
22 k
R6
4.7 k
R1
560
Universal Input
R2
150
C14
22
F
D2
1N4148
D6
1N5819
L2
10
H
C11
100
F
10 V
IC4
SFH61562
1.5 nF Y1
C12
1 nF
C10
470
F
10 V
5 V
M2
MTD1N60E
R4
10
D7
5.1 V
C13
R5
15
R3
3.3
* R10
15 k
* Please refer to the application information section regarding this element.
Figure 2. Typical Application Example for DIP14 Version
NCP1205P2
+
+
+
4x1N4007
R8
22 k
R6
2.7 k
R1
560
Universal Input
R2
15
C14
33
F/35 V
D2
1N4148
D6
1N5819
L2
10
H
C11
47
F
10 V
IC4
SFH61562
C12
1 nF
C10
470
F
10 V
5 V
M2
MTD1N60E
R4
6.8
D7
4.3 V
1
14
2
3
4
13
12
11
5
6
7
10
9
8
ROVPL
ROVPU
R5
15
R3
3.3
+ C1
10
F
* Please refer to the application information section regarding this element.
* R10
15 k
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Figure 3. Internal Circuit Architecture for DIP8 Version
2
3
+
+
+
Internal Regulator
Internal Clamp
DEMAG ?
Last Pulse of Demag
after 4
s
FlipFlop
Over Voltage
Protection (V
CC
> 40 V)
Lasts more than 128 ms?
> Protection Circuitry
V
CO
Feedback
T
off
= f (V
err
)
Max T
off
= f (Ct)
Over Current
Protection (OCP)
V() < 1.5 V
V
err
Max = 3 V
V
err
Min = 10 mV
Internal V
CC
Ri
Rf
1
4
5
7
6
200 ns L.E.B
2.5 V
1/3
+
8
Clock
R
Q
D
Driver
Current Comparator
250 mV 1 V
Max Setpoint
HV
Demag
FB
Ct
V
CC
DRV
I
sense
Gnd
Startup
UVLO
H
= 15 V
UVLO
L
= 7.2 V
250 mV Clamp
1 V
V
err
+
+
OVP
2.8 V
18 k
35 V Zener
V
CC
Pin 8
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Figure 4. Internal Circuit Architecture for DIP14 Version
3
4
+
+
+
Internal Regulator
Internal Clamp
DEMAG ?
Last Pulse of Demag
after 4
s
FlipFlop
Over Voltage
Protection (V
CC
> 40 V)
Lasts more than 128 ms?
> Protection Circuitry
V
CO
Feedback
T
off
= f (V
err
)
Max T
off
= f (Ct)
Over Current
Protection (OCP)
V() < 1.5 V
V
err
Max = 3 V
V
err
Min = 10 mV
Internal V
CC
Ri
Rf
1
5
200 ns L.E.B
2.5 V
1/3
+
14
Clock
R
Q
D
Driver
Current Comparator
250 mV 1 V
Max Setpoint
HV
Demag
FB
Ct
V
CC
DRV
I
sense
Gnd
Startup
UVLO
H
= 15 V
UVLO
L
= 7.2 V
250 mV Clamp
1 V
V
err
2
7
6
13
12
11
10
8
9
2.0 k
OVP
+
+
OVP
2.8 V
18 k
35 V Zener
V
CC
Pin 13
V
CC
Pin 13
NC
NC
OVP
NC
NC
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6
MAXIMUM RATINGS
Pin No.
Value
Rating
DIP8
DIP14
Symbol
Min
Max
Unit
Power Supply Voltage
8
13
V
in
45
V
Thermal Resistance JunctiontoAir
DIP8
DIP14
R
q
JA
100
100
C/W
Operating Junction Temperature Range
Maximum Junction Temperature
T
J
T
Jmax
25 to +125
150
C
C
Storage Temperature Range
T
stg
60 to +150
C
ESD Capability, HBM Model
All Pins
All Pins
2.0
kV
ESD Capability, Machine Model
All Pins
All Pins
200
V
Demagnetization Pin Current
3
3
"
5.0
mA
ELECTRICAL CHARACTERISTICS
(For typical values T
A
= 25
C, for min/max values T
J
= 25
C to +125
C, Max T
J
= 150
C,
V
CC
= 12 V unless otherwise noted.)
Pin No.
Characteristics
DIP8
DIP14
Symbol
Min
Typ
Max
Unit
Demagnetization Block
Input Threshold Voltage (V
pin2
increasing)
2
3
Vth
50
65
85
mV
Hysteresis (V
pin2
decreasing)
2
3
V
H
30
mV
Input Clamp Voltage
High State (I
pin2
= 3.0 mA)
Low State (I
pin2
= 3.0 mA)
2
3
VC
H
VC
L
8.0
0.9
10
0.7
12
0.5
V
Demag Propagation Delay
100
300
350
ns
No Demag Signal Activation
4.0
8.0
s
Internal Input Capacitance at 1.0 V
2
3
C
pin2
10
pF
Demag Propagation Delay with 22 k
External Resistor
2
3
100
370
480
ns
Feedback Path
Input Impedance at V
FB
= 3.0 V
3
4
Zin
50
k
Internal Error Amplifier Closed Loop Gain
3
4
AV
CL
3.0
Internal BuiltIn Offset Voltage for Error Detection
V
ref
2.2
2.5
2.8
V
Error Amplifier Level of VCO Take Over
1.0
V
Internal Divider from Internal Error Amp, Pin to Current
Setpoint
3.0
Fault Detection Circuitry
Internal Over Current Level
WL
L
1.5
V
Fault Time Duration to Latch Activation @ Ct = 1.0
F
128
ms
Over Current LatchOff Phase @ Ct = 1.0
F
1.0
s
Hysteresis when V
FB
goes back into Regulation
100
mV
V
CC
(Pin 8) Over Voltage Protection
8
13
OVP1
36
40
43
V
Over Voltage Protection Threshold for DIP14 Version
6
6
OVP2
2.5
2.8
3.1
V
Current Sense Comparator
Input Bias Current @ 1.0 V
6
11
I
IB
0.02
A
Maximum Current Setpoint
6
11
V
cl
0.9
1.0
1.1
V
Minimum Current Setpoint
6
11
V
min
225
250
285
mV
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7
ELECTRICAL CHARACTERISTICS (continued)
(For typical values T
A
= 25
C, for min/max values T
J
= 25
C to +125
C,
Max T
J
= 150
C, V
CC
= 12 V unless otherwise noted.)
Pin No.
Characteristics
DIP8
DIP14
Symbol
Min
Typ
Max
Unit
Current Sense Comparator (continued)
Propagation Delay from Current Detection to Gate OFF
State
6
11
T
del
200
250
ns
Leading Edge Blanking (LEB)
6
11
T
leb
200
ns
Frequency Modulator
Minimum Frequency Operation @ Ct = 1.0
F and
V
CC
= 35 V
4
5
F
min
0
kHz
Maximum Frequency Operation @ Ct = 1.0
F and
V
CC
= 35 V
4
5
F
max
90
110
125
kHz
Minimum Ct Charging Current (Note 3)
4
5
I
Ct
min
0
A
Maximum Ct Charging Current (Note 3)
4
5
I
Ct
max
280
350
420
A
Discharge Time @ Ct = 1.0
F
4
5
500
ns
Drive Output
Output Voltage Rise Time @ C
L
= 1.0
F (
D
V = 10 V)
7
12
t
r
30
50
ns
Output Voltage Fall Time @ C
L
= 1.0
F (
D
V = 10 V)
7
12
t
f
30
50
ns
Clamped Output Voltage @ V
CC
= 35 V (Note 4)
7
12
V
DRV
11
13
16
V
Voltage Drop on the Stage @ V
CC
= 10 V (Note 4)
12
12
V
DRV
0.5
V
Undervoltage Lockout
Startup Threshold (V
CC
Increasing)
8
13
UVLO
H
13.5
15
16.5
V
Minimum Operating Voltage (V
CC
Decreasing)
8
13
UVLO
L
6.5
7.2
8.0
V
Startup Current Source
Maximum Voltage, Pin 1 Grounded
1
1
450
V
Maximum Voltage, Pin 1 Decoupled (470
F)
1
1
500
V
Startup Current Source Flowing through Pin 1
1
1
2.3
3.0
4.8
mA
Leakage Current in Offstate @ Vpin 1 = 500 V
1
1
32
70
A
Device Current Consumption
V
CC
less than UVLO
H
8
13
1.5
1.8
mA
V
CC
= 35 V and Fsw = 2.0 kHz, C
L
= 1.0
F
8
13
1.2
3.0
mA
V
CC
= 35 V and Fsw = 125 kHz, C
L
= 1.0
F
8
13
3.0
4.0
mA
Startup Current to V
CC
Capacitor
8
13
1.4
mA
3. Typical capacitor swing is between 0.5 V and 3.5 V.
4. Guaranteed by design, T
J
= 25
C.
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8
50
0
50
100
50
0
50
100
110
100
115
95
105
90
125
1000
50
360
Ct CHARGING CURRENT (
A)
280
TEMPERATURE (
C)
Figure 5. Ct Charging Current versus
Temperature
Figure 6. Switching Frequency @ Ct = 1 nF
versus Temperature
SWITCHING FREQUENCY (kHz)
16.5
16
14.5
14
13.5
Figure 7. Startup Threshold versus
Temperature
TEMPERATURE (
C)
Figure 8. Maximum Current Set Point versus
Temperature
TEMPERATURE (
C)
MAXIMUM CURRENT SET POINT (mV)
ST
AR
TUP THRESHOLD (V)
420
950
900
1050
1100
TEMPERATURE (
C)
340
380
320
0
50
100
50
0
50
100
150
300
400
150
120
150
15
15.5
50
0
50
100
50
0
50
100
7.5
43
42
36
Figure 9. V
CC
Over Voltage Protection versus
Temperature
TEMPERATURE (
C)
Figure 10. Minimum Operating Voltage versus
Temperature
TEMPERATURE (
C)
MINIMUM OPERA
TING VOL
T
AGE (V)
V
CC
OVER VOL
T
AGE (V)
7
7.75
6.75
7.25
6.5
8
150
150
41
40
39
38
37
150
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9
APPLICATION INFORMATION
Introduction
By implementing a unique smooth frequency reduction
technique, the NCP1205 represents a major leap toward
lowpower SwitchMode Power Supply (SMPS) integrated
management. The circuit combines freerunning operation
with minimum drainsource switching (socalled valley
switching), which naturally reduces the peak current stress
as well as the ElectroMagnetic Interferences (EMI). At
nominal output power, the circuit implements a traditional
currentmode SMPS whose peak current setpoint is given
by the feedback signal. However, rather than keeping the
switching frequency constant, each cycle is initiated by the
end of the primary demagnetization. The system therefore
operates at the boundary between Discontinuous
Conduction Mode (DCM) and Continuous Conduction
Mode (CCM). Figure 11 details this terminology:
0
0
DeadTime
Time
0 Before
Turn ON
Not 0 at
Turn ON
ON
OFF
D/Fs
I
L(avg)
I
L
I
P
L < Lc
L > Lc
L = Lc
Borderline
Figure 11. Defining the Conduction Mode, Discontinuous, Continuous and Borderline
When the output power demands decreases, the natural
switching frequency raises. As a natural result, switching
losses also increase and degrade the SMPS efficiency. To
overcome this problem, the maximum switching frequency
of the NCP1205 is clamped to typically 125 kHz. When the
free running mode (also called Borderline Control Mode,
BCM) reaches this clamp value, an internal
VoltageControlled Oscillator (VCO) takes over and starts
to decrease the switching frequency: we are in Variable
Frequency Mode (VFM). Please note that during this
transition phase, the peak current is not fixed but is still
decreasing because the output power demand does. At a
given state, the peak current reaches a minimum ceil
(typically 250 mV/Rsense), and cannot go further down: the
switching frequency continues its decrease down to a
possible minimum of 0 Hz (the IC simply stops switching).
During normal freerunning operation and VFM, the
controller always ensures single or multiple drainsource
valley switching. We will see later on how this is internally
implemented.
The FLYBACK operation is mainly defined through a
simple formula:
Pout
+
1
2
Lp Ip2 Fsw
(eq. 1)
With:
Lp the primary transformer inductance (also called the
magnetizing inductance)
Ip the peak current at which the MOSFET is turned off
Fsw the nominal switching frequency
To adjust the transmitted power, the PWM controller can
play on the switching frequency or the peak current setpoint.
To refine the control, the NCP1205 offers the ability to play
on both parameters either altogether on an individual basis.
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10
In order to clarify the device behavior, we can distinguish the
following simplified operating phases:
1. The load is at its nominal value. The SMPS operates in
borderline conduction mode and the switching
frequency is imposed by the external elements (Vin,
Lp, Ip, Vout). The MOSFET is turned on at the
minimum drainsource level.
2. The load starts to decrease and the freerunning
frequency hits the internal clamp.
3. The frequency can no longer naturally increase
because of the clamp. The frequency is now controlled
by the internal VCO but remains constant. The peak
current finds no other option that diminishing to satisfy
equation (1).
4. The peak current has reached the internal minimum
ceiling level and is now frozen for the remaining
cycles.
5. To further reduce the transmitted power (V
FB
goes up),
the VCO decreases the switching frequency. In case of
output overshoot, the VCO could decrease the
frequency
down to zero. When the overshoot has gone,
V
FB
diminishes again and the IC smoothly resumes its
operation.
Advantages of the Method
By implementing the aforementioned control scheme, the
NCP1205 brings the following advantages:
Discontinuous only operation: in DCM, the Flyback is
a first order system (at low frequencies) and thus
naturally eases the feedback loop compensation.
A lowcost secondary rectifier can be used due to
smooth turnoff conditions.
Valley switching ensures minimum switching losses
brought by Coss and all the parasitic capacitances.
By folding back the switching frequency, you turn the
system into Pulse Duration Modulation. This method
prevents from generating uncontrolled output ripple as
with hysteretic controllers.
By letting you control the peak current value at which
the frequency goes down, you ensure that this level is
low enough to avoid transformer acoustic noise
generation even at audible frequencies.
Detailed Description
The following sections describe the internal behavior of
the NCP1205.
FreeRunning Operation
As previously said, the operating frequency at nominal load
is dictated by the external elements. We can split the different
switching sections in two separated instants. In the following
text we use the internal error voltage, Verr. This level is
elaborated as Figure 14 portrays. Verr is linked to VFB (pin 4)
by the following formula:
(eq. 2)
Verr
+
10
*
3 VFB
ON time: The ON time is given by the time it takes to
reach the peak current setpoint imposed by the level on FB
pin (pin 4). Since this level is internally divided by three, the
peak setpoint is simply:
Ipk
+
1
3 Rsense
Verr
(eq. 3)
The rising slope of the peak current is also dependent on
the inductance value and the rectified DC input voltage by:
dIL
dt
+
VinDC
Lp
(eq. 4)
By combining both equations, we obtain the ON time
definition:
ton
+
Lp
VinDC
Ip
+
Lp VERR
VinDC 3 Rsense
(eq. 5)
OFF time: The time taken by the demagnetization of the
transformer depends on the reset voltage applied at the
switch opening. During the conduction time of the
secondary diode, the primary side of the transformer
undergoes a reflected voltage of: [Np/Ns . (Vf + Vout)]. This
voltage applied on the primary inductance dictates the time
needed to decrease from Ip down to zero:
toff
+
Lp
Np
Ns
(Vout
)
Vf)
(eq. 6)
Ip
+
Lp Verr
Np
Ns
(Vout
)
Vf) 3 Rsense
By adding ton + toff, we obtain the natural switching
frequency of the SMPS operating in Borderline Conduction
Mode (BCM):
(eq. 7)
ton
)
toff
+
Verr Lp
3 Rsense
1
VinDC
)
1
Np
Ns
(Vout
)
Vf)
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11
If we now enter this formula into a spreadsheet, we can easily plot the switching frequency versus the output power demand:
Figure 12. A Typical Behavior of Free Running Systems
with a Smooth Frequency Foldback with the NCP1205
150000
0
250000
50000
100000
200000
0
15
10
5
SWITCHING FREQUENCY (Hz)
Transition
BCM to VFM
OUTPUT POWER (W)
20
Fmax
Fmax
V
CO
Action
The typical above diagram shows how the frequency
moves with the output power demand. The components used
for the simulation were: Vin = 300 V, Lp = 6.5 mH,
Vout = 10 V, Np/Ns = 12.
The red line indicates where the maximum frequency is
clamped. At this time, the VCO takes over and decreases the
switching frequency to the minimum value.
VCO Operation
The VCO is controlled from the Verr voltage. For Verr
levels above 1.0 V, the VCO frequency remains unchanged
at 125 kHz. As soon as Verr starts to decrease below 1.0 V,
the VCO frequency decreases with a typical smallsignal
slope of 175 kHz/mV @ Verr = 500 mV down to
zero (typically at FB
3.3 V). The demagnetization
synchronization is however kept when the Toff expands.
The maximum switching frequency can be altered by
adjusting the Ct capacitor on pin 5. The 125 kHz maximum
operation ensures that the fundamental component stays
external from the international EMI CISPR22
specification beginning.
The following drawing explains the philosophy behind
the idea:
Figure 13. When the Power Demand goes Low, the Peak Current is Frozen and the Frequency Decreases
3 V
1 V
0.75 V
Peak Current is Fixed
Peak current
can change
V
CO
Frequency
is Fixed at 130 kHz
V
CO
Frequency
can Decrease
Internal V
err
BCM Mode
Zero Crossing Detector
To detect the zero primary current, we make use of an
auxiliary winding. By coupling this winding to the primary,
we have a voltage image of the flux activity in the core.
Figure 13 details the shape of the signal in BCM.
The auxiliary winding for demagnetization needs to
be wired in Forward mode. However, the application
note describes an alternative solution showing how to wire
the winding in Flyback as well. As Figure 13 depicts, when
the MOSFET closes, the auxiliary winding delivers
(Naux/Np . Vin). At the switch opening, we couple the
auxiliary winding to the main output power winding and
thus deliver: (Naux/Ns . Vout). When DCM occurs, the
ringing also takes place on the auxiliary winding. As soon
as the level crossesup the internal reference level
(65 mV), a signal is internally sent to restart the MOSFET.
Three different conditions can occur:
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12
1. In BCM, every time the 65 mV line is crossed, the
switch is immediately turnedon. By accounting for
the internal Demag pin capacitance (1015 pF
typical), you can introduce a fixed delay, which,
combined to the propagation delay, allows to precisely
restart in the drainsource valley (minimum voltage
to reduce capacitive losses).
2. When the IC enters VFM, the VCO delivers a pulse
which is internally latched. As soon as the
demagnetization pulse appears, the logic restarts the
MOSFET.
3. As can be seen from Figure 13, the parasitic
oscillations on the drain are subject to a natural
damping, mainly imputed to ohmic losses. At a given
point, the demag activity on the auxiliary winding
becomes too low to be detected. To avoid any restart
problem, the TY72001 features an internal 4.0
s
timeout delay. This timeout runs after each demag
pulse. If within 4.0
s further to a demag pulse no
activity is detected, an internal signal is combined
with the VCO to actually restart the MOSFET
(synchronized with Ct).
Error Amplifier and Fault Detection
The NCP1205 features an internal error amplifier solely
used to detect an overcurrent problem. The application
assumes that all the error gain associated with the precise
reference level is located on the secondary side of the SMPS.
Various solutions can be purposely implemented such as the
TL431 or a dedicated circuit like the MC33341. In the
NCP1205, the internal OPAMP is used to create a virtual
ground permanently biased at 2.5 V (Figure 14), an internal
reference level. By monitoring this virtual ground further
called V(), we have the possibility to confirm the good
behavior of the loop. If by any mean the loop is broken
(shorted optocoupler, open LED etc.) or the regulation
cannot be reached (true output shortcircuit), the OPAMP
network is adjusted in order to no longer be able to ensure
the 2.5 V virtual point V(). If V() passes down the 1.5 V
level (e.g. output shorted) for a time longer than 128 ms, then
the pulses are stopped for 8 x 128 ms. The IC enters a kind
of burst mode with bunch of pulses lasting 128 ms and
repeating every 8 x 128 ms. If the loop is restored within the
8 x 128 ms period, then the pulses are back again on the
output drive (synchronized with UVLO
H
).
Figure 14. Core Reset Detection is done through
an Auxiliary Winding Operated in Forward
2
750.0 U
754.0 U
758.0 U
762.0 U
766.0 U
I
P
= 0
Auxiliary Level
Restart when Demag is too low
65 mV
0 V
Valley
Switching
Drain Level
Possible Demag
4
s
NCP1205
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13
Figure 15. This Typical Arrangement Allows for an Easy Fault Detection Management
+
V()
Ri
50 k
+
+
+
+
2R
R
OCP
Circuitry
Current
Setpoint
V
fb
V
low
1.5 V
V
fb
V1
2.5 V
V
HIGH
= 3 V
V
LOW
= 5 mV
1
2
3
5
6
7
Rf
150 k
Monitor
To illustrate how the system reacts to a variable FB level,
we have entered the above circuit into a SPICE simulator
and observed the output waveforms. When FB is within
regulation, the error flag is low. However, as soon as FB
leaves its normal operating area, the OPAMP can no longer
keep the V() point and either goes to the positive top or
down to zero: the error flag goes high.
Because of the large amount of delay necessary for this
128 ms operation, the capacitor used for the timing is Ct,
connected from ground to pin 5. In normal VFM operation,
this timing capacitor serves as the VCO capacitor and the
error management circuit is transparent. As soon as an error
is detected (error flag goes high), an internal switch routes
Ct to the 128 ms generator. As a first effect, the switching
frequency is no longer controlled by the VCO (if the error
appears during VFM) and the system is relaxed to natural
BCM. The capacitor now ramps up and down to be further
divided and finally create the 128 ms delay.
Figure 16. By Monitoring the Internal Virtual Ground, the System can Detect the Presence of a Fault
Regulation Area
OCP Condition
Error Flag
Virtual Point
FB
1.5 V
1.000 M
3.000 M
5.000 M
7.000 M
9.000 M
6.500
4.500
2.500
500.0 M
NCP1205
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14
As soon as the system recovers from the error, e.g. FB is
back within its regulation area, the IC operation comes back
to normal.
To avoid any system thermal runaway, another internal
8 x 128 ms delay is combined with the previous 128 ms. It
works as follows: the 128 ms delay is provided to account for
any normal transients that engender a temporary loss of
feedback (FB goes toward ground). However, when the
128 ms period is actually over (the feedback is definitively
lost) the IC stops the output driving pulses for a typical
period of 8 x 128 ms. During this mode, the rest of the
functions are still activated. For instance, in lack of pulses,
the selfsupplied being no longer provided, the startup
source turns on and off (when reaching the corresponding
UVLO
L
and UVLO
H
levels), creating an hiccup waveform
on the Vcc line. As soon as the feedback condition is
restored, the 8 x 128 ms is interrupted and, in synchronism
with the Vcc line, the IC is back to normal. The following
diagrams show how this mechanism takes place when FB is
down to zero (optocoupler opened) or up to Vcc
(optocoupler shorted). If we assume that the error is
permanently present, then a burst mode takes place with a
128/8 x 128 = 12.5% dutycycle. The real transmitted
power is thus:
PoutBURST
+
1
2
Lp Ip2 Fsw DutyBURST
Overvoltage Detection (OVP)
OVP detection is done differently on the DIP8 and DIP14
versions. In the DIP8, because of available pin count, the
OVP is accomplished by monitoring the Vcc voltage. On the
DIP14, the device also monitors the Vcc level but in parallel,
the triggering point has been pinout to allow precise OVP
selection. This pin can also be used to externally latchoff
the IC.
As mentioned, Over Voltage Conditions are detected by
monitoring the Vcc level. Figure 17 describes how three
10 V zener plus one 5.0 V zener are connected in series
together with a 18 k
to ground. As soon as Vcc exceeds
40 V typical, a current starts to flow in the 18 k resistor.
When the voltage developed across this element exceeds
2.8 V, an error is triggered and immediately latches the IC
off. In lack of switching pulses, the Vcc capacitor is no
longer refreshed by the auxiliary supply and slowly
discharges toward ground. When the Vcc level crosses
UVLO
L
, a new startup sequence occurs. If the OVP has
gone, normal IC operation takes place. For different OVP
levels, the comparator input is accessible through pin 6 in the
DIP14 option.
Figure 17. In the DIP8 Version, the OVP Pad is not
Pinned Out and is Available with DIP14 Devices Only
+
+
2.8 V
Latched
OVP
5 V
10 V
18 k
10 V
10 V
6
5
4
3
2
1
7
V
CC
8
2 k
OVP
Protecting Pin 1 Against Negative Spikes
As any CMOS controller, NCP1205 is sensitive to
negative voltages that could appear on it's pins. To avoid any
adverse latchup of the IC, we strongly recommend
inserting a 15 k resistor in series with pin 1 and the
highvoltage rail, as shown in Figures 18 and 19. This 15 k
resistor prevents from adversely latching the controller in
case of negative spikes appearing on the bulk capacitor
during the poweroff sequence. Please note that this resistor
does not dissipate any continuous power and can therefore
be of low power type. Two 8.2 k can also be wired in series
to sustain the large DC voltage present on the bulk.
NCP1205
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15
V
CC
Drive
Unit V
CC
Reaches UVLO
L
OVP
UVLO
H
UVLO
L
40 V
8 x 128 ms maximum if loop does not
recover
UVLO
H
UVLO
L
3.5 V
Loop Recovers
Here
1.5 V
V
CC
Drive
V()
128 ms
Arbitrary V
CC
Representation
Figure 18. When the V
CC
Voltage Goes Above the
Maximum Value, the Device Enters Safe Burst Mode
Figure 19. When the Internal V() Passes Below 1.5 V, the IC
Senses a ShortCircuit Event
NCP1205
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16
PACKAGE DIMENSIONS
PDIP8
N SUFFIX
CASE 62605
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
1
4
5
8
F
NOTE 2
A
B
T
SEATING
PLANE
H
J
G
D
K
N
C
L
M
M
A
M
0.13 (0.005)
B
M
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.40
10.16
0.370
0.400
B
6.10
6.60
0.240
0.260
C
3.94
4.45
0.155
0.175
D
0.38
0.51
0.015
0.020
F
1.02
1.78
0.040
0.070
G
2.54 BSC
0.100 BSC
H
0.76
1.27
0.030
0.050
J
0.20
0.30
0.008
0.012
K
2.92
3.43
0.115
0.135
L
7.62 BSC
0.300 BSC
M
---
10
---
10
N
0.76
1.01
0.030
0.040
_
_
NCP1205
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17
PACKAGE DIMENSIONS
PDIP14
P SUFFIX
CASE 64606
ISSUE M
1
7
14
8
B
A
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.715
0.770
18.16
18.80
B
0.240
0.260
6.10
6.60
C
0.145
0.185
3.69
4.69
D
0.015
0.021
0.38
0.53
F
0.040
0.070
1.02
1.78
G
0.100 BSC
2.54 BSC
H
0.052
0.095
1.32
2.41
J
0.008
0.015
0.20
0.38
K
0.115
0.135
2.92
3.43
L
M
---
10 ---
10
N
0.015
0.039
0.38
1.01
_
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
H
G
D
K
C
SEATING
PLANE
N
T
14 PL
M
0.13 (0.005)
L
M
J
0.290
0.310
7.37
7.87
NCP1205
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18
Notes
NCP1205
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19
Notes
NCP1205
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20
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