Semiconductor Components Industries, LLC, 2005
December, 2005 - Rev. 2
1
Publication Order Number:
NCP1308/D
NCP1308
PWM Current-Mode
Controller for Free-Running
Quasi-Resonant Operation
The NCP1308 combines a true current mode modulator and a
demagnetization detector to ensure full borderline/Critical
Conduction Mode in any load/line conditions and minimum drain
voltage switching (Quasi-Resonant operation). Due to its inherent
skip cycle capability, the controller enters burst mode as soon as the
power demand falls below a predetermined level. As this happens at
low peak current, no audible noise can be heard. An internal 10
ms
timer prevents the free-run frequency to exceed a high frequency
(therefore below the 150 kHz CISPR-22 EMI starting limit), while
the skip adjustment capability lets the user select the frequency at
which the burst foldback takes place.
The Dynamic Self-Supply (DSS) drastically simplifies the
transformer design in avoiding the use of an auxiliary winding to
supply the NCP1308. This feature is particularly useful in
applications where the output voltage varies during operation (e.g.
battery chargers). Thanks to its high-voltage technology, the IC is
directly connected to the high-voltage DC rail. As a result, the
short-circuit trip point is not dependent upon any V
CC
auxiliary
level.
The transformer core reset detection is done through an auxiliary
winding which, brought via a dedicated pin. If an OVP is detected on
the V
CC
pin, the IC permanently latches off.
Finally, the continuous feedback signal monitoring implemented
with an Overcurrent fault Protection circuitry (OCP) makes the final
design rugged and reliable.
Features
Free-Running Borderline/Critical Mode Quasi-Resonant Operation
Current-Mode with Adjustable Skip Cycle Capability
Dynamic Self-Supply Type of V
CC
Auto-Recovery Overcurrent Protection
Improved UVLO for V
CC
below 10 V
Latching Overvoltage Protection on V
CC
500 mA Peak Current Source/Sink Capability
Internal 1.0 ms Soft-Start
Internal 10
ms Minimum T
OFF
Adjustable Skip Level
Internal Temperature Shutdown
Internal Leading Edge Blanking
Direct Optocoupler Connection
SPICE Models Available for TRANsient Analysis
This is a Pb-Free Device
Typical Applications
AC-DC Adapters for Notebooks, etc.
Offline Battery Chargers
Consumer Electronics (DVD Players, Set-Top Boxes, TVs, etc.)
Auxiliary Power Supplies (USB, Appliances, TVs, etc.)
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SOIC-8
DR SUFFIX
CASE 751
PIN CONNECTIONS
MARKING
DIAGRAM
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
1
8
1
Dmg
8 HV
2
FB
3
CS
4
GND
6 V
CC
5 Drv
(Top View)
1308
ALYW
G
1
8
7
Device
Package
Shipping
ORDERING INFORMATION
NCP1308DR2G
SOIC-8
(Pb-Free)
2500/Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
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2
Figure 1. Typical Application Schematic
1
8
2
3
4
6
5
7
NCP1308
+
Universal
Network
R*
+
12 V @ 1 A
GND
+
Y1 Type
*Please refer to the application information section.
PIN FUNCTION DESCRIPTION
Pin
Symbol
Function
Description
1
Dmg
Core reset detection
The auxiliary FLYBACK signal ensures discontinuous operation.
2
FB
Sets the peak current setpoint
By connecting an optocoupler to this pin, the peak current setpoint is adjusted
accordingly to the output power demand. By bringing this pin below the internal
skip level, the device shuts off.
3
CS
Current sense input and skip
cycle level selection
This pin senses the primary current and routes it to the internal comparator via an
LEB By inserting a resistor in series with the pin, you control the level at which the
skip operation takes place.
4
GND
The IC ground
-
5
Drv
Driving pulses
The driver's output to an external MOSFET.
6
V
CC
Supplies the IC
This pin is connected to an external bulk capacitor of typically 10
m
F. If an auxiliary
winding brings this pin above 16 V typical, the circuit permanently latches off.
7
NC
-
This unconnected pin ensures adequate creepage distance.
8
HV
High-voltage pin
Connected to the high-voltage rail, this pin injects a constant current into the V
CC
bulk capacitor.
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Figure 2. Internal Circuit Architecture
HV
V
CC
GND
Dmg
7 mA
To Internal
Supply
+
+
12 V
10 V
5.3 V (Fault)
Fault
Mngt.
PON
16 V
+
OVP
+
Dmg
10 us
Blanking
S
S
R
R
Q
Q
+
+
-
Overload?
5 us
Timeout
Time
Reset
Dmg
380 ns
LEB
1 V
/3
200
m
A
when DRV
is OFF
FB
Driver src = 20 sink = 10
Drv
CS
+
50 mV
10 V
Resd
-
+
VUVLO
+
Soft-Start = 1 ms
50 us
Filter
20k
To internal supply
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
V
CC
, Drv
20
V
Maximum Voltage on all other pins except Pin 8 (HV), Pin 6 (V
CC
) and Pin 5 (Drv) and
Pin 1 (Dmg)
-
-0.3 to 10
V
Maximum Current into all pins except V
CC
(6), HV (8) and Dmg (1) when 10 V ESD diodes
are activated
-
5.0
mA
Maximum Current in Pin 1
Idem
+3.0/-2.0
mA
Thermal Resistance, Junction-to-Case
R
q
JC
57
C/W
Thermal Resistance, Junction-to-Air
R
q
JA
178
C/W
Maximum Junction Temperature
TJ
MAX
150
C
Temperature Shutdown
-
155
C
Hysteresis in Shutdown
-
30
C
Storage Temperature Range
-
-60 to +150
C
ESD Capability, Human Body Model (All pins except HV)
-
2.0
kV
ESD Capability, Machine Model
-
200
V
Maximum Voltage on Pin 8 (HV), Pin 6 (V
CC
) Decoupled to Ground with 10
m
F
V
HVMAX
500
V
Minimum Voltage on Pin 8 (HV), Pin 6 (V
CC
) Decoupled to Ground with 10
m
F
V
HVMIN
40
V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
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4
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25
C, for min/max values T
J
= 0
C to +125
C, Max T
J
= 150
C,
V
CC
= 11 V unless otherwise noted.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
DYNAMIC SELF SUPPLY
V
CC
Increasing Level at which the Current Source Turns-Off
6
VCC
OFF
10.8
12
12.9
V
V
CC
Decreasing Level at which the Current Source Turns-On
6
VCC
ON
9.1
10
10.6
V
V
CC
Decreasing Level at which the Latchoff Phase Ends
6
VCC
latch
-
5.3
-
V
V
CC
Level at which pulses are disabled
6
VUVLO
-
VCC
ON
-
200 mV
-
V
Internal IC Consumption, No Output Load on Pin 5, F
SW
= 60 kHz
6
ICC1
-
1.0
1.3
(Note 1)
mA
Internal IC Consumption, 1.0 nF Output Load on Pin 5, F
SW
= 60 kHz
6
ICC2
-
1.6
2.0
(Note 1)
mA
Internal IC Consumption, Latchoff Phase, V
CC
= 6.0 V
6
ICC3
-
330
-
m
A
INTERNAL STARTUP CURRENT SOURCE ( T
J
= 0
C)
High-Voltage Current Source, V
CC
= 10 V
8
IC1
4.3
7.0
9.6
mA
High-Voltage Current Source, V
CC
= 0
8
IC2
-
8.0
-
mA
DRIVE OUTPUT
Output Voltage Rise-Time @ CL = 1.0 nF, 10-90% of Output Signal
5
T
r
-
40
-
ns
Output Voltage Fall-Time @ CL = 1.0 nF, 10-90% of Output Signal
5
T
f
-
20
-
ns
Source Resistance
5
R
OH
12
20
36
W
Sink Resistance
5
R
OL
5.0
10
20
W
CURRENT COMPARATOR
Input Bias Current @ 1.0 V Input Level on Pin 3
3
I
IB
-
0.02
-
m
A
Maximum Internal Current Setpoint
3
I
Limit
0.92
1.0
1.12
V
Propagation Delay from Current Detection to Gate OFF State
3
T
DEL
-
100
160
ns
Leading Edge Blanking Duration
3
T
LEB
-
380
-
ns
Internal Current Offset Injected on the CS Pin During OFF Time
3
Iskip
-
200
-
m
A
OVERVOLTAGE SECTION
Voltage on the V
CC
above which the controller latches off
6
VOVP
14.3
16
17.8
V
Integration Time Constraint on the OVP comparator
6
Tint
-
50
-
m
s
FEEDBACK SECTION (V
CC
= 11 V, Pin 5 loaded by 1.0 k
W
)
Internal Pullup Resistor
2
Rup
-
20
-
k
W
Pin 3 to Current Setpoint Division Ratio
-
Iratio
-
3.3
-
-
Internal Soft-Start
-
Tss
-
1.0
-
ms
DEMAGNETIZATION DETECTION BLOCK
Input Threshold Voltage (Vpin 1 Decreasing)
1
V
th
35
50
90
mV
Hysteresis (Vpin 1 Decreasing)
1
V
H
-
20
-
mV
Input Clamp Voltage
High State (Ipin 1 = 3.0 mA)
Low State (Ipin 1 = -2.0 mA)
1
1
VC
H
VC
L
8.0
-0.9
10
-0.7
12
-0.5
V
Dmg Propagation Delay
1
T
dem
-
210
-
ns
Internal Input Capacitance at Vpin 1 = 1.0 V
1
C
par
-
10
-
pF
Minimum T
OFF
(Internal Blanking Delay After T
ON
)
1
T
blank
-
10
-
m
s
Timeout After Last Dmg Transition
1
Tout
-
5.0
-
m
s
1. Max value at T
J
= 0
C, please see characterization curves.
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TYPICAL CHARACTERISTICS
0
20
40
60
80
100
120
Figure 3. Demagnetization Threshold
vs. Temperature
-25
0
25
50
75
100
125
TEMPERATURE (
C)
V
TH
, (mV)
-25
0
25
50
75
100
125
TEMPERATURE (
C)
I
lim
it
, (V)
1.20
Figure 4. Maximum Peak Current Setpoint
vs. Temperature
1.15
1.10
1.05
1.00
0.95
0.90
Figure 5. OVP Level Threshold vs. Temperature
TEMPERATURE (
C)
V
CC
, (V)
15
16
16
17
17
18
18
-25
0
25
50
75
100
125
0.40
0.60
0.80
1.00
1.20
1.40
1.60
Figure 6. Internal IC Consumption
(No Output Load) vs. Temperature
-25
0
25
50
75
100
125
TEMPERATURE (
C)
I
CC1
, (mA)
TEMPERATURE (
C)
I
CC2
, (mA)
Figure 7. Internal IC Consumption (1.0 nF Load)
vs. Temperature
2.00
-25
0
25
50
75
100
125
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
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TYPICAL CHARACTERISTICS
TEMPERATURE (
C)
VCC
ON
, (V)
9.0
9.2
9.4
9.6
9.8
10.0
10.2
10.4
10.6
10.8
11.0
TEMPERATURE (
C)
VCC
OF
F
, (V)
12.90
-25
0
25
50
75
100
125
12.40
11.90
11.40
10.90
10.40
Figure 8. V
CC
Increasing Level at which the
Current Source Turns-off vs. Temperature
Figure 9. V
CC
Decreasing Level at which the
Current Source Turns-on vs. Temperature
2
3
4
5
6
7
8
9
10
11
12
TEMPERATURE (
C)
I
C1
, (mA)
-25
0
25
50
75
100
125
Figure 10. Internal Startup Current Source,
V
CC
= 10 V vs. Temperature
TEMPERATURE (
C)
R
OH
and R
OL
(
W
)
-25
0
25
50
75
100
125
0
5
10
15
20
25
30
35
40
R
OH
R
OL
Figure 11. Source and Sink Resistance vs.
Temperature
-25
0
25
50
75
100
125
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7
APPLICATION INFORMATION
INTRODUCTION
The NCP1308 implements a standard current mode
architecture where the switch-off time is dictated by the
peak current setpoint, whereas the core reset detection
triggers the turn-on event. This component represents the
ideal candidate where low part-count is the key parameter,
particularly in low-cost AC/DC adapters, consumer
electronics, auxiliary supplies, etc. Due to its
high-performance High-Voltage technology, the
NCP1308 incorporates all the necessary
components/features needed to build a rugged and reliable
Switch-Mode Power Supply (SMPS):
Transformer Core Reset Detection: Borderline/critical
operation is ensured whatever the operating conditions
are. As a result, there are virtually no primary switch
turn-on losses and no secondary diode recovery
losses. The converter also stays a first-order system
and accordingly eases the feedback loop design.
Quasi-Resonant Operation: By delaying the turn-on
event, it is possible to restart the MOSFET in the
minimum of the drain-source wave, ensuring reduced
EMI/video noise perturbations. In nominal power
conditions, the NCP1308 operates in Borderline
Conduction Mode (BCM) also called Critical
Conduction Mode (CCM).
Dynamic Self-Supply (DSS): Due to its Very High
Voltage Integrated Circuit (VHVIC) technology, ON
Semiconductor 's NCP1308 allows for a direct pin
connection to the high-voltage DC rail. A dynamic
current source charges up a capacitor and thus
provides a fully independent V
CC
level to the
NCP1308. As a result, there is no need for an auxiliary
winding to supply the IC, whose management is
always a problem in variable output voltage designs
(e.g. battery chargers).
Overvoltage Protection (OVP): By monitoring the
V
CC
pin via a 50
ms time constant filter, the NCP1308
goes into latched fault condition whenever an
overvoltage condition is detected. This occurs if V
CC
goes above 16 V typically. The controller stays fully
latched in this position until the V
CC
is cycled down to
4 V, e.g. when the user unplugs the power supply from
the mains outlet and re-plugs it.
Adjustable Skip Cycle Level: By offering the ability
to tailor the level at which the skip cycle takes place,
the designer can make sure that the skip operation
only occurs at low peak current. This point guarantees
a noise-free operation with cheap transformer. This
option also offers the ability to fix the maximum
switching frequency when entering light load conditions.
Overcurrent Protection (OCP): By continuously
monitoring the FB line activity, NCP1308 enters burst
mode as soon as the power supply undergoes an
overload. The device enters a safe low power
operation that prevents from any lethal thermal
runaway. As soon as the default disappears, the power
supply resumes operation. Unlike other controllers,
overload detection is performed independently of any
auxiliary winding level. In presence of a bad coupling
between both power and auxiliary windings, the short
circuit detection can be severely affected. The DSS
naturally shields you against these troubles.
Dynamic Self-Supply
The DSS principle is based on the charge/discharge of the
V
CC
bulk capacitor from a low level up to a higher level.
We can easily describe the current source operation with
some simple logical equations:
POWER-ON: IF V
CC
< VCC
OFF
THEN Current Source
is ON, no output pulses
IF V
CC
decreasing > VCC
ON
THEN
Current Source is OFF, output is pulsing
IF V
CC
increasing < VCC
OFF
THEN
Current Source is ON, output is pulsing
Typical values are: VCC
OFF
= 12 V, VCC
ON
= 10 V
To better understand the operational principle, the
diagram in Figure 12 offers the necessary light:
Vripple = 2V
VCC OFF
= 12V
VCC ON = 10V
ON
OFF
Output pulses
V
CC
CURRENT
SOURCE
Figure 12. The Charge/Discharge Cycle over a 10
m
F
V
CC
Capacitor
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The DSS behavior actually depends on the internal IC
consumption and the MOSFET's gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg equals 22 nC
(max). With a maximum switching frequency selected at
75 kHz, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is:
FSW
@
Qg
@
VCC
with:
F
SW
= maximum switching frequency
Qg = MOSFET's gate charge
V
CC
= V
GS
level applied to the gate
To obtain the output current, simply divide this result by
V
CC
:
Idriver
+
FSW
@
Qg
+
1.6 mA
. The total standby
power consumption at no-load will therefore heavily rely
on the internal IC consumption plus the above driving
current (altered by the driver's efficiency). Suppose that
the IC is supplied from a 350 VDC line. The current
flowing through Pin 8 is a direct image of the NCP1308
consumption (neglecting the switching losses of the HV
current source). If I
CC2
equals 2.3 mA @ T
J
= 60
C, then
the power dissipated (lost) by the IC is simply:
350 V x 2.3 mA = 805 mW. For design and reliability
reasons, it would be interesting to reduce this source of
wasted power that increases the die temperature. This can
be achieved by using different methods:
1. Use a MOSFET with lower gate charge Qg
2. Connect a diode to the half-wave portion to
directly supply the HV pin:
Figure 13. The Connection to the Half-Wave Signal
Reduces the Dissipated Power on the Controller
1
8
2
3
4
6
5
7
Cbulk
1N4007
MAINS
HV
1
2
5
6
3. Permanently force the V
CC
level above VCC
ON
with an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self-supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. Make sure the auxiliary
voltage never exceeds the 16 V limit. When the
power supply is switched off, an internal
comparator makes sure that all output pulses are
disable when V
CC
crosses VCC
ON
.
Skipping Cycle Mode
The NCP1308 automatically skips switching cycles
when the output power demand drops below a given level.
This is accomplished by monitoring the FB pin. In normal
operation, Pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so-called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 14)
and follows the following formula:
1
2
@
Lp
@
Ip2
@
FSW
@
Dburst
with:
Lp = primary inductance
F
SW
= switching frequency within the burst
Ip = peak current at which skip cycle occurs
D
burst
= burst width/burst recurrence
Figure 14. The Skip Cycle Takes Place at Low Peak
Currents which Guarantees Noise-Free Operation
0
300
200
100
MAX PEAK
CURRENT
WIDTH
RECURRENCE
SKIP CYCLE
CURRENT LIMIT
NORMAL CURRENT
MODE OPERATION
CURRENT SENSE SIGNAL (mV)
+
-
RESET
DRIVER
R
sense
R
skip
+
DRIVER = HIGH ? I = 0
DRIVER = LOW ? I = 200
m
A
2
3
Figure 15. A Patented Method Allows for Skip
Level Selection via a Series Resistor Inserted in
Series with the Current
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The skip level selection is done through a simple resistor
inserted between the current sense input and the sense
element. Every time the NCP1308 output driver goes low,
a 200
mA source forces a current to flow through the sense
pin (Figure 15): when the driver is high, the current source
is off and the current sense information is normally
processed. As soon as the driver goes low, the current
source delivers 200
mA and develops a ground-referenced
voltage across R
skip
. If this voltage is below the feedback
voltage, the current sense comparator stays in the high state
and the internal latch can be triggered by the next clock
cycle. Now, if because of a low load mode the feedback
voltage is below R
skip
level, then the current sense
comparator permanently resets the latch and the next clock
cycle (given by the demagnetization detection) is ignored:
we are skipping cycles as shown in Figure 15. As soon as
the feedback voltage goes up again, there can be two
situations: the recurrent period is small and a new
demagnetization detection (next wave) signal triggers the
NCP1308. To the opposite, in low output power conditions,
no more ringing waves are present on the drain and the
toggling of the current sense comparator together with the
internal 5
ms timeout initiates a new cycle start. In normal
operating conditions, e.g. when the drain oscillations are
generous, the demagnetization comparator can detect the
50 mV crossing and gives the "green light", alone, to
re-active the power switch. However, when skip cycle
takes place (e.g. at low output power demands), the restart
event slides along the drain ringing waveforms (actually
the valley locations) which decays more or less quickly,
depending on the L
primary
-C
parasitic
network damping
factor. The situation can thus quickly occur where the
ringing becomes too weak to be detected by the
demagnetization comparator: it then permanently stays
locked in a given position and can no longer deliver the
"green light" to the controller. To help in this situation, the
NCP1308 implements a 5
ms timeout generator: each time
the 50 mV crossing occurs, the timeout is reset. So, as long
as the ringing becomes too low, the timeout generator starts
to count and after 5
ms, it delivers its "green light". If the
skip signal is already present then the controller restarts;
otherwise the logic waits for it to set the drive output high.
Figure 16 depicts these two different situations:
Figure 16. When the primary natural ringing becomes too low, the internal Timeout
together with the sense comparator initiates a new cycle when FB passes the skip level.
Dmg Restart
Current Sense and Timeout Restart
5
m
s
5
m
s
Drain
Signal
Timeout
Signal
Drain
Signal
Timeout
Signal
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Demagnetization Detection
The core reset detection is done by monitoring the
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 17.
Figure 17. Core Reset Detection is Done through
a Dedicated Auxiliary Winding Monitoring
POSSIBLE
RESTARTS
50 mV
7.0
5.0
3.0
1.0
-1.0
0 V
DMG SIGNAL (V)
An internal timer prevents any restart within 10
s
further to the driver going-low transition. This prevents the
switching frequency to exceed (1/(T
ON
+ 10
ms)) but also
avoid false leakage inductance tripping at turn-off. In some
cases, the leakage inductance kick is so energetic, that a
slight filtering is necessary.
The NCP1308 demagnetization detection pad features a
specific component arrangement as detailed by Figure 18.
In this picture, the Zener diodes network protect the IC
against any potential ESD discharge that could appear on
the pins. The first ESD diode connected to the pad, exhibits
a parasitic capacitance. When this parasitic capacitance
(10 pF typically) is combined with R
dem
, a restart delay is
created and the possibility to switch right in the
drain-source wave exists. This guarantees QR operation
with all the associated benefits (low EMI, no turn-on losses
etc.). R
dem
should be calculated to limit the maximum
current flowing through Pin 1 to less than +3 mA / -2 mA:
if during turn-on, the auxiliary winding delivers -30 V (at
the highest line level), then the minimum R
dem
value is
defined by: (-30 + 0.7. This value will be further increased
to introduce a restart delay and also a slight filtering in case
of high leakage energy.
Figure 18. Internal Pad Implementation
TO INTERNAL
COMPARATOR
Aux
R
esd
R
dem
ESD
ESD
4
1
Figure 19 portrays a typical Vds shot at nominal output
power.
Figure 19. The NCP1308 Operates in
Borderline/Critical Operation
400
300
200
100
0
DRAIN
VOL
T
AGE (V)
Overvoltage Protection
The overvoltage works by monitoring the V
CC
pin via a
comparator and a reference voltage. Figure 20 portrays the
internal arrangement:
Figure 20. OVP Section Circuitry
+
-
50 us
FILTER
+
V
CC
16 V
OVP
COMPARATOR
TO LATCH
A 50
ms time-constant filter prevents any parasitic spikes
superimposed on the V
CC
to adversely trigger the OVP
comparator. When the OVP comparator output goes high,
the NCP1308 fully latches off and stays latched, being
self-supplied by the DSS. The user must unplug the power
supply and wait that the V
CC
comes down below a reset
voltage of typically 4 V.
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Shutting off the NCP1308
Shutdown can easily be implemented through a simple
NPN bipolar transistor as depicted by Figure 21. When
OFF, Q1 is transparent to the operation. When forward
biased, the transistor pulls the FB pin to ground (V
CEsat
200 mV) and permanently disables the IC. A small time
constant on the transistor base will avoid false triggering
Figure 21. A Simple Bipolar Transistor Totally
Disables the IC
1
8
2
3
4
6
5
7
NCP1308
ON/OFF
10 k
10 nF
Q1
Power Dissipation
The SOIC package offers a 178
C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decreasing this number: 12 mm x 12 mm to drop
R
JA
down to 100
C/W with 35 mm copper thickness (1 oz)
or 6.5 mm x 6.5 mm with 70
mm copper thickness (2 oz).
As one can see, the designer must be cautious when using
the SO-8 package to check if its thermal performance is
compatible with the total power dissipation. The power
dissipation is simply Vbulk (high line) x I
DSS,AVG
. The
I
DSS,AVG
parameter can be measured by inserting an
amp-meter in series with the HV pin and compute its
average value.
We therefore recommend the insertion of a resistor from
the bulk connection to the HV pin. This will help to:
1. Avoid negative spikes at turn-off on the HV pin
(see below)
2. Split the power budget between this resistor and
the package. The resistor is calculated by leaving
at least 50 V on pin 8 at minimum input voltage
(suppose 100 Vdc in our case):
Rdrop
v
Vbulkmin
*
50 V
7.0 mA
t
7.1 k
W
.
The power dissipated by the resistor is thus:
Pdrop
+
VdropRMS2
Rdrop
+
99.5 mW
+
(IDSS
@
Rdrop
@
DSSduty-cycle)2
Rdrop
+
(7.0 mA
@
7.1 k
W @
0.286) 2
7.1 k
W
where I
DSS
is the peak DSS capability, DSS
duty-cycle
is the
duty-cycle of the DSS, that is to say, the time it is on and
the time it stays off (DSS
duty-cycle
= on/(on + off) ).
Please refer to the application note AND8069/D
available at www.onsemi.com/pub/ncp1200.
If the power consumption budget is really too high for the
DSS alone, connect a diode between the auxiliary winding
and the V
CC
pin which will disable the DSS operation
(V
CC
> 10 V).
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it
is interesting to implement a true short-circuit protection.
A short-circuit actually forces the output voltage to be at
a low level, preventing a bias current to circulate in the
optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please
note that this can also happen in case of feedback loss, e.g.
a broken optocoupler. To account for this situation,
NCP1308 hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in
a burst manner with a low duty-cycle. The system recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to
the maximum until the output voltage reaches its target and
the feedback loop takes over. This period of time depends
on normal output load conditions and the maximum peak
current allowed by the system. The timeout used by this IC
works with the V
CC
decoupling capacitor: as soon as the
V
CC
decreases from the VCC
OFF
level (typically 12 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCC
ON
level is
reached, the controller stops the driving pulses, prevents
the self-supply current source to restart and puts all the
circuitry in standby, consuming as little as 330
mA typical
(ICC3 parameter). As a result, the V
CC
level slowly
discharges toward 0. When this level crosses 5.3 V typical,
the controller enters a new startup phase by turning the
current source on: V
CC
rises toward 12 V and again delivers
output pulses at the VCC
OFF
crossing point. If the fault
condition has been removed before VCC
ON
approaches,
then the IC continues its normal operation. Otherwise, a
new fault cycle takes place. Figure 22 on the following
page shows the evolution of the signals in presence of a
fault.
NCP1308
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12
If the fault is relaxed during the V
CC
natural fall down sequence, the IC
automatically resumes.
If the fault still persists when V
CC
reached VCC
ON
, then the controller
cuts everything off until recovery.
Figure 22.
TIME
TIME
TIME
INTERNAL
FAULT FLAG
V
CC
12 V
10 V
5.3 V
DRV
DRIVER
PULSES
FAULT IS
RELAXED
FAULT OCCURS HERE
STARTUP PHASE
REGULATION
OCCURS HERE
LATCHOFF
PHASE
Soft-Start
The NCP1308 features an internal 1ms soft-start to
soften the constraints occurring in the power supply during
startup. It is activated during the power on sequence. As
soon as V
CC
reaches VCC
OFF
, the peak current is gradually
increased from nearly zero up to the maximum clamping
level (e.g. 1.0 V). The soft-start is also activated during the
over current burst (OCP) sequence. Every restart attempt
is followed by a soft-start activation. Generally speaking,
the soft-start will be activated when V
CC
ramps up either
from zero (fresh power-on sequence) or 5.3 V, the latchoff
voltage occurring during OCP.
Calculating the V
CC
Capacitor
As the above section describes, the fall down sequence
depends upon the V
CC
level: how long does it take for the
V
CC
line to go from 12 V to 10 V? The required time
depends on the startup sequence of your system, i.e. when
you first apply the power to the IC. The corresponding
transient fault duration due to the output capacitor charging
must be less than the time needed to discharge from 12 V
to 10 V, otherwise the supply will not properly start. The
test consists in either simulating or measuring in the lab
how much time the system takes to reach the regulation at
full load. Let's suppose that this time corresponds to 6ms.
Therefore a V
CC
fall time of 10 ms could be well
appropriated in order to not trigger the overload detection
circuitry. If the corresponding IC consumption, including
the MOSFET drive, establishes at 1.6 mA (e.g. with a
10 nC Qg), we can calculate the required capacitor using
the following formula:
D
t
+ D
V
@
C
i
, with
V = 2 V. Then
for a wanted
t of 10 ms, C equals 9 mF or 22 mF for a
standard value. When an overload condition occurs, the IC
blocks its internal circuitry and its consumption drops to
330
mA typical. This happens at V
CC
= 10 V and it remains
stuck until V
CC
reaches 5.3 V: we are in latchoff phase.
Again, using the calculated 22
mF and 330 mA current
consumption, this latchoff phase lasts: 313 ms.
NCP1308
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13
Protecting Pin 8 Against Negative Spikes
As any CMOS controller, NCP1308 is sensitive to
negative voltages that could appear on its pins (Figure 23).
To avoid any adverse latchup of the IC, we strongly
recommend to insert a resistor in series with pin 8. This
resistor prevents from adversely latching the controller in
case of negative spikes appearing on the bulk capacitor
during the power-off sequence. Please refer to the power
dissipation section of this data sheet to see how to calculate
this element.
Figure 23. A negative spike can occur at mains switch-off if the
quality coefficient of Cbulk-Lp is high enough.
Vbulk
< 0
Vcc
Latch!
Vbulk
Another option consists in adding a diode (or two in
series for safety) from the V
CC
to the bulk capacitor.
Figure 12 details this other option:
Figure 24. A diode will force the V
CC
to decrease at
the same pace the bulk capacitor does, avoiding a
negative ringing on the HV pin.
1
8
2
3
4
6
5
7
Cbulk
1N4007
+
CVCC
+
1N4007
1N4007
or
NCP1308
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Operation Shots
Below are some oscilloscope shots captured at Vin = 120 VDC with a transformer featuring a 800
mH primary inductance:
1
st
Upper Plot: Free run, valley switching operation, Pout = 26 W.
2
nd
Middle Plot: Min Toff clamps the switching frequency and selects
the second valley.
3
rd
Lowest Plot: The skip slices the second valley pattern and will
further expand the burst as Pout goes low.
Figure 25. This plot gathers waveforms captured at three different operating points:
Figure 26. This picture explains how the 200
m
A internal offset
current creates the skip cycle level.
Vrsense (200 mV/div)
Vgate (5 V/div)
200
m
A x Rskip
Current Sense Pin (200 mV/pin)
NCP1308
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Figure 27. The short-circuit protection forces the IC to enter burst
in presence of a secondary overload.
V
CC
(5 V/div)
Vgate (5 V/div)
NCP1308
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16
PACKAGE DIMENSIONS
SOIC-8
DR SUFFIX
CASE 751-07
ISSUE AG
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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NCP1308/D
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