Semiconductor Components Industries, LLC, 2004
October, 2004 - Rev. 7
1
Publication Order Number:
NCP1442/D
NCP1442, NCP1443,
NCP1444, NCP1445
4.0 A 280 kHz/560 kHz
Boost Regulators
The NCP1442/3/4/5 products are 280 kHz/560 kHz switching
regulators with a high efficiency, 4.0 A integrated switch. These parts
operate over a wide input voltage range, from 2.7 V to 30 V. The
flexibility of the design allows the chips to operate in most power
supply configurations, including boost, flyback, forward, inverting,
and SEPIC. The ICs utilize current mode architecture, which allows
excellent load and line regulation, as well as a practical means for
limiting current. Combining high-frequency operation with a highly
integrated regulator circuit results in an extremely compact power
supply solution. The circuit design includes provisions for features
such as frequency synchronization, shutdown, and feedback controls
for either positive or negative voltage regulation.
Part Number
Frequency
Feedback Voltage Polarity
NCP1442
280 kHz
Positive
NCP1443
280 kHz
Negative
NCP1444
560 kHz
Positive
NCP1445
560 kHz
Negative
Features
Pb-Free Packages are Available*
Integrated Power Switch: 4.0 A Guaranteed
Wide Input Range: 2.7 V to 30 V
High Frequency Allows for Small Components
Minimum External Components
Easy External Synchronization
Built-in Overcurrent Protection
Frequency Foldback Reduces Component Stress During an
Overcurrent Condition
Thermal Shutdown with Hysteresis
Regulates Either Positive or Negative Output Voltages
Shut Down Current: 50
mA Maximum
Applications
Boost Converter
Inverting Converter
Distributed Power
Portable Computers
Battery Powered Systems
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
PowerFLEX
]
7-PIN
F SUFFIX
CASE 936J
1
7
NCP1442/4
Pin 1. V
C
2. FB
3. TEST
4. GND
5. V
SW
6. SS
7. V
CC
NCP1443/5
1. V
C
2. TEST
3. NFB
4. GND
5. V
SW
6. SS
7. V
CC
PIN CONNECTIONS AND
MARKING DIAGRAMS
x
= Device Number 2, 3, 4, or 5
A
= Assembly Location
WL = Wafer Lot
Y
= Year
WW = Work Week
NC
P144xF
AWLYWW
NC
P144xT
AWLYWW
1
7
1
7
1
7
7 LEAD, TO-220
T SUFFIX
CASE 821P
PowerFLEX
7-PIN
7 LEAD, TO-220
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2
V
SW
GND
SS
3.3 V
+
NCP1442/4
1
2
3
4
5
6
7
5 V
OUT
/1.5 A
33
m
F
V
C
NC
SS
GND
FB
V
SW
+
MBRS320T3
220 pF
22 k
5.1 k
0.01
m
F
V
CC
33
m
F
33
m
F
7.5 k
GND
10
m
H
+
Figure 1. Application Diagram - NCP1442/4,
3.3 V to 5.0 V/1.5 A Boost Converter
33
m
F
+
33
m
F
+
+
33
m
F
MAXIMUM RATINGS
Rating
Value
Unit
Thermal Resistance Junction-to-Air, TO220-7 Version In Air (Socketed)
Thermal Resistance Junction-to-Air, TO220-7 Version
On Cold Plate (25
C)
66.7
1.45
C/W
Thermal Resistance Junction-to-Air, PowerFLEX on 2.1 sq. in. 1 oz.
53.8
C/W
Junction Temperature Range, T
J
0 to +150
C
Storage Temperature Range, T
STORAGE
-65 to +150
C
Lead Temperature Soldering: Reflow (Note 1)
230 Peak
C
ESD, Human Body Model
2.0
kV
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183
C.
MAXIMUM RATINGS
Pin Name
Pin Symbol
V
MAX
V
MIN
I
SOURCE
I
SINK
IC Power Input
V
CC
30 V
-0.3 V
N/A
200 mA
Shutdown/Sync
SS
30 V
-0.3 V
1.0 mA
1.0 mA
Loop Compensation
V
C
6.0 V
-0.3 V
10 mA
10 mA
Voltage Feedback Input
FB
(NCP1442/4 only)
10 V
-0.3 V
1.0 mA
1.0 mA
Negative Feedback Input
(Transient, 10 ms)
NFB
(NCP1443/5 only)
10 V
-10 V
1.0 mA
1.0 mA
Test Pin
Test
6.0 V
-0.3 V
1.0 mA
1.0 mA
Ground
GND
0.3 V
-0.3 V
9.0 A
10 mA
Switch Input
V
SW
40 V
-0.3 V
10 mA
9.0 A
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ELECTRICAL CHARACTERISTICS
(2.7 V < V
CC
< 30 V; 0
C < T
A
< 85
C; 0
C < T
J
< 125
C; For all NCP1442/3/4/5 specifications
unless otherwise stated.) (See Note 2)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Positive and Negative Error Amplifiers
FB Reference Voltage (NCP1442/4 only)
V
C
tied to FB; measure at FB
1.246
1.276
1.300
V
NFB Reference Voltage (NCP1443/5 only)
V
C
= 1.25 V
-2.60
-2.475
-2.40
V
FB Input Current (NCP1442/4 only)
FB = V
REF
-1.0
0.1
1.0
m
A
NFB Input Current (NCP1443/5 only)
NFB = NV
REF
-16
-10
-5.0
m
A
FB Reference Voltage Line Regulation
(NCP1442/4 only)
V
C
= FB
-0.03
0.01
0.03
%/V
NFB Reference Voltage Line Regulation
(NCP1443/5 only)
V
C
= 1.25 V
-0.05
0.01
0.05
%/V
Positive Error Amp Transconductance
I
VC
=
25
m
A
300
550
800
m
Mho
Negative Error Amp Transconductance
I
VC
=
5.0
m
A
115
160
225
m
Mho
Positive Error Amp Gain
(Note 3)
200
500
-
V/V
Negative Error Amp Gain
(Note 3)
100
180
320
V/V
V
C
Source Current
FB = 1.0 V or NFB = -1.9 V, V
C
= 1.25 V
-90
-50
-25
m
A
V
C
Sink Current
FB = 1.5 V or NFB = -3.1 V, V
C
= 1.25 V
200
460
1500
m
A
V
C
High Clamp Voltage
FB = 1.0 V or NFB = -1.9 V; V
C
sources 25
m
A
1.5
1.64
1.9
V
V
C
Low Clamp Voltage
FB = 1.5 V or NFB = -3.1 V, V
C
sinks 25
m
A
0.30
0.47
0.70
V
V
C
Threshold
Reduce V
C
from 1.5 V until switching stops
0.70
1.05
1.30
V
Oscillator
Base Operating Frequency
NCP1442/3, FB = 1.0 V or NFB = -1.9 V
240
280
320
kHz
Reduced Operating Frequency
NCP1442/3, FB = 0 V or NFB = 0 V
30
68
120
kHz
Maximum Duty Cycle
NCP1442/3
90
96
-
%
Base Operating Frequency
NCP1444/5, FB = 1.0 V or NFB = -1.9 V
480
560
640
kHz
Reduced Operating Frequency
NCP1444/5, FB = 0 V or NFB = 0 V
60
120
160
kHz
Maximum Duty Cycle
NCP1444/5
82
92
-
%
FB Frequency Shift Threshold
Frequency drops to reduced operating frequency
0.36
0.40
0.44
V
NFB Frequency Shift Threshold
Frequency drops to reduced operating frequency
-0.80
-0.68
-0.50
V
Sync/Shutdown
Sync Range
NCP1442/3
-
500
-
kHz
Sync Range
NCP1444/5
-
1000
-
kHz
Sync Pulse Transition Threshold
Rise time = 20 ns
-
2.5
-
V
SS Bias Current
SS = 0 V
SS = 3.0 V
-10
-
-1.0
0.2
-
4.0
m
A
m
A
Shutdown Threshold
-
0.50
0.85
1.20
V
Shutdown Delay
2.7 V
V
CC
12 V
12 V < V
CC
30 V
12
12
100
40
500
400
m
s
m
s
2. For the FR4 suffix parts, production testing is performed at 25
C and 85
C; limits at 0
C are guaranteed by design.
3. Guaranteed by design, not 100% tested in production.
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ELECTRICAL CHARACTERISTICS
(continued) (2.7 V < V
CC
< 30 V; 0
C < T
A
< 85
C; 0
C < T
J
< 125
C; For all
NCP1442/3/4/5 specifications unless otherwise stated.) (See Note 2)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Power Switch
Switch Saturation Voltage
I
SWITCH
= 4.0 A
I
SWITCH
= 10 mA, 2.7 V < V
CC
< 12 V
I
SWITCH
= 10 mA,
12 V < V
CC
< 30 V
-
-
-
0.6
0.14
0.9
1.0
0.5
0.4
V
V
V
Switch Current Limit
50% duty cycle (Note 4)
80% duty cycle (Note 4)
5.0
4.0
6.0
-
8.0
-
A
A
Minimum Pulse Width
FB = 0 V or NFB = 0 V, I
SW
= 4.0 A (Note 4)
200
250
300
ns
Switch Transconductance,
D
I
CC
/
D
IV
SW
2.7 V
V
CC
12 V, 10 mA
I
SW
4.0 A
12 V < V
CC
30 V, 10 mA
I
SW
4.0 A
-
-
8.0
10
30
50
mA/A
Switch Leakage
V
SW
= 40 V, V
CC
= 0V
-
2.0
20
m
A
General
Operating Current
I
SW
= 0
-
15
27
mA
Shutdown Mode Current
V
C
< 0.8 V, SS = 0 V, 2.7 V
V
CC
12 V
V
C
< 0.8 V, SS = 0 V, 12 V
V
CC
30 V
-
-
16
25
60
60
m
A
Minimum Operation Input Voltage
V
SW
switching, maximum I
SW =
10 mA
-
2.2
2.6
V
Thermal Shutdown
(Note 4)
150
180
210
C
Thermal Hysteresis
(Note 4)
-
25
-
C
4. Guaranteed by design, not 100% tested in production.
PACKAGE PIN DESCRIPTION
Package Pin Number
Pin Symbol
Function
1
V
C
Loop compensation pin. The V
C
pin is the output of the error amplifier and is used for loop
compensation, current limit and soft start. Loop compensation can be implemented by a sim-
ple RC network as shown in the application diagram on page 2.
2 (NCP1442/4 only)
FB
Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to
1.276 V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to
20% of the nominal frequency.
2 (NCP1443/5 only)
3 (NCP1442/4 only)
Test
These pins are connected to internal test logic and should either be left floating or tied to
ground. Connection to a voltage between 2.0 V and 6.0 V shuts down the internal oscillator
and leaves the power switch running.
3 (NCP1443/5 only)
NFB
Negative feedback pin. This pin senses a negative output voltage and is referenced to -2.475
V. When the voltage at this pin goes above -0.65 V, chip switching frequency reduces to 20%
of the nominal frequency.
4
GND
Ground pin. This pin provides a ground for the controller circuitry and the internal power
switch. This pin is internally connected to the metal pad of the package to provide an addition-
al ground connection as well as an effective means of dissipating heat.
5
V
SW
High current switch pin. This pin connects internally to the collector of the power switch. The
open voltage across the power switch can be as high as 40 V. To minimize radiation, use a
trace as short as practical.
6
SS
Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly
twice the base frequency. A TTL low will shut the part down and put it into low current mode.
If synchronization is not used, this pin should be either tied high or left floating for normal
operation.
7
V
CC
Input power supply pin. This pin supplies power to the part and should have a bypass capaci-
tor connected to GND.
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5
GND
V
SW
+
-
+
-
+
-
V
CC
SS
NFB
FB
Positive
Error Amp
NCP1443/5
only
NCP1442/4
only
Negative
Error Amp
PWM
Comparator
Ramp
Summer
Slope
Compensation
Thermal
Shutdown
2.0 V
Regulator
Delay
Timer
Sync
Shutdown
Oscillator
Frequency
Shift 5:1
S PWM
Latch
R
Q
Driver
Switch
15 m
W
-0.65 V Detector
0.4 V Detector
1.276 V
250 k
200 k
2.0 V
V
C
5
Figure 2. Block Diagram
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6
T
A
, AMBIENT TEMPERATURE (
C)
0
20
40
60
265
T
A
, AMBIENT TEMPERATURE (
C)
40
60
20
0
80
255
270
250
260
275
290
10
15
0
5
20
Figure 3. Supply Current versus Temperature
V
CC
= 30 V
Figure 4.
D
I
CC
/
D
I
SW
versus Temperature
Figure 5. Switch Saturation Voltage versus
Switch Current
Figure 6. Switching Frequency versus
Temperature (NCP1442/3 Only)
12
8
6
10
0
T
A
, AMBIENT TEMPERATURE (
C)
D
I
CC
/
D
I
SW
(mA/A)
40
60
20
0
80
4
400
0
1.0
0.5
100
500
0
200
600
800
700
300
1.5
2.0
2.5
3.0
3.5
4.0
I
SW
, SWITCH CURRENT (A)
V
CE(sat)
, SWITCH SA
TURA
TION VOL
T
AGE (mV)
2
I
CC
, SUPPL
Y CURRENT (mA)
f, SWITCHING FREQUENCY (kHz)
80
V
FB
, POSITIVE FEEDBACK VOLTAGE (V)
0.42
0.43
0.41
0.40
0.45
0.39
0
25
100
125
Figure 7. Switching Frequency versus
Temperature (NCP1444/5 Only)
Figure 8. Switching Frequency versus Positive
Feedback Voltage
555
585
595
590
T
A
, AMBIENT TEMPERATURE (
C)
f, SWITCHING FREQUENCY (kHz)
0.38
f, SWITCHING FREQUENCY (% of T
ypical)
560
565
570
0
20
50
75
V
CC
= 12 V
V
CC
= 2.7 V
V
CC
= 30 V
V
CC
= 12 V
V
CC
= 2.7 V
D
I
SW
= 2.99 A
V
CC
= 2.7 V
T
A
= 25
C
T
A
= 85
C
280
285
40
60
80
575
580
V
CC
= 12 V
T
A
= 25
C
T
A
= 85
C
0.44
300
295
30
50
10
70
550
600
30
50
10
70
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-0.665 -0.67
V
NFB
, NEGATIVE FEEDBACK VOLTAGE (V)
-0.675
-0.68
-0.685
-0.69
0.23
T
A
, AMBIENT TEMPERATURE (
C)
40
60
20
0
80
0.21
0.25
0.20
0.22
0.26
0.30
50
75
0
25
125
Figure 9. Switching Frequency versus
Negative Feedback Voltage
Figure 10. Feedback Reference Voltage versus
Temperature (NCP1442/4 Only)
Figure 11. Feedback Reference Voltage versus
Temperature (NCP1443/5 Only)
Figure 12. Error Amplifier Bias Current versus
Temperature (NCP1442/3 Only)
1.269
T
A
, AMBIENT TEMPERATURE (
C)
V
FB
, FEEDBACK REFERENCE VOL
T
AGE (V)
40
60
20
0
80
-2.47
-2.50
-2.49
-2.46
0
20
40
60
80
T
A
, AMBIENT TEMPERATURE (
C)
V
FB
, FEEDBACK REFERENCE VOL
T
AGE (V)
1.270
f, SWITCHING FREQUENCY (% of T
ypical)
I
FB
, ERROR AMPLIFIER BIAS CURRENT (
m
A)
-0.695
T
A
, AMBIENT TEMPERATURE (
C)
20
40
0
80
93.0
93.5
97.0
Figure 13. Error Amplifier Bias Current versus
Temperature (NCP1443/5 Only)
Figure 14. Maximum Duty Cycle versus
Temperature
-14
-10
-8
-9
T
A
, AMBIENT TEMPERATURE (
C)
I
NFB
, ERROR AMPLIFIER BIAS CURRENT (
m
A)
D
max
, MAXIMUM DUTY CYCLE (%)
-13
-12
0
20
94.0
95.0
V
CC
= 30 V
V
CC
= 12 V
V
CC
= 2.7 V
V
CC
= 2.7 V
0.28
0.29
40
60
80
-11
V
CC
= 2.7 V
60
100
V
CC
= 12 V
T
A
= 25
C
T
A
= 85
C
1.271
1.272
1.273
1.274
1.275
1.276
V
CC
= 30 V
V
CC
= 12 V
-2.48
0.24
0.27
V
CC
= 2.7 V
V
CC
= 30 V
V
CC
= 12 V
V
CC
= 30 V
12 V
2.7 V
94.5
95.5
96.0
96.5
V
CC
= 12 V
V
CC
= 30 V
30
50
10
70
1.268
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T
A
, AMBIENT TEMPERATURE (
C)
0
20
40
60
T
A
, AMBIENT TEMPERATURE (
C)
40
60
20
0
80
0
50
150
1.08
1.02
1.04
1.00
Figure 15. V
C
Threshold Voltage versus
Temperature
Figure 16. Shutdown Threshold versus
Temperature
Figure 17. Shutdown Delay versus Temperature
(NCP1442)
Figure 18. Shutdown Delay versus Temperature
(NCP1444)
0
T
A
, AMBIENT TEMPERATURE (
C)
V
SS
, SHUTDOWN THRESHOLD (V)
40
60
20
0
80
60
0
20
100
160
120
0
20
40
60
80
T
A
, AMBIENT TEMPERATURE (
C)
T
D
, SHUTDOWN DELA
Y (
m
s)
0.3
V
cth
, THRESHOLD VOL
T
AGE (V)
T
D
, SHUTDOWN DELA
Y (
m
s)
80
V
CC
, SUPPLY VOLTAGE (V)
10
20
15
30
5
0
5
45
Figure 19. I
SS
versus V
SS
Figure 20. Supply Current versus Supply
Voltage During Shutdown
0
0
5
3.0
4.0
3.5
V
SS
(V)
I
SS
(
m
A)
0
I
SD
, SUPPL
Y CURRENT (
m
A)
0.5
1.0
10
15
10
20
V
CC
= 2.7 V
200
250
20
25
30
2.5
25
1.14
0.4
0.6
0.8
1.0
0.9
V
CC
= 30 V
V
CC
= 12 V
40
100
V
CC
= 2.7 V
V
CC
= 30 V
V
CC
= 12 V
15
25
35
40
1.06
1.10
1.12
80
140
2.0
1.5
30
T
A
= 25
C
T
A
= 85
C
30
50
10
70
30
50
10
70
30
50
10
70
0.7
0.5
0.2
0.1
180
30
50
10
70
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T
A
, AMBIENT TEMPERATURE (
C)
0
20
40
60
V
ref
-V
NFB
, FEEDBACK VOLTAGE (mV)
0
0.1
-0.1
0.2
-0.2
-200
-150
-50
100
530
470
480
570
Figure 21. Error Amplifier Transconductance
versus Temperature
Figure 22. Negative Error Amplifier
Transconductance versus Temperature
Figure 23. Error Amplifier Output Current
versus Positive Feedback Voltage
Figure 24. Error Amplifier Output Current versus
Negative Feedback Voltage
-950
T
A
, AMBIENT TEMPERATURE (
C)
gm, TRANSCONDUCT
ANCE (
m
mho)
40
60
20
0
80
-300
-0.2
-0.25
100
-100
-0.15
0
0.05
0.2
0.25
V
ref
-V
FB
, FEEDBACK VOLTAGE (mV)
I
C
, EA OUTPUT CURRENT (
m
A)
-900
gm, TRANSCONDUCT
ANCE (
m
mho)
-0.3
I
C
, EA OUTPUT CURRENT (
m
A)
80
Figure 25. Switch Leakage Current versus
Temperature
3.0
5.0
6.0
5.5
T
A
, AMBIENT TEMPERATURE (
C)
I
SW
, SWITCH LEAKAGE CURRENT (
m
A)
3.5
0
20
0
50
40
60
80
4.5
560
-850
-800
-700
-600
-500
-100
490
540
550
-200
0
4.0
500
510
520
-650
-750
0.1
0.15
-0.1 -0.05
-400
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APPLICATIONS INFORMATION
THEORY OF OPERATION
Current Mode Control
+
-
Driver
C
O
R
LOAD
V
SW
X5
SUMMER
Slope Compensation
V
C
Oscillator
D1
V
CC
S
R
Q
In Out
PWM
Comparator
L
15 m
W
Figure 26. Current Mode Control Scheme
Power Switch
The NCP144X family incorporates a current mode
control scheme, in which the PWM ramp signal is derived
from the power switch current. This ramp signal is compared
to the output of the error amplifier to control the on-time of
the power switch. The oscillator is used as a fixed-frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulse-by-pulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows both a simpler compensation and a higher
gain-bandwidth over a comparable voltage mode circuit.
Without discrediting its apparent merits, current mode
control comes with its own peculiar problems, mainly,
subharmonic oscillation at duty cycles over 50%. The
NCP144X family solves this problem by adopting a slope
compensation scheme in which a fixed ramp generated by
the oscillator is added to the current ramp. A proper slope
rate is provided to improve circuit stability without
sacrificing the advantages of current mode control.
Oscillator and Shutdown
Figure 27. Timing Diagram of Sync and Shutdown
V
SW
Current
Ramp
Sync
The oscillator is trimmed to guarantee frequency
accuracy. The output of the oscillator turns on the power
switch at a frequency of 280 kHz (NCP1442/3) or 560 kHz
(NCP1444/5), as shown in Figure 26. The power switch is
turned off by the output of the PWM Comparator.
A TTL-compatible sync input at the SS pin is capable of
syncing up to 1.8 times the base oscillator frequency. As
shown in Figure 27, in order to sync to a higher frequency,
a positive transition turns on the power switch before the
output of the oscillator goes high, thereby resetting the
oscillator. The sync operation allows multiple power
supplies to operate at the same frequency.
A sustained logic low at the SS pin will shut down the IC
and reduce the supply current.
An additional feature includes frequency shift to 20% of
the nominal frequency when either the NFB or FB pins
trigger the threshold. During power up, overload, or short
circuit conditions, the minimum switch on-time is limited
by the PWM comparator minimum pulse width. Extra
switch off-time reduces the minimum duty cycle to protect
external components and the IC itself.
As previously mentioned, this block also produces a ramp
for the slope compensation to improve regulator stability.
Error Amplifier
+
-
+
-
NCP1443/5
NCP1442/4
Figure 28. Error Amplifier Equivalent Circuit
2.0 V
200 k
250 k
1M
W
positive error-amp
negative error-amp
1.276 V
FB
NFB
V
C
C1
R1
5 k
W
0.01
m
F
Voltage
Clamp
120 pF
For NCP1443/5, the NFB pin is internally referenced to
-2.475 V with approximately a 250 k
W input impedance.
For NCP1442/4, the FB pin is directly connected to the
inverting input of the positive error amplifier, whose
non-inverting input is fed by the 1.276 V reference. Both
amplifiers are transconductance amplifiers with a high
output impedance of approximately 1.0 M
W, as shown in
Figure 28. The V
C
pin is connected to the output of the error
amplifiers and is internally clamped between 0.5 V and
1.7 V. A typical connection at the V
C
pin includes a capacitor
in series with a resistor to ground, forming a pole/zero for
loop compensation.
An external shunt can be connected between the V
C
pin
and ground to reduce its clamp voltage. Consequently, the
current limit of the internal power transistor current is
reduced from its nominal value.
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Switch Driver and Power Switch
The switch driver receives a control signal from the logic
section to drive the output power switch. The switch is
grounded through emitter resistors (15 m
W total) to the
GND pin. The peak switching current is clamped by an
internal circuit. The clamp current is guaranteed to be
greater than 4.0 A and varies with duty cycle due to slope
compensation. The power switch can withstand a maximum
voltage of 40 V on the collector (V
SW
pin). The saturation
voltage of the switch is typically less than 1.0 V to minimize
power dissipation.
Short Circuit Condition
When a short circuit condition happens in a boost circuit,
the inductor current will increase during the whole
switching
cycle, causing excessive current to be drawn from
the input power supply. Since control ICs don't have the
means to limit load current, an external current limit circuit
(such as a fuse or relay) has to be implemented to protect the
load, power supply and ICs.
In other topologies, the frequency shift built into the IC
prevents damage to the chip and external components. This
feature reduces the minimum duty cycle and allows the
transformer secondary to absorb excess energy before the
switch turns back on.
Figure 29. Startup Waveforms of Circuit Shown in
the Application Diagram. Load = 400 mA.
I
L
V
OUT
V
C
V
CC
The NCP144X can be activated by either connecting the
V
CC
pin to a voltage source or by enabling the SS pin.
Startup waveforms shown in Figure 29 are measured in the
boost converter demonstrated in the Block Diagram
(Figure
2). Recorded after the input voltage is turned on, this
waveform shows the various phases during the power up
transition.
When the V
CC
voltage is below the minimum supply
voltage, the V
SW
pin is in high impedance. Therefore,
current conducts directly from the input power source to the
output through the inductor and diode. Once V
CC
reaches
approximately 1.5 V, the internal power switch briefly turns
on. This is a part of the NCP144X's normal operation. The
turn-on of the power switch accounts for the initial current
swing.
When the V
C
pin voltage rises above the threshold, the
internal power switch starts to switch and a voltage pulse can
be seen at the V
SW
pin. Detecting a low output voltage at the
FB pin, the built-in frequency shift feature reduces the
switching frequency to a fraction of its nominal value,
reducing the minimum duty cycle, which is otherwise
limited by the minimum on-time of the switch. The peak
current during this phase is clamped by the internal current
limit.
When the FB pin voltage rises above 0.4 V, the frequency
increases to its nominal value, and the peak current begins
to decrease as the output approaches the regulation voltage.
The overshoot of the output voltage is prevented by the
active pull-on, by which the sink current of the error
amplifier is increased once an overvoltage condition is
detected. The overvoltage condition is defined as when the
FB pin voltage is 50 mV greater than the reference voltage.
COMPONENT SELECTION
Frequency Compensation
The goal of frequency compensation is to achieve
desirable transient response and DC regulation while
ensuring the stability of the system. A typical compensation
network, as shown in Figure 30, provides a frequency
response of two poles and one zero. This frequency response
is further illustrated in the Bode plot shown in Figure 31.
NCP1442/3/4/5
Figure 30. A Typical Compensation Network
V
C
GND
C1
R1
C2
The high DC gain in Figure 31 is desirable for achieving
DC accuracy over line and load variations. The DC gain of
a transconductance error amplifier can be calculated as
follows:
GainDC
+
GM
RO
where:
G
M
= error amplifier transconductance;
R
O
= error amplifier output resistance
1.0 M
W.
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The low frequency pole, f
P1,
is determined by the error
amplifier output resistance and C1 as:
fP1
+
1
2
p
C1RO
The first zero generated by C1 and R1 is:
fZ1
+
1
2
p
C1R1
The phase lead provided by this zero ensures that the loop
has at least a 45
phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
fP
+
1
2
p
CORLOAD
where:
C
O
= equivalent output capacitance of the error amplifier
120pF;
R
LOAD
= load resistance.
The high frequency pole, f
P2
, can be placed at the output
filter's ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
fP2
+
1
2
p
C2R1
One simple method to ensure adequate phase margin is to
design the frequency response with a -20 dB per decade
slope, until unity-gain crossover. The crossover frequency
should be selected at the midpoint between f
Z1
and f
P2
where
the phase margin is maximized.
Figure 31. Bode Plot of the Compensation Network
Shown in Figure 30
Frequency (LOG)
f
P1
Gain (dB)
DC Gain
f
Z1
f
P2
Negative Voltage Feedback
Since the negative error amplifier has finite input
impedance as shown in Figure 32, its induced error has to be
considered. If a voltage divider is used to scale down the
negative output voltage for the NFB pin, the equation for
calculating output voltage is:
*
VOUT
+
*
2.475 (R1
)
R2)
R2
*
10
m
A
R1
+
-
Figure 32. Negative Error Amplifier and NFB Pin
2 V
200 k
W
Negative Error-Amp
R
P
NFB
R
IN
-V
OUT
R1
250 k
W
R2
It is shown that if R1 is less than 10 k, the deviation from
the design target will be less than 0.1 V. If the tolerances of
the negative voltage reference and NFB pin input current are
considered, the possible offset of the output V
OFFSET
varies
in the range of:
*
0.0.5 (R1
)
R2)
R2
*
(15
m
A
R1)
v
VOFFSET
v
0.0.5 (R1
)
R2)
R2
*
(5
m
A
R1)
V
SW
Voltage Limit
In the boost topology, V
SW
pin maximum voltage is set by
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes:
VSW(MAX)
+
VOUT(MAX)
)
VF
where:
V
F
= output diode forward voltage.
In the flyback topology, peak V
SW
voltage is governed by:
VSW(MAX)
+
VCC(MAX)
)
(VOUT
)
VF)
N
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
spike superimposed on top of the steady-state voltage.
Usually this voltage spike is caused by transformer leakage
inductance charging stray capacitance between the V
SW
and
GND pins. To prevent the voltage at the V
SW
pin from
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
the V
SW
pin and ground.
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Magnetic Component Selection
When choosing a magnetic component, one must consider
factors such as peak current, core and ferrite material, output
voltage ripple, EMI, temperature range, physical size and
cost. In boost circuits, the average inductor current is the
product of output current and voltage gain (V
OUT
/V
CC
),
assuming 100% energy transfer efficiency. In continuous
conduction mode, inductor ripple current is:
IRIPPLE
+
VCC(VOUT
*
VCC)
(f)(L)(VOUT)
where:
f = 280 kHz for NCP1442/3 and 560 kHz for NCP1444/5.
The peak inductor current is equal to average current plus
half of the ripple current, which should not cause inductor
saturation. The above equation can also be referenced when
selecting the value of the inductor based on the tolerance of
the ripple current in the circuits. Small ripple current
provides the benefits of small input capacitors and greater
output current capability. A core geometry like a rod or
barrel is prone to generating high magnetic field radiation,
but is relatively cheap and small. Other core geometries,
such as toroids, provide a closed magnetic loop to prevent
EMI.
Input Capacitor Selection
In boost circuits, the inductor becomes part of the input
filter, as shown in Figure 34. In continuous mode, the input
current waveform is triangular and does not contain a large
pulsed current, as shown in Figure 33. This reduces the
requirements imposed on the input capacitor selection.
During continuous conduction mode, the peak to peak
inductor ripple current is given in the previous section. As
we can see from Figure 33, the product of the inductor
current ripple and the input capacitor's effective series
resistance (ESR) determine the V
CC
ripple. In most
applications, input capacitors in the range of 10
mF to
100
mF with an ESR less than 0.3 W work well up to a full
4.0 A switch current.
V
CC
ripple
Figure 33. Boost Input Voltage and Current
Ripple Waveforms
I
IN
I
L
+
-
Figure 34. Boost Circuit Effective Input Filter
V
CC
C
IN
R
ESR
I
L
I
IN
The situation is different in a flyback circuit. The input
current is discontinuous and a significant pulsed current is
seen by the input capacitors. Therefore, there are two
requirements for capacitors in a flyback regulator: energy
storage and filtering. To maintain a stable voltage supply to
the chip, a storage capacitor larger than 20
mF with low ESR
is required. To reduce the noise generated by the inductor,
insert a 1.0
mF ceramic capacitor between V
CC
and ground
as close as possible to the chip.
Output Capacitor Selection
Figure 35. Typical Output Voltage Ripple
V
OUT
ripple
I
L
By examining the waveforms shown in Figure 35, we can
see that the output voltage ripple comes from two major
sources, namely capacitor ESR and the
charging/discharging of the output capacitor. In boost
circuits, when the power switch turns off, I
L
flows into the
output capacitor causing an instant
DV = I
IN
ESR. At the
same time, current I
L
- I
OUT
charges the capacitor and
increases the output voltage gradually. When the power
switch is turned on, I
L
is shunted to ground and I
OUT
discharges the output capacitor. When the I
L
ripple is small
enough, I
L
can be treated as a constant and is equal to input
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current I
IN
. Summing up, the output voltage peak-peak
ripple can be calculated by:
VOUT(RIPPLE)
+
(IIN
*
IOUT)(1
*
D)
(COUT)(f)
)
IOUTD
(COUT)(f)
)
IIN
ESR
The equation can be expressed more conveniently in
terms of V
CC
, V
OUT
and I
OUT
for design purposes as
follows:
VOUT(RIPPLE)
+
IOUT(VOUT
*
VCC)
(COUT)(f)
1
(COUT)(f)
)
(IOUT)(VOUT)(ESR)
VCC
The capacitor RMS ripple current is:
IRIPPLE
+
(IIN
*
IOUT)2(1
*
D)
)
(IOUT)2(D)
+
IOUT
VOUT
*
VCC
VCC
Although the above equations apply only for boost
circuits, similar equations can be derived for flyback
circuits.
Reducing the Current Limit
In some applications, the designer may prefer a lower
limit on the switch current than 4.0 A. An external shunt can
be connected between the V
C
pin and ground to reduce its
clamp voltage. Consequently, the current limit of the
internal power transistor current is reduced from its nominal
value.
The voltage on the V
C
pin can be evaluated with the
equation:
VC
+
ISWREAV
where:
R
E
= .015
W, the value of the internal emitter resistor;
A
V
= 5.0 V/V, the gain of the current sense amplifier.
Since R
E
and A
V
cannot be changed by the end user, the
only available method for limiting switch current below
4.0 A is to clamp the V
C
pin at a lower voltage. If the
maximum switch or inductor current is substituted into the
equation above, the desired clamp voltage will result.
A simple diode clamp, as shown in Figure 36, clamps the
V
C
voltage to a diode drop above the voltage on resistor R3.
Unfortunately, such a simple circuit is not generally
acceptable if V
IN
is loosely regulated.
Figure 36. Current Limiting using a Diode Clamp
V
C
D1
V
CC
R1
V
IN
C2
C1
R2
R3
Another solution to the current limiting problem is to
externally measure the current through the switch using a
sense resistor. Such a circuit is illustrated in Figure 37.
-
+
Figure 37. Current Limiting using a Current Sense
Resistor
V
C
R
SENSE
Q1
V
CC
R1
V
IN
C2
C1
R2
C3
Output
Ground
PGND AGND
The switch current is limited to:
ISWITCH(PEAK)
+
VBE(Q1)
RSENSE
where:
V
BE(Q1)
= the base-emitter voltage drop of Q1, typically
0.65 V.
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The improved circuit does not require a regulated voltage
to operate properly. Unfortunately, a price must be paid for
this convenience in the overall efficiency of the circuit. The
designer should note that the input and output grounds are
no longer common. Also, the addition of the current sense
resistor, R
SENSE
, results in a considerable power loss which
increases with the duty cycle. Resistor R2 and capacitor C3
form a low-pass filter to remove noise.
Subharmonic Oscillation
Subharmonic oscillation (SHM) is a problem found in
current-mode control systems, where instability results
when duty cycle exceeds 50%. SHM only occurs in
switching regulators with a continuous inductor current.
This instability is not harmful to the converter and usually
does not affect the output voltage regulation. SHM will
increase the radiated EM noise from the converter and can
cause, under certain circumstances, the inductor to emit
high-frequency audible noise.
SHM is an easily remedied problem. The rising slope of
the inductor current is supplemented with internal "slope
compensation" to prevent any duty cycle instability from
carrying through to the next switching cycle. In the
NCP144X family, slope compensation is added during the
entire switch on-time, typically in the amount of
180 mA/
ms.
In some cases, SHM can rear its ugly head despite the
presence of the onboard slope compensation. The simple
cure to this problem is more slope compensation to avoid the
unwanted oscillation. In that case, an external circuit, shown
in Figure 38, can be added to increase the amount of slope
compensation used. This circuit requires only a few
components and is "tacked on" to the compensation
network.
Figure 38. Technique for Increasing Slope
Compensation
V
C
R1
C2
C1
R2
R3
V
SW
C3
V
SW
The dashed box contains the normal compensation
circuitry to limit the bandwidth of the error amplifier.
Resistors R2 and R3 form a voltage divider off of the V
SW
pin. In normal operation, V
SW
looks similar to a square
wave, and is dependent on the converter topology. Formulas
for calculating V
SW
in the boost and flyback topologies are
given in the section "V
SW
Voltage Limit." The voltage on
V
SW
charges capacitor C3 when the switch is off, causing
the voltage at the V
C
pin to shift upwards. When the switch
turns on, C3 discharges through R3, producing a negative
slope at the V
C
pin. This negative slope provides the slope
compensation.
The amount of slope compensation added by this circuit
is
D
I
D
T
+
VSW
R3
R2
)
R3
1
*
e
*
(1
*
D)
R3C3fSW
fSW
(1
*
D)REAV
where:
DI/DT = the amount of slope compensation added (A/s);
V
SW
= the voltage at the switch node when the transistor
is turned off (V);
f
SW
= the switching frequency, typically 280 kHz
(NCP1442/3) or 560 kHz (NCP1444/5) (Hz);
D = the duty cycle;
R
E
= 0.015
W, the value of the internal emitter resistor;
A
V
= 5.0 V/V, the gain of the current sense amplifier.
In selecting appropriate values for the slope compensation
network, the designer is advised to choose a convenient
capacitor, then select values for R2 and R3 such that the
amount of slope compensation added is 100 mA/
ms. Then
R2 may be increased or decreased as necessary. Of course,
the series combination of R2 and R3 should be large enough
to avoid drawing excessive current from V
SW
. Additionally,
to ensure that the control loop stability is improved, the time
constant formed by the additional components should be
chosen such that:
R3C3
t
1
*
D
fSW
Finally, it is worth mentioning that the added slope
compensation is a trade-off between duty cycle stability and
transient response. The more slope compensation a designer
adds, the slower the transient response will be, due to the
external circuitry interfering with the proper operation of the
error amplifier.
Soft-Start
Through the addition of an external circuit, a soft-start
function can be added to the NCP1442/3/4/5 family of
components. Soft-start circuitry prevents the V
C
pin from
slamming high during startup, thereby inhibiting the
inductor current from rising at a high slope.
This circuit, shown in Figure 39, requires a minimum
number of components and allows the soft-start circuitry to
activate any time the SS pin is used to restart the converter.
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Figure 39. Soft-Start
V
C
R1
C2
C1
D2
D1
V
CC
C3
V
IN
SS
SS
Resistor R1 and capacitors C1 and C2 form the
compensation
network. At turn on, the voltage at the V
C
pin
starts to come up, charging capacitor C3 through Schottky
diode D2, clamping the voltage at the V
C
pin such that
switching begins when V
C
reaches the V
C
threshold,
typically 1.05 V (refer to graphs for detail over
temperature).
VC
+
VF(D2)
)
VC3
Therefore, C3 slows the startup of the circuit by limiting
the voltage on the V
C
pin. The soft-start time increases with
the size of C3.
Diode D1 discharges C3 when SS is low. If the shutdown
function is not used with this part, the cathode of D1 should
be connected to V
IN
.
Calculating Junction Temperature
To ensure safe operation of the NCP1442/3/4/5, the
designer must calculate the on-chip power dissipation and
determine its expected junction temperature. Internal
thermal protection circuitry will turn the part off once the
junction temperature exceeds 180
C
30
. However,
repeated operation at such high temperatures will ensure a
reduced operating life.
Calculation of the junction temperature is an imprecise
but simple task. First, the power losses must be quantified.
There are three major sources of power loss on the
NCP144X:
biasing of internal control circuitry, P
BIAS
switch driver, P
DRIVER
switch saturation, P
SAT
The internal control circuitry, including the oscillator and
linear regulator, requires a small amount of power even
when the switch is turned off. The specifications section of
this datasheet reveals that the typical operating current, I
Q
,
due to this circuitry is 5.5 mA. Additional guidance can be
found in the graph of operating current vs. temperature. This
graph shows that IQ is strongly dependent on input voltage,
V
IN
, and the ambient temperature, T
A
. Then:
PBIAS
+
VINIQ
Since the onboard switch is an NPN transistor, the base
drive current must be factored in as well. This current is
drawn from the V
IN
pin, in addition to the control circuitry
current. The base drive current is listed in the specifications
as
DI
CC
/
DI
SW
, or switch transconductance. As before, the
designer will find additional guidance in the graphs. With
that information, the designer can calculate:
PDRIVER
+
VINISW
ICC
D
ISW
D
where:
I
SW
= the current through the switch;
D = the duty cycle or percentage of switch on-time.
I
SW
and D are dependent on the type of converter. In a
boost converter,
ISW(AVG)
^
ILOAD
D
I
efficiency
D
^
VOUT
*
VIN
VOUT
In a flyback converter,
ISW(AVG)
^
VOUTILOAD
VIN
I
efficiency
D
^
VOUT
VOUT
)
ns
np
VIN
where:
n
s
= number of turns in the transformer secondary winding.
n
p
= number of turns in the transformer primary winding.
The switch saturation voltage, V
(CE)SAT
, is the last major
source of on-chip power loss. V
(CE)SAT
is the
collector-emitter voltage of the internal NPN transistor
when it is driven into saturation by its base drive current. The
value for V
(CE)SAT
can be obtained from the specifications
or from the graphs, as "Switch Saturation Voltage." Thus,
PSAT
^
V(CE)SATISW
D
Finally, the total on-chip power losses are:
PD
+
PBIAS
)
PDRIVER
)
PSAT
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Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
gradient is expressed in manufacturers' data sheets as
q
JA
,
or junction-to-ambient thermal resistance. The on-chip
junction temperature can be calculated if
q
JA
, the air
temperature near the surface of the IC, and the on-chip
power dissipation are known.
TJ
+
TA
)
(PD
q
JA)
where:
T
J
= IC or FET junction temperature (
C);
T
A
= ambient temperature (
C);
P
D
= power dissipated by part in question (W);
q
JA
= junction-to-ambient thermal resistance (
C/W).
For ON Semiconductor components, the value for
q
JA
can
be found on page 19 of the datasheet, under "Package
Thermal Data." Note that this value is different for every
package style and every manufacturer. For the NCP144X,
q
JA
varies between 10-50
C/W, depending upon the size of
the copper pad to which the IC is mounted.
Once the designer has calculated T
J
, the question of
whether the NCP144X can be used in an application is
settled. If T
J
exceeds 150
C, the absolute maximum
allowable junction temperature, the NCP144X is not
suitable for that application.
If T
J
approaches 150
C, the designer should consider
possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
surface of the chip might be considered to reduce T
A
. A
copper "landing pad" can be connected to ground -
designers are referred to ON Semiconductor applications
note SR006 for more information on properly sizing a
copper area.
Circuit Layout Guidelines
In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage
transitions
that can cause problems. Therefore the following
guidelines should be followed in the layout.
1. In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
on-chip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
on-chip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.
2. Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.
3. Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.
NCP1442, NCP1443, NCP1444, NCP1445
http://onsemi.com
18
ORDERING INFORMATION
Device
Operating
Temperature Range
Package
Shipping
NCP1442FR4
7 Lead PowerFLEX Short-Leaded
2000 Tape & Reel
NCP1442FR4G
7 Lead PowerFLEX Short-Leaded
(Pb-Free)
2000 Tape & Reel
NCP1442T
7 Lead TO-220 (Straight Lead)
50 Units/Rail
NCP1443FR4
7 Lead PowerFLEX Short-Leaded
2000 Tape & Reel
NCP1443FR4G
0
C < T
A
< 85
C
7 Lead PowerFLEX Short-Leaded
(Pb-Free)
2000 Tape & Reel
NCP1443T
7 Lead TO-220 (Straight Lead)
50 Units/Rail
NCP1444FR4
7 Lead PowerFLEX Short-Leaded
2000 Tape & Reel
NCP1444T
7 Lead TO-220 (Straight Lead)
50 Units/Rail
NCP1445FR4
7 Lead PowerFLEX Short-Leaded
2000 Tape & Reel
NCP1445T
7 Lead TO-220 (Straight Lead)
50 Units/Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1442, NCP1443, NCP1444, NCP1445
http://onsemi.com
19
PACKAGE DIMENSIONS
PowerFLEX
7-PIN
F SUFFIX
CASE 936J-01
ISSUE O
3
6
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAX.
A
J
L
C
D
7 PL
G
0.076 (0.003)
7 PL
B
M
N
P
DIM
A
MIN
MAX
MIN
MAX
MILLIMETERS
0.350
0.360
8.89
9.14
INCHES
B
0.350
0.360
8.89
9.14
C
0.070
0.080
1.78
2.03
D
0.026
0.030
0.66
0.76
E
0.005
0.015
0.13
0.38
F
0.031
0.041
0.79
1.04
G
0.050 BSC
1.270 BSC
H
0.008
0.012
0.199
0.301
J
0.410
0.420
10.41
10.67
K
0.365 00.375
9.27
9.53
L
0.040 REF
1.02 REF
M
0.367
9.16
9.31
N
0.310
0.320
7.87
8.13
P
0.394
0.400
10.00
10.16
R
0.002
---
0.05
---
S
0.070
0.080
1.78
2.03
U
0.001
0.005
0.03
0.13
V
W
0.296 REF
7.52 REF
Y
0.075 REF
1.91 REF
AA
0.071 REF
1.81 REF
AB
0.140 REF
3.56 REF
AC
0.220 REF
5.58 REF
AD
0.281 REF
7.14 REF
AE
12
AF
3
6
AE
DETAIL AG
-T-
SEATING
PLANE
S
K
Y
AD
W
AA
AC
AB
THERMAL
DIE PAD
AF
DETAIL AG
U
F
H
E
R
(TOP OFFSET)
R 0.20 (0.008)
R 0.25 (0.010)
V
12
12
12
0.361
PACKAGE THERMAL DATA
Parameter
PowerFLEX 7-PIN
Unit
R
q
JC
Typical
1.0-4.0
C/W
R
q
JA
Typical
10-50*
C/W
*Depending on thermal properties of substrate. R
q
JA =
R
q
JC
+
R
q
CA.
NCP1442, NCP1443, NCP1444, NCP1445
http://onsemi.com
20
PACKAGE DIMENSIONS
7 LEAD TO-220
T SUFFIX
CASE 821P-03
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. 821P-01 AND -02 OBSOLETE. NEW
STANDARD IS 821P-03.
A
F
Q
D
B
C
N
U
E
J
H
7 PL
G
6 PL
M
K
L
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.91
10.54
0.390
0.415
B
8.23
9.40
0.324
0.370
C
4.19
4.83
0.165
0.190
D
0.66
0.81
0.026
0.032
E
0.89
1.40
0.035
0.055
F
7.62 TYP
0.3 TYP
G
1.22
1.32
0.052
H
2.16
2.92
0.085
0.115
J
0.30
0.64
0.012
0.025
K
24.00
26.54
0.945
1.045
L
26.67
29.03
1.050
1.143
M
6.10
6.48
0.240
0.255
N
7
---
7
---
Q
3.53
3.96
0.139
0.156
U
4
6
4
6
0.048
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
NCP1442/D
PowerFLEX is a trademark of Texas Instruments Incorporated.
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082-1312 USA
Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada
Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
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For additional information, please contact your
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