Semiconductor Components Industries, LLC, 2006
August, 2006 - Rev. 0
1
Publication Order Number:
NCP1523/D
NCP1523
3 MHz, 600 mA,
High-Efficiency, Adjustable
Output Voltage Stepdown
Converter
The NCP1523 stepdown PWM DC-DC converter is optimized for
portable applications powered from 1-cell Li-ion or 3-cell
Alkaline/NiCd/NiMH batteries. The device is available in an
adjustable output voltage from 0.9 V to 2.3 V. It uses synchronous
rectification to increase efficiency and reduce external part count. The
device also has a built-in 3 MHz (nominal) oscillator which reduces
component size by allowing a small inductor and capacitors.
Automatic switching PWM/PFM mode offers improved system
efficiency.
Finally, it includes an integrated soft-start, cycle-by-cycle current
limiting, and thermal shutdown protection. The NCP1523 is available
in a space saving, 8 pin chip scale package.
Features
Up to 93% Efficiency
Sources up to 600 mA
3 MHz Switching Frequency
Adjustable Output Voltage from 0.9 V to 2.3 V
60
mA Quiescent Current
Synchronous Rectification for Higher Efficiency.
2.7 V to 5.5 V Input Voltage Range
Thermal Limit Protection
Shutdown Current Consumption of 0.3
mA
This is a Pb-Free Device*
Typical Applications
Cellular Phones, Smart Phones and PDAs
Digital Still Cameras
MP3 Players and Portable Audio Systems
Wireless and DSL Modems
Portable Equipment
Figure 1. NCP1523 Typical Applications
A2
C1
A1
B2
B1
D1
C2
D2
V
OUT
C
OUT
R1
R2
C
IN
V
IN
V
IN
GND
GND
EN
ADJ
SW
V
OUT
FB
OFF ON
L
Device
Package
Shipping
ORDERING INFORMATION
NCP1523FCT2G FLIP-CHIP-8
(Pb-Free)
3000 /
Tape * Reel
FLIP-CHIP-8
CASE 766AE
MARKING
DIAGRAM
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb-Free Package
http://onsemi.com
A1
NCP1523G
AYWW
A1
*For additional information on our Pb-Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
A1
B1
C1
D1
A2
B2
C3
D2
PIN: A1 - GND
A2 - V
IN
B1 - SW
B2 - EN
C1 - GND
C2 - ADJ
D1 - V
OUT
D2 - FB
Top View
(Bumps Below)
NCP1523
http://onsemi.com
2
EFFICIENCY
(%)
Figure 2. Efficiency vs. Output Current
(V
OUT
= 2.0 V, Temperature = 25C)
30
40
50
60
70
80
90
100
1
10
100
1000
V
IN
= 2.7 V
V
IN
= 4.2 V
V
IN
= 3.6 V
I
OUT
, OUTPUT CURRENT (mA)
TYPICAL APPLICATIONS
Figure 3. Simplified Block Diagram
A2
C1
A1
B2
B1
D1
C2
D2
V
IN
GND
GND
EN
ADJ
SW
V
OUT
FB
Logic Control &
Thermal Shutdown
Reference Voltage
Comp
I
LIMIT
PWM/PFM
Control
Q2
Q1
R1
R2
4.7 mF
2.2 mH
Enable
V
BATTERY
4.7 mF
NCP1523
http://onsemi.com
3
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
Description
A1
GND
Power Ground
Ground connection for the NFET Power Stage and the analog sections.
B2
V
IN
Power Input
Power Supply Input for the PFET Power stage and the Analog Sections of the IC.
B1
S
W
Analog Output
Connection from Power MOSFETs to the Inductor.
B2
EN
Digital Input
Enable for Switching Regulator. This pin is active high. This pin contains an internal
pulldown resistor.
C1
GND
Power Ground
Ground connection for the NFET Power Stage and the analog sections.
C2
ADJ
Analog Input
This pin is the compensation input. R1 is connected to this pin.
D1
V
OUT
Analog Input
This pin is connected of the converter's output. This is the sense of the output voltage.
D2
F
B
Analog Input
Feedback voltage from the output of the power supply. This is the input to the error
amplifier.
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Minimum Voltage All Pins
V
MIN
-0.3
V
Maximum Voltage All Pins (Note 1)
V
MAX
7
V
Maximum Voltage Enable, FB, SW
V
MAX
V
IN
+ 0.3
V
Thermal Resistance, Junction-to-Air (Note 2)
R
JA
159
C/W
Operating Ambient Temperature Range
T
A
-40 to 85
C
Storage Temperature Range
T
STG
-55 to 150
C
Junction Operating Temperature
T
J
-40 to 125
C
Latchup Current maximum Rating T
A
= 85C (Note 4)
L
U
"100
mA
ESD Withstand Voltage (Note 3)
Human Body Model
Machine Model
V
ESD
2.0
200
kV
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22-A108B
2. For the 8-Pin Chip scale package, the R
JA
is highly dependent of the PCB heatsink area. R
JA
= 159C/W with 50 mm
2
PCB heatsink area.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22-A114
Machine Model (MM) $200 V per JEDEC standard: JESD22-A115
4. Latchup current maximum rating per JEDEC standard: JESD78.
NCP1523
http://onsemi.com
4
ELECTRICAL CHARACTERISTICS
(Typical values are referenced to T
A
= +25C, Minimum and Maximum values are referenced -40C to +85C ambient temperature,
unless otherwise noted, operating conditions V
IN
= 3.6 V, V
OUT
= 1.8 V unless otherwise noted)
Symbol
Rating
Min
Typ
Max
Unit
V
IN
Input Voltage Range
2.7
5.5
V
V
UVLO
Under voltage Lockout (V
IN
Falling)
2.4
V
I
q
Quiescent Current
PFM no load
60
95
mA
I
STB
Standby Current, EN Low
0.3
1.2
mA
F
OSC
Oscillator Frequency
2.400
3
3.600
MHz
I
LIM
Peak Inductor Current
1200
mA
V
REF
Feedback Reference Voltage
0.6
V
V
FBtol
F
B
Pin Tolerance Overtemperature
-3
3
%
DV
FB
Reference Voltage Line Regulation
0.1
%
V
OUT
Output Voltage Accuracy (Note 5)
-3%
V
nom
+3%
V
V
OUT
Minimum Output Voltage
0.9
V
V
OUT
Maximum Output Voltage
2.3
V
DV
OUT
Output Voltage Line Regulation (V
IN
= 2.7 5.5)
I
O
= 100 mA
0.1
%
V
LOA-
DREG
Voltage Load Regulation
(I
O
= 150 mA to 300 mA)
(I
O
= 150 mA to 600 mA)
0.0005
0.001
%/mA
%/mA
Duty Cycle
100
%
R
SWH
P-Channel On-Resistance
300
mW
R
SWL
N-Channel On-Resistance
300
mW
I
LeakH
P-Channel Leakage Current
0.05
mA
I
LeakL
N-Channel Leakage Current
0.01
mA
V
ENH
Enable Pin High
1.2
V
V
ENL
Enable Pin Low
0.4
V
T
START
Soft-Start Time
350
450
ms
5. The overall output voltage tolerance depends upon the accuracy of the external resistor (R1, R2).
NCP1523
http://onsemi.com
5
I
Q
, QUIESCENT CURRENT (
m
A)
TEMPERATURE (C)
Figure 4. Quiescent Current vs. Supply
Voltage
0
10
20
30
40
50
60
70
80
90
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
EN = V
IN
I
OUT
= 0 mA
V
IN
, INPUT VOLTAGE (V)
0
10
20
30
40
50
60
70
80
90
100
-40
10
60
110
I
Q
, QUIESCENT CURRENT (
m
A)
V
IN
= 2.7 V
V
IN
= 5.5 V
Figure 5. Quiescent Current vs. Temperature
SHUTDOWN CURRENT (
m
A)
Figure 6. Shutdown Current vs. Supply
Voltage
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V
IN
, INPUT VOLTAGE (V)
EN = GND
I
OUT
= 0 mA
30
40
50
60
70
80
90
100
1
10
100
1000
EFFICIENCY
(%)
Figure 7. Efficiency vs. Output Current
(V
OUT
= 1.8 V, V
IN
= 3.6 V)
-40C
25C
105C
I
OUT
, OUTPUT CURRENT (mA)
30
40
50
60
70
80
90
100
1
10
100
1000
EFFICIENCY
(%)
-40C
25C
105C
Figure 8. Efficiency vs. Output Current
(V
OUT
= 0.9 V, V
IN
= 3.6 V)
I
OUT
, OUTPUT CURRENT (mA)
30
40
50
60
70
80
90
100
1
10
100
1000
EFFICIENCY
(%)
-40C
25C
105C
Figure 9. Efficiency vs. Output Current
V
OUT
= 2.0 V, V
IN
= 3.6 V)
I
OUT
, OUTPUT CURRENT (mA)
NCP1523
http://onsemi.com
6
FREQUENCY
(MHz)
2.4
2.6
2.8
3.0
3.2
3.4
3.6
2.8
3.3
3.8
4.3
4.8
5.3
I
OUT
= 400 mA
I
OUT
= 600 mA
V
IN
, INPUT VOLTAGE (V)
Figure 10. Frequency vs. Input Voltage
TEMPERATURE (C)
FREQUENCY
(MHz)
2.4
2.6
2.8
3.0
3.2
3.4
3.6
-40
-20
0
20
40
60
80
I
OUT
= 600 mA
I
OUT
= 400 mA
Figure 11. Frequency vs. Temperature
LOAD REGULA
TION (%)
-5.0
-3.0
-1.0
1.0
3.0
5.0
0
100
200
300
400
500
600
V
OUT
= 2.0 V
V
OUT
= 0.9 V
Figure 12. Load Regulation
V
OUT
, OUTPUT VOLTAGE (V)
0
50
100
150
200
250
300
2.7
3.2
3.7
4.2
4.7
5.2
I
OUT
, OUTPUT CURRENT (mA)
V
IN
, INPUT VOLTAGE (V)
Figure 13. PFM/PWM Threshold vs. Input
Voltage
Figure 14. Stepdown Converter PFM Mode
Operation
Figure 15. Stepdown Converter PWM Mode
Operation
NCP1523
http://onsemi.com
7
Figure 16. Load Transient Response in PFM
Operation (10 mA to 100 mA)
Figure 17. Load Transient Response Between
PFM and PWM Operation (100 mA to 200 mA)
Figure 18. Soft-Start Time (V
IN
= 3.6 V)
NCP1523
http://onsemi.com
8
OPERATION DESCRIPTION
Overview
The NCP1523 uses a constant frequency, voltage mode
stepdown architecture. Both the main (P-Channel
MOSFET) and synchronous (N-Channel MOSFET)
switches are internal.
It delivers a constant voltage from either a single Li-Ion
or three cell NiMH/NiCd battery to portable devices such as
cell phones and PDA. The output voltage is sets by external
resistor divider. The NCP1523 sources up to 600 mA
depending on external components chosen.
The NCP1523 works with two mode of operation
PWM/PFM depending on the current required. The device
operates in PWM mode at load currents of approximately
130 mA or higher, having voltage tolerance of
3% with
90% efficiency or better. Lighter load currents cause the
device to automatically switch into PFM mode for reduced
current consumption (I
Q
= 60
mA typ) and a longer battery
life.
Additional features include soft-start, under voltage
protection, current overload protection, and thermal
shutdown protection. As shown in Figure 1, only six
external components are required for implementation. The
part uses an internal reference voltage of 0.6 V. It is
recommended to keep the part in shutdown until the input
voltage is 2.7 V or higher.
PWM Operating Mode
In this mode, the output voltage of the NCP1523 is
regulated by modulating the on-time pulse width of the
main switch Q1 at a fixed frequency of 3 MHz. The
switching of the PMOS Q1 is controlled by a flip-flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
PWM ramp. At the beginning of each cycle, the main switch
Q1 is turned ON by the rising edge of the internal oscillator
clock. The inductor current ramps up until the sum of the
current sense signal and compensation ramp becomes higher
than the error voltage amplifier. Once this has occurred, the
PWM comparator resets the flip-flop, Q1 is turned OFF and
the synchronous switch Q2 is turned ON. Q2 replaces the
external Schottky diode to reduce the conduction loss and
improve the efficiency. To avoid overall power loss, a
certain amount of dead time is introduced to ensure Q1 is
completely turned OFF before Q2 is being turned ON.
PFM Operating Mode
Under light load conditions, The NCP1523 enters in low
current PFM mode operation to reduce power consumption.
The output regulation is implemented by pulse frequency
modulation. If the output voltage drops below the threshold
of PM comparator (typically V
nom
- 2%), a new cycle will
be initiated by the PM comparator to turn on the switch Q1.
Q1 remains ON until the peak inductor current reaches
200 mA (nom). Then I
LIM
comparator goes high to switch
off Q1. After a short dead time delay, switch rectifier Q2 is
turn ON. The Negative current detector (NCD) will detect
when the inductor current drops below zero and send the
signal to turn off Q2. The output voltage continues to
decrease through discharging the output capacitor. When the
output voltage falls below the threshold of the PFM
comparator, a new cycle starts immediately.
Cycle-by-Cycle Current Limitation
From the block diagram (Figure 3), an I
LIM
comparator is
used to realize cycle-by-cycle current limit protection. The
comparator compares the SW pin voltage with the reference
voltage, which is biased by a constant current. If the inductor
current reaches the limit, the I
LIM
comparator detects the
SW voltage falling below the reference voltage and releases
the signal to turn off the switch Q1. The cycle-by-cycle
current limit is set at 1200 mA (nom).
Soft-Start
The NCP1523 uses soft-start to limit the inrush current
when the device is initially powered up or enabled.
Soft-start is implemented by gradually increasing the
reference voltage until it reaches the full reference voltage.
During startup, a pulsed current source charges the internal
soft-start capacitor to provide gradually increasing
reference voltage. When the voltage across the capacitor
ramps up to the nominal reference voltage, the pulsed
current source will be switched off and the reference voltage
will switch to the regular reference voltage.
Shutdown Mode
When the EN pin has a voltage applied of less than 0.4 V,
the NCP1523 will be disabled. In shutdown mode, the
internal reference, oscillator and most of the control
circuitries are turned off. Therefore, the typical current
consumption will be 0.3
mA (typical value). Applying a
voltage above 1.2 V to EN pin will enable the device for
normal operation. The device will go through soft-start to
normal operation. EN pin should be activated after the input
voltage is applied.
Thermal Shutdown
circuitry is provided to protect the integrated circuit in the
event that the maximum junction Temperature is exceeded.
If the junction temperature exceeds 160
C, the device shuts
down. In this mode switch Q1 and Q2 and the control circuits
are all turned off. The device restarts in soft start after the
temperature drops below 135
C. This feature is provided to
prevent catastrophic failures from accidental device
overheating and it is not intended as a substitute for proper
heatsinking.
NCP1523
http://onsemi.com
9
APPLICATION INFORMATION
Output Voltage Selection
The output voltage is programmed through an external
resistor divider connected from ADJ to FB then to GND. For
low power consumption and noise immunity, the resistor
from FB to GND (R2) should be in the [100 k
W - 600 kW]
range. If R2 is 200 k
W given the V
FB
is 0.6 V, the current
through the divider will be 3
mA.
The formula below gives the value of V
OUT
, given the
desired R1 and the R1 value,
VOUT + VFB 1 )
R1
R2
(eq. 1)
V
OUT
: output voltage (volts)
V
FB
: feedback voltage = 0.6 V
R1: feedback resistor from V
OUT
to FB
R2: feedback resistor from FB to GND
Input Capacitor Selection
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the input
supply source, thereby reducing switching noise
significantly. The capacitance needed for the input bypass
capacitor depends on the source impedance of the input
supply.
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is I
O
, max/2.
For NCP1523, a low profile ceramic capacitor of 4.7
mF
should be used for most of the cases. For effective bypass
results, the input capacitor should be placed as close as
possible to the V
IN
Pin.
Table 1. LIST OF INPUT CAPACITOR
Murata
GRM188R60J475KE
GRM21BR71C475KA
Taiyo Yuden
JMK212BY475MG
TDK
C2012X5ROJ475KB
C1632X5ROJ475KT
Output L-C Filter Design Considerations:
The NCP1523 is built in 3 MHz frequency and uses
voltage mode architecture. The correct selection of the
output filter ensures good stability and fast transient
response.
Due to the nature of the buck converter, the output
L-C filter must be selected to work with internal
compensation. For NCP1523, the internal compensation is
internally fixed and it is optimized for an output filter of L
= 2.2
mH and C
OUT
= 4.7
mF
The corner frequency is given by:
fc +
1
2p L Cout
+
1
2p 2.2 mH 4.7 mF
+ 49.5 kHz
(eq. 2)
The device operates with inductance value between 1
mH
and maximum of 4.7
mH.
If the corner frequency is moved, it is recommended to
check the loop stability depending of the output ripple
voltage accepted and output current required. For lower
frequency, the stability will be increase; a larger output
capacitor value could be chosen without critical effect on the
system. On the other hand, a smaller capacitor value
increases the corner frequency and it should be critical for
the system stability. Take care to check the loop stability.
The phase margin is usually higher than 45
.
Table 2. L-C FILTER EXAMPLE
Inductance (L)
Output Capacitor (C
OUT
)
1 mH
10 mF
2.2 mH
4.7 mF
4.7 mH
2.2 mF
Inductor Selection
The inductor parameters directly related to device
performances are saturation current and DC resistance and
inductance value. The inductor ripple current (
D
IL
)
decreases with higher inductance:
DIL +
VOUT
L fSW
1 *
VOUT
VIN
(eq. 3)
D
IL
peak to peak inductor ripple current
L inductor value
f
SW
Switching frequency
The Saturation current of the inductor should be rated
higher than the maximum load current plus half the ripple
current:
IL(MAX) + IO(MAX) )
DIL
2
(eq. 4)
I
L(MAX)
Maximum Inductor Current
I
O(MAX)
Maximum Output Current
The inductor's resistance will factor into the overall
efficiency of the converter. For best performances, the DC
resistance should be less than 0.3
W for good efficiency.
Table 3. LIST OF INDUCTOR
FDK
MIPW3226 Series
TDK
VLF3010AT Series
Taiyo Yuden
LQ CBL2012
Coil Craft
DO1605-T Series
LPO3010
NCP1523
http://onsemi.com
10
Output Capacitor Selection
Selecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with low
ESR values will have the lowest output ripple voltage and
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric.
The output ripple voltage in PWM mode is given by:
DVOUT + DIL
1
4 fSW COUT
) ESR
(eq. 5)
In PFM mode (at light load), the output voltage is
regulated by pulse frequency modulation. The output
voltage ripple is independent of the output capacitor value.
It is set by the threshold of PM comparator.
Table 4. LIST OF OUTPUT CAPACITOR ROHS
Murata
GRM188R60J475KE
4.7 mF
GRM21BR71C475KA
GRM188R60OJ106ME
10 mF
Taiyo Yuden
JMK212BY475MG
4.7 mF
JMK212BJ106MG
10 mF
TDK
C2012X5ROJ475KB
4.7 mF
C1632X5ROJ475KT
C2012X5ROJ106K
10 mF
APPLICATION BOARD
PCB Layout Recommendations
Good PCB layout plays an important role in switching
mode power conversion. Careful PCB layout can help to
minimize ground bounce, EMI noise and unwanted
feedback that can affect the performance of the converter.
Hints suggested below can be used as a guideline in most
situations.
1. Use star-ground connection to connect the IC
ground nodes and capacitor GND nodes together
at one point. Keep them as close as possible, and
then connect this to the ground plane through
several vias. This will reduce noise in the ground
plane by preventing the switching currents from
flowing through the ground plane.
2. Place the power components (i.e., input capacitor,
inductor and output capacitor) as close together as
possible for best performance. All connecting
traces must be short, direct, and wide to reduce
voltage errors caused by resistive losses through
the traces.
3. Separate the feedback path of the output voltage
from the power path. Keep this path close to the
NCP1523 circuit. And also route it away from
noisy components. This will prevent noise from
coupling into the voltage feedback trace.
4. Place the DC-DC converter away from noise
sensitive circuitry, such as RF circuits.
The following shows the NCP1523 demo board
schematic and layout and bill of materials:
Figure 19. NCP1523 Board Schematic
A2
B2
C2
D2
A1
D1
C1
D1
NCP1523
U2
R1
R2
C2
V
BATTERY
V
IN
EN
ADJ
FB
GND1
GND
SW
V
OUT
OFF ON
L1
C1
NCP1523
http://onsemi.com
11
Figure 20. NCP1523 Board Layout
Figure 21. NCP1523 Board Schematic
A2
B2
C2
D2
A1
D1
C1
D1
NCP1523
U1
R1
220k
R2
220k
C2
4.7 mF
V
IN
EN
ADJ
FB
GND
GND
SW
V
OUT
L1
C1
4.7 mF
FB
V
IN
EN
ADJ
V
OUT
B2
V
OUT
SW
TP3
V
OUT
1
2
V
IN
TP1
V
IN
B1
V
IN
1
2
V
IN
TP2
EN
J1
S1
G1
EN
3
JMP1
JMP
JMP2
JMP
1
2
1
2
2.2 mH
EN
NCP1523
http://onsemi.com
12
Figure 22. NCP1523 Assembly Layer
Figure 23. NCP1523 Top Layer Routing
NCP1523
http://onsemi.com
13
Figure 24. NCP1523 Bottom Layer Routing
BILL OF MATERIALS
Designator
Qty
Description
Value
Tolerance
Footprint
Manufacturer
Manufacturer
Part Number
U1
1
IC, Converter,
DC/DC
NA
NA
8-Pin Flip
Chip
ON Semiconductor
NCP1523
C1, C2
2
Ceramic
Capacitor
4.7 mF, 10 V,
X5R
0,1
0805
Murata
GRM219R61A475
KE19D
R1, R2
2
SMD resistor
220k
0.05
0805
Standard
Standard
L1
1
Inductor
2.2 mH
0.2
1605
Coilcraft
DO1605T-222MLB
B1, B2
2
Male
SL5.08/2/90B +
Female
BLZ5.08/2/90B
Connector I/O
NA
NA
NA
Weidmuller
1510360000
+
1555060000
J1
1
3 Pin Jumper
Header
NA
NA
2.54 mm
TYCO/AMP
5-826629-0
JMP1, JMP2
2
Jumper for GND
NA
NA
10.16 mm
Harwin
D3082-01
TP1, TP2,
TP3
3
Test point
NA
NA
NA
Standard
Standard
G1
0*
SMB Connector
NA
NA
NA
Radiall
R114665000
PCB
1
88.9 x 61.1 x
1.6 mm
4 Layers
NA
NA
NA
Any
TLS-P-001-A-050
6-DA
NCP1523
http://onsemi.com
14
PACKAGE DIMENSIONS
FLIP-CHIP-8
CASE 766AE-01
ISSUE A
SEATING
PLANE
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
2X
DIM
A
MIN
MAX
---
MILLIMETERS
A1
A2
0.335
0.385
D
2.050 BSC
E
b
0.290
0.340
e
0.500 BSC
D1
1.500 BSC
0.655
E
D
A B
TERMINAL A1
LOCATOR
e
D1
A
0.05
B
C
0.03 C
0.05 C
8X
b
A B
2
1
0.10 C
A
A1
A2
C
0.210
0.270
1.050 BSC
e
C
BOTTOM VIEW
SIDE VIEW
TOP VIEW
0.10 C
2X
8X
D
e/2
NOTE 3
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5773-3850
NCP1523/D
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
PDF 
ZIP