Semiconductor Components Industries, LLC, 2002
February, 2002 Rev. 4
1
Publication Order Number
NCP1570/D
NCP1570
Low Voltage Synchronous
Buck Controller
The NCP1570 is a low voltage buck controller. It provides the
control for a DCDC power solution producing an output voltage as
low as 0.985 V over a wide current range. The NCP1570based
solution is powered from 12 V with the output derived from a 5 V
supply. It contains all required circuitry for a synchronous NFET buck
regulator using the V
2
TM
control method to achieve the fastest possible
transient response and best overall regulation. The NCP1570 operates
at a fixed internal 200 kHz frequency and is packaged in an SO8.
The NCP1570 provides undervoltage lockout protection, Soft Start,
Power Good with delay, and builtin adaptive nonoverlap.
Features
0.985 V
1.0% Reference
V
2
Control Topology
200 ns Transient Response
Programmable Soft Start
Power Good
Programmable Power Good Delay
40 ns Gate Rise and Fall Times (3.3 nF Load)
50 ns Adaptive FET NonOverlap Time
Fixed 200 kHz Oscillator Frequency
Undervoltage Lockout
On/Off Control Through Use of the COMP Pin
Overvoltage Protection through Synchronous MOSFETs
Synchronous NChannel Buck Design
Dual Supply, 12 V Control, 5 V Power Source
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Device
Package
Shipping
ORDERING INFORMATION
NCP1570D
SO8
98 Units/Rail
NCP1570DR2
SO8
2500 Tape & Reel
SO8
D SUFFIX
CASE 751
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
GATE(H)
COMP
1
1570
AL
YW
8
GATE(L)
PGDELAY
V
FB
PWRGD
GND
V
CC
PIN CONNECTIONS AND
MARKING DIAGRAM
1
8
NCP1570
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2
Figure 1. Applications Circuit
GND
V
FB
GATE(L)
GATE(H)
V
CC
PWRGD
PGDELAY
COMP
NCP1570
C13
0.1
F
C12
0.01
F
R1
50 k
12 V
V
LOGIC
5.0 V
NTD4302
NTD4302
1.2
H
10 k
+
+
33
F/8.0 V/1.6 Arms
4
56
F/4.0 V/1.6 Arms
SPCAP 40 m
GND
Q1
Q2
+
+
C3
C2
C1
+
+
+
GND
1.2 V
C8
C9
C10
C11
1.2 V/10 A
2.0 k
R3
R5
L1
100 pF
C6
C4
0.1
F
PWRGD
MAXIMUM RATINGS*
Rating
Value
Unit
Operating Junction Temperature
150
C
Storage Temperature Range
65 to 150
C
ESD Susceptibility (Human Body Model)
2.0
kV
ESD Susceptibility (Machine Model)
200
V
Lead Temperature Soldering:
Reflow: (Note 1)
230 peak
C
Moisture Sensitivity Level
2
Package Thermal Resistance, SO8
JunctiontoCase, R
JC
JunctiontoAmbient, R
JA
48
165
C/W
C/W
1. 60 second maximum above 183
C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Name
Pin Symbol
V
MAX
V
MIN
I
SOURCE
I
SINK
IC Power Input
V
CC
15 V
0.5 V
N/A
1.5 A Peak
450 mA DC
Compensation Capacitor
COMP
6.0 V
0.5 V
10 mA
10 mA
Voltage Feedback Input
V
FB
6.0 V
0.5 V
1.0 mA
1.0 mA
Power Good Output
PWRGD
15 V
0.5 V
1.0 mA
20 mA
Power Good Delay
PGDELAY
6.0 V
0.5 V
1.0 mA
10 mA
HighSide FET Driver
GATE(H)
15 V
0.5 V
2.0 V for 50 ns
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
LowSide FET Driver
GATE(L)
15 V
0.5 V
2.0 V for 50 ns
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
Ground
GND
0.5 V
0.5 V
1.5 A Peak
450 mA DC
N/A
NCP1570
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3
ELECTRICAL CHARACTERISTICS
(0
C < T
J
< 125
C, 11.4 V < V
CC
< 12.6 V, C
GATE(H)
= C
GATE(L)
= 3.3 nF,
C
PGDELAY
= 0.01
F, C
COMP
= 0.1
F; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
V
FB
Bias Current
V
FB
= 0 V
0.2
2.0
A
COMP Source Current
COMP = 1.5 V, V
FB
= 0.8 V
15
30
60
A
COMP Sink Current
COMP = 1.5 V, V
FB
= 1.2 V
15
30
60
A
Reference Voltage
COMP = V
FB
0.975
0.985
0.995
V
COMP Max Voltage
V
FB
= 0.8 V
2.4
2.7
V
COMP Min Voltage
V
FB
= 1.2 V
0.1
0.2
V
COMP Fault Discharge Current at
UVLO
COMP = 1.2 V, V
CC
= 6.9 V
0.5
1.7
mA
COMP Fault Discharge Threshold to
Reset UVLO
COMP = 0.5 V, V
CC
= 12 V 6.9 V 12 V.
Ramp COMP to 0.1 V. Monitor I (COMP)
0.1
0.25
0.3
V
Open Loop Gain
98
dB
Unity Gain Bandwidth
20
kHz
PSRR @ 1.0 kHz
70
dB
Output Transconductance
32
mmho
Output Impedance
2.5
M
GATE(H) and GATE(L)
Rise Time
1.0 V < GATE(L) & GATE(H) < V
CC
2.0 V
40
80
ns
Fall Time
V
CC
2.0 V < GATE(L) & GATE(H) < 1.0 V
40
80
ns
GATE(H) to GATE(L) Delay
GATE(H) < 2.0 V, GATE(L) > 2.0 V
25
50
75
ns
GATE(L) to GATE(H) Delay
GATE(L) < 2.0 V, GATE(H) > 2.0 V
25
50
75
ns
Minimum Pulse Width
GATE(X) = 4.0 V
250
ns
High Voltage (AC)
Measure GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF
Note 2
V
CC
0.5
V
CC
V
Low Voltage (AC)
Measure GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF
Note 2
0
0.5
V
GATE(H)/(L) PullDown
Resistance to GND. Note 2
20
50
115
k
Power Good
Lower Threshold, V
O
Rising
0.856
0.887
0.917
V
Lower Threshold, V
O
Falling
0.666
0.690
0.713
V
PWRGD Low Voltage
I
SINK
= 1.0 mA, V
FB
= 0 V
0.15
0.4
V
Delay Charge Current
PGDELAY = 2.0 V
7.0
12
18
A
Delay Clamp Voltage
3.45
4.0
4.3
V
Delay Charge Threshold
Ramp PGDELAY, Monitor PWRGD
3.1
3.3
3.5
V
Delay Discharge Current at UVLO
PGDELAY = 0.5 V, V
CC
= 6.9 V
0.5
2.0
mA
Delay Discharge Threshold to Reset
UVLO
PGDELAY = 0.5 V, V
CC
= 12 V to 6.9 V to
12 V, Ramp PGDELAY to 0.1 V, Monitor I
(PGDELAY)
0.1
0.25
0.3
V
"Good" Signal Delay
With 0.01
F. Note 2
1.0
3.0
5.0
ms
2. Guaranteed by design. Not tested in production.
NCP1570
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ELECTRICAL CHARACTERISTICS (continued)
(0
C < T
J
< 125
C, 11.4 V < V
CC
< 12.6 V, C
GATE(H)
= C
GATE(L)
= 3.3 nF,
C
PGDELAY
= 0.01
F, C
COMP
= 0.1
F; unless otherwise specified.)
Characteristic
Unit
Max
Typ
Min
Test Conditions
PWM Comparator
PWM Comparator Offset
V
FB
= 0 V, Increase COMP Until GATE(H)
Starts Switching
0.475
0.525
0.575
V
Ramp Max Duty Cycle
80
%
Artificial Ramp
Duty Cycle = 50%
18
25
35
mV
Transient Response
COMP = 1.5 V, V
FB
20 mV Overdrive.
Note 3
200
300
ns
V
FB
Input Range
Note 3
0
1.4
V
Oscillator
Switching Frequency
150
200
250
kHz
General Electrical Specifications
V
CC
Supply Current
COMP = 0 V (No Switching)
10
15
mA
Start Threshold
GATE(H) Switching, COMP Charging
8.0
8.5
9.0
V
Stop Threshold
GATE(H) Not Switching, COMP Discharging
7.0
7.5
8.0
V
Hysteresis
Start Stop
0.75
1.0
1.25
V
3. Guaranteed by design. Not tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO8
PIN SYMBOL
FUNCTION
1
V
CC
Power supply input.
2
PWRGD
Open collector output goes low when V
FB
is out of regulation. User
must externally limit current into this pin to less than 20 mA.
3
PGDELAY
External capacitor programs PWRGD lowtohigh transition delay.
4
COMP
Error amp output. PWM comparator reference input. A capacitor to
LGND provides error amp compensation and Soft Start. Pulling pin
< 0.45 locks gate outputs to a zero percent duty cycle state.
5
GATE(H)
Highside switch FET driver pin. Capable of delivering peak currents
of 1.5 A.
6
GATE(L)
Lowside synchronous FET driver pin. Capable of delivering peak
currents of 1.5 A.
7
V
FB
Error amplifier and PWM comparator input.
8
GND
Power supply return.
NCP1570
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Figure 2. Block Diagram
+
UVLO COMP
+
+
+
Fault Latch
Set Dominant
+
0.25 V
Error Amp
R
S
Q
PWM Latch
Reset Dominant
PWM COMP
+
OSC
Art Ramp
80%, 200 kHz
0.525 V
+
8.5 V/7.5 V
+
0.985 V
S
R
Q
V
CC
GND
V
FB
COMP
GATE(H)
GATE(L)
PGDELAY
PWRGD
Non
Overlap
V
CC
+
0.89 V/0.69 V
+
+
0.25 V
S
R
Q
PGDELAY Latch
Set Dominant
+
+
3.3 V
12
A
+
NCP1570
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Supply Current vs. Temperature
Figure 4. Oscillator Frequency vs. Temperature
Figure 5. Reference Voltage vs. Temperature
Figure 6. Artificial Ramp Amplitude vs. Temperature
(50% Duty Cycle)
Figure 7. PWM Offset Voltage vs. Temperature
Figure 8. Undervoltage Lockout Thresholds vs.
Temperature
0
I
CC
(mA)
6
Temperature (
C)
7
8
9
10
11
20
40
60
80
100
120
0
Oscillator Frequency (kHz)
198
Temperature (
C)
199
200
201
202
203
204
205
20
40
60
80
120
100
0
V
REF
(mV)
982
Temperature (
C)
984
986
988
20
40
60
80
100
120
0
Ramp Amplitude (mV)
22
Temperature (
C)
23
24
25
26
20
40
60
80
100
120
0
PWM Of
fset V
oltage (mV)
504
Temperature (
C)
508
512
516
520
20
40
60
80
100
120
0
Start/Stop Threshold V
oltages (V)
7.0
Temperature (
C)
7.2
7.4
7.6
7.8
8.0
8.2
8.4
20
40
60
80
120
100
TurnOn
Threshold
TurnOff
Threshold
NCP1570
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. V
FB
Bias Current vs. Temperature
Figure 10. Error Amp Output Currents vs. Temperature
Figure 11. COMP Voltages vs. Temperature
Figure 12. COMP Fault Mode Discharge Current vs.
Temperature
Figure 13. GATE Output Rise and Fall Times vs.
Temperature
Figure 14. GATE NonOverlap Times vs. Temperature
0
V
FB
Bias Current (
A)
0.20
Temperature (
C)
0.25
0.30
0.35
0.40
0.45
0.50
0.55
20
40
60
80
120
100
0
COMP Minimum V
oltage (mV)
0
Temperature (
C)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
20
40
60
80
120
100
0
Error Amp Source/Sink Currents (
A)
28
Temperature (
C)
29
30
31
33
34
20
40
60
80
100
120
32
0
Discharge Current (mA)
1.10
Temperature (
C)
1.14
1.18
1.22
1.30
1.34
20
40
60
80
100
120
1.26
0
GA
TE Rise/Fall T
imes (ns)
20
Temperature (
C)
22
24
26
32
34
36
38
20
40
60
80
120
100
30
28
0
Gate NonOverlap T
ime (ns)
30
Temperature (
C)
35
40
45
50
55
20
40
60
80
100
120
Source
Current
Sink
Current
COMP Maximum
Voltage
COMP Fault
Threshold Voltage
COMP Minimum
Voltage
GATEL Fall Time
GATEH Fall Time
GATEH Rise Time
GATEL Rise Time
GATEH to GATEL
Delay Time
GATEL to GATEH
Delay Time
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TYPICAL PERFORMANCE CHARACTERISTICS
Figure 15. Power Good Thresholds vs. Temperature
Figure 16. PGOOD Output Low Voltage vs.
Temperature
Figure 17. PGOOD Delay Charge Current vs.
Temperature
Figure 18. PGDELAY Discharge Current vs.
Temperature
Figure 19. Power Good Discharge Threshold Voltage
vs. Temperature
Figure 20. PGDELAY Voltages vs. Temperature
0
Power Good Threshold V
oltage (mV)
600
Temperature (
C)
700
800
900
1000
20
40
60
80
100
120
0
PGOOD Low V
oltage (mV)
40
Temperature (
C)
45
50
55
65
70
20
40
60
80
100
120
60
0
GOOD
Delay
Charge
Current
(
A)
11.3
Temperature (
C)
11.4
11.5
11.6
11.8
11.9
20
40
60
80
100
120
11.7
0
Discharge Current (mA)
1.35
Temperature (
C)
1.40
1.45
1.50
1.60
1.65
20
40
60
80
100
120
1.55
0
Discharge Threshold V
oltage (mV)
259
Temperature (
C)
260
261
262
263
20
40
60
80
100
120
0
PGDELA
Y V
oltages (V)
3.20
Temperature (
C)
3.30
3.40
3.50
3.70
3.80
3.90
4.00
20
40
60
80
120
100
3.60
TurnOn Threshold,
V
FB
Rising
TurnOff Threshold,
V
FB
Falling
PGDELAY
Max Voltage
PGDELAY Upper
Threshold Voltage
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APPLICATION INFORMATION
THEORY OF OPERATION
The NCP1570 is a simple, synchronous, fixedfrequency,
lowvoltage buck controller using the V
2
control method. It
provides a programmabledelay Power Good function to
indicate when the output voltage is out of regulation.
V
2
Control Method
The V
2
control method uses a ramp signal generated by
the ESR of the output capacitors. This ramp is proportional
to the AC current through the main inductor and is offset by
the DC output voltage. This control scheme inherently
compensates for variation in either line or load conditions,
since the ramp signal is generated from the output voltage
itself. The V
2
method differs from traditional techniques
such as voltage mode control, which generates an artificial
ramp, and current mode control, which generates a ramp
using the inductor current.
Figure 21. V
2
Control with Slope Compensation
COMP
Reference
Voltage
+
+
PWM
RAMP
Error
Amplifier
Error
Signal
Output
Voltage
V
FB
GATE(H)
GATE(L)
Slope
Compensation
The V
2
control method is illustrated in Figure 21. The
output voltage generates both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it
is affected by any change in the output, regardless of the
origin of that change. The ramp signal also contains the DC
portion of the output voltage, allowing the control circuit to
drive the main switch to 0% or 100% duty cycle as required.
A variation in line voltage changes the current ramp in the
inductor, which causes the V
2
control scheme to compensate
the duty cycle. Since any variation in inductor current
modifies the ramp signal, as in current mode control, the V
2
control scheme offers the same advantages in line transient
response.
A variation in load current will affect the output voltage,
modifying the ramp signal. A load step immediately changes
the state of the comparator output, which controls the main
switch. The comparator response time and the transition
speed of the main switch determine the load transient
response. Unlike traditional control methods, the reaction
time to the output load step is not related to the crossover
frequency of the error signal loop.
The error signal loop can have a low crossover frequency,
since the transient response is handled by the ramp signal
loop. The main purpose of this `slow' feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be rolled
off at a low frequency. Enhanced noise immunity improves
remote sensing of the output voltage, since the noise
associated with long feedback traces can be effectively
filtered.
Line and load regulation are drastically improved because
there are two independent control loops. A voltage mode
controller relies on the change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains a fixed error signal during
line transients, since the slope of the ramp signal changes in
this case. However, regulation of load transients still requires
a change in the error signal. The V
2
method of control
maintains a fixed error signal for both line and load variation,
since the ramp signal is affected by both line and load.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope in the output ripple can
lead to pulse width jitter and variation caused by both random
and synchronous noise. A ramp waveform generated in the
oscillator is added to the ramp signal from the output voltage
to provide the proper voltage ramp at the beginning of each
switching cycle. This slope compensation increases the noise
immunity, particularly at duty cycles above 50%.
Start Up
The NCP1570 features a programmable Soft Start
function, which is implemented through the error amplifier
and the external compensation capacitor. This feature
prevents stress to the power components and limits output
voltage overshoot during startup. As power is applied to the
regulator, the NCP1570 undervoltage lockout circuit (UVL)
monitors the IC's supply voltage (V
CC
). The UVL circuit
prevents the MOSFET gates from switching until V
CC
exceeds the 8.5 V threshold. A hysteresis function of 1.0 V
improves noise immunity. The compensation capacitor
connected to the COMP pin is charged by a 30
A current
source. When the capacitor voltage exceeds the 0.5 V offset
of the PWM comparator, the PWM control loop will allow
switching to occur. The upper gate driver GATE(H) is
activated turning on the upper MOSFET. The current then
ramps up through the main inductor and linearly powers the
output capacitors and load. When the regulator output
voltage exceeds the COMP pin voltage minus the 0.5 V
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PWM comparator offset threshold and the artificial ramp,
the PWM comparator terminates the initial pulse.
Figure 22. Idealized Waveforms
8.5 V
0.5 V
V
IN
V
COMP
V
FB
GATE(H)
UVLO
STARTUP
NORMAL OPERATION
t
S
Normal Operation
During normal operation, the duty cycle of the gate drivers
remains approximately constant as the V
2
control loop
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load conditions
will result in changes in duty cycle to maintain regulation.
Gate Charge Effect on Switching Times
When using the onboard gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading.
Transient Response
The 200 ns reaction time of the control loop provides fast
transient response to any variations in input voltage and
output current. Pulsebypulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
Overvoltage Protection
Overvoltage protection is provided as a result of the
normal operation of the V
2
control method and requires no
additional external components. The control loop responds
to an overvoltage condition within 200 ns, turning off the
upper MOSFET and disconnecting the regulator from its
input voltage. This results in a crowbar action to clamp the
output voltage, preventing damage to the load. The regulator
remains in this state until the overvoltage condition ceases.
Power Good
The PWRGD pin is asserted when the output voltage is
within regulation limits. Sensing for the PWRGD pin is
achieved through the V
FB
pin. When the output voltage is
rising, PWRGD goes high at 90% of the designed output
voltage. When the output voltage is falling, PWRGD goes
low at 70% of the designed output voltage. PWRGD is an
opencollector output and should be externally pulled to
logic high through a resistor to limit current to no more than
20mA. Figure 23 shows the hysteretic nature of the PWRGD
pin's operation.
Figure 23. PWRGD Assertion
High
Low
V
OUT
70%
90%
Percent of
Designed V
OUT
PWRGD
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
D
VOUT
+ D
IOUT
ESL
D
t
)
ESR
)
tTR
COUT
where:
I
OUT
/
t = load current slew rate;
I
OUT
= load transient;
t = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
t
TR
= output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula:
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11
ESRMAX
+ D
VESR
D
IOUT
where:
V
ESR
= change in output voltage due to ESR (assigned
by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula:
Number of capacitors
+
ESRCAP
ESRMAX
where:
ESR
CAP
= maximum ESR per capacitor (specified in
manufacturer's data sheet).
ESR
MAX
= maximum allowable ESR.
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
D
VESR
+ D
IOUT
ESRMAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESLMAX
+ D
VESL
D
t
D
I
Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor's limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.
The minimum inductance value for the input inductor is
therefore:
LIN
+
D
V
(dI dt)MAX
where:
L
IN
= input inductor value;
V = voltage seen by the input inductor during a full load
swing;
(dI/dt)
MAX
= maximum allowable input current slew rate.
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a doublepole network
with a slope of 2.0, a rolloff rate of 40 dB/dec, and a
corner frequency:
fC
+
1
2
p
LC
where:
L = input inductor;
C = input capacitor(s).
Selection of the Output Inductor
There are many factors to consider when choosing the
output inductor. Maximum load current, core and winding
losses, ripple current, short circuit current, saturation
characteristics, component height and cost are all variables
that the designer should consider. However, the most
important consideration may be the effect inductor value has
on transient response.
The amount of overshoot or undershoot exhibited during
a current transient is defined as the product of the current
step and the output filter capacitor ESR. Choosing the
inductor value appropriately can minimize the amount of
energy that must be transferred from the inductor to the
capacitor or viceversa. In the subsequent paragraphs, we
will determine the minimum value of inductance required
for our system and consider the tradeoff of ripple current
vs. transient response.
In order to choose the minimum value of inductance, input
voltage, output voltage and output current must be known.
Most computer applications use reasonably well regulated
bulk power supplies so that, while the equations below
specify V
IN(MAX)
or V
IN(MIN)
, it is possible to use the
nominal value of V
IN
in these calculations with little error.
Current in the inductor while operating in the continuous
current mode is defined as the load current plus ripple
current.
IL
+
ILOAD
)
IRIPPLE
The ripple current waveform is triangular, and the current
is a function of voltage across the inductor, switch FET
ontime and the inductor value. FET ontime can be defined
as the product of duty cycle and switch frequency, and duty
cycle can be defined as a ratio of V
OUT
to V
IN
. Thus,
IRIPPLE
+
(VIN
*
VOUT)VOUT
(fOSC)(L)(VIN)
Peak inductor current is defined as the load current plus
half of the peak current. Peak current must be less than the
maximum rated FET switch current, and must also be less
than the inductor saturation current. Thus, the maximum
output current can be defined as:
IOUT(MAX)
+
ISWITCH(MAX)
*
VIN(MAX)
*
VOUT VOUT
2 fOSC L VIN(MAX)
Since the maximum output current must be less than the
maximum switch current, the minimum inductance required
can be determined.
L(MIN)
+
(VIN(MIN)
*
VOUT)VOUT
(fOSC)(ISWITCH(MAX))(VIN(MIN))
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12
This equation identifies the value of inductor that will
provide the full rated switch current as inductor ripple
current, and will usually result in inefficient system
operation. The system will sink current away from the load
during some portion of the duty cycle unless load current is
greater than half of the rated switch current. Some value
larger than the minimum inductance must be used to ensure
the converter does not sink current. Choosing larger values
of inductor will reduce the ripple current, and inductor value
can be designed to accommodate a particular value of ripple
current by replacing I
SWITCH(MAX)
with a desired value of
I
RIPPLE
:
L(RIPPLE)
+
(VIN(MIN)
*
VOUT)VOUT
(fOSC)(IRIPPLE)(VIN(MIN))
However, reducing the ripple current will cause transient
response times to increase. The response times for both
increasing and decreasing current steps are shown below.
TRESPONSE(INCREASING)
+
(L)(
D
IOUT)
(VIN
*
VOUT)
TRESPONSE(DECREASING)
+
(L)(
D
IOUT)
(VOUT)
Inductor value selection also depends on how much output
ripple voltage the system can tolerate. Output ripple voltage
is defined as the product of the output ripple current and the
output filter capacitor ESR.
Thus, output ripple voltage can be calculated as:
VRIPPLE
+
ESRC IRIPPLE
+
ESRC VIN
*
VOUT VOUT
fOSC L VIN
Finally, we should consider power dissipation in the
output inductors. Power dissipation is proportional to the
square of inductor current:
PD
+
(I
2
L
)(ESRL)
The temperature rise of the inductor relative to the air
surrounding it is defined as the product of power dissipation
and thermal resistance to ambient:
D
T(inductor)
+
(Ra)(PD)
Ra for an inductor designed to conduct 20 A to 30 A is
approximately 45
C/W. The inductor temperature is given as:
T(inductor)
+ D
T(inductor)
)
Tambient
V
CC
Bypass Filtering
A small RC filter should be added between module V
CC
and
the V
CC
input to the IC. A 10
resistor and a 0.1
F capacitor
should be sufficient to ensure the controller IC does not operate
erratically due to injected noise.
Input Filter Capacitors
The input filter capacitors provide a charge reservoir that
minimizes supply voltage variations due to changes in current
flowing through the switch FETs. These capacitors must be
chosen primarily for ripple current rating.
Figure 24.
V
IN
V
OUT
I
IN(AVE)
I
RMS(CIN)
C
IN
CONTROL
INPUT
L
IN
L
OUT
C
OUT
Consider the schematic shown in Figure 24. The average
current flowing in the input inductor L
IN
for any given
output current is:
IIN(AVE)
+
IOUT
VOUT
VIN
Input capacitor current is positive into the capacitor when
the switch FETs are off, and negative out of the capacitor
when the switch FETs are on. When the switches are off,
I
IN(AVE)
flows into the capacitor. When the switches are on,
capacitor current is equal to the perphase output current
minus I
IN(AVE)
. If we ignore the small current variation due
to the output ripple current, we can approximate the input
capacitor current waveform as a square wave. We can then
calculate the RMS input capacitor ripple current:
IRMS(CIN)
+
I
2
IN(AVE)
)
VOUT
VIN
IOUT per phase
*
IIN(AVE) 2
*
I
2
IN(AVE)
The input capacitance must be designed to conduct the
worst case input ripple current. This will require several
capacitors in parallel. In addition to the worst case current,
attention must be paid to the capacitor manufacturer's
derating for operation over temperature.
As an example, let us define the input capacitance for a
5 V to 3.3 V conversion at 10 A at an ambient temperature
of 60
C. A droop voltage of 90 mV to 1.61 V and efficiency
of 80% is assumed. Average input current in the input filter
inductor is:
IIN(AVE)
+
(10 A)(3.3 V 5 V)
+
6.6 A
Input capacitor RMS ripple current is then
IIN(RMS)
+
6.62
)
3.3 V
5 V
[(10 A
*
6.6 A)2
*
6.6 A2]
+
4.74 A
If we consider a Rubycon MBZ series capacitor, the ripple
current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at
100 kHz and 105
C. We determine the number of input
capacitors by dividing the ripple current by the
percapacitor current rating:
Number of capacitors
+
4.74 A 2.0 A
+
2.3
A total of at least 3 capacitors in parallel must be used to
meet the input capacitor ripple current requirements.
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Output Switch FETs
Output switch FETs must be chosen carefully, since their
properties vary widely from manufacturer to manufacturer.
The NCP1570 system is designed assuming that nchannel
FETs will be used. The FET characteristics of most concern
are the gate charge/gatesource threshold voltage, gate
capacitance, onresistance, current rating and the thermal
capability of the package.
The onboard FET driver has a limited drive capability. If
the switch FET has a high gate charge, the amount of time
the FET stays in its ohmic region during the turnon and
turnoff transitions is larger than that of a low gate charge
FET, with the result that the high gate charge FET will
consume more power. Similarly, a low onresistance FET
will dissipate less power than will a higher onresistance
FET at a given current. Thus, low gate charge and low
R
DS(ON)
will result in higher efficiency and will reduce
generated heat.
It can be advantageous to use multiple switch FETs to
reduce power consumption. By placing a number of FETs in
parallel, the effective R
DS(ON)
is reduced, thus reducing the
ohmic power loss. However, placing FETs in parallel
increases the gate capacitance so that switching losses
increase. As long as adding another parallel FET reduces the
ohmic power loss more than the switching losses increase,
there is some advantage to doing so. However, at some point
the law of diminishing returns will take hold, and a marginal
increase in efficiency may not be worth the board area
required to add the extra FET. Additionally, as more FETs
are used, the limited drive capability of the FET driver will
have to charge a larger gate capacitance, resulting in
increased gate voltage rise and fall times. This will affect the
amount of time the FET operates in its ohmic region and will
increase power dissipation.
The following equations can be used to calculate power
dissipation in the switch FETs.
For ohmic power losses due to R
DS(ON)
:
PON(TOP)
+
(RDS(ON)(TOP))(IRMS(TOP))2
(number of topside FETs)
PON(BOTTOM)
+
RDS(ON)(BOTTOM) IRMS(BOTTOM) 2
number of bottomside FETs
where:
n = number of phases.
Note that R
DS(ON)
increases with temperature. It is good
practice to use the value of R
DS(ON)
at the FET's maximum
junction temperature in the calculations shown above.
IRMS(TOP)
+
I
2
PK
*
(IPK)(IRIPPLE)
)
D
3
I
2
RIPPLE
IRMS(BOTTOM)
+
I
2
PK
*
(IPKIRIPPLE)
)
(1
*
D)
3
I
2
RIPPLE
IRIPPLE
+
(VIN
*
VOUT)(VOUT)
(fOSC)(L)(VIN)
IPEAK
+
ILOAD
)
IRIPPLE
2
+
IOUT
3
)
IRIPPLE
2
where:
D = Duty cycle.
For switching power losses:
PD
+
nCV2(fOSC)
where:
n = number of switch FETs (either top or bottom),
C = FET gate capacitance,
V = maximum gate drive voltage (usually V
CC
),
f
OSC
= switching frequency.
Layout Considerations
1. The fast response time of V
2
technology increases
the IC's sensitivity to noise on the V
FB
line.
Fortunately, a simple RC filter, formed by the
feedback network and a small capacitor (100 pF
works well, shown below as C6) placed between
V
FB
and GND, filters out most noise and provides a
system practically immune to jitter. This capacitor
should be located as close as possible to the IC.
2. The COMP capacitor (shown below as C13)
should be connected via its own path to the IC
ground. The COMP capacitor is sensitive to the
intermittent ground drops caused by switching
currents. A separate ground path will reduce the
potential for jitter.
3. The V
CC
bypass capacitor (0.1
F or greater,
shown below as C4) should be located as close as
possible to the IC. This capacitor's connection to
GND must be as short as possible. The 10
resistor (shown below as R3) should be placed
close to the V
CC
pin.
4. The IC should not be placed in the path of
switching currents. If a ground plane is used, care
should be taken by the designer to ensure that the
IC is not located over a ground or other current
return path.
Figure 25.
V
OUT
R4
R6
C6
C4
R3
GND
12 V PWRGD
R1
U1
5 V
C13
C12
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PACKAGE DIMENSIONS
SO8
D SUFFIX
CASE 75107
ISSUE W
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
B
S
D
H
C
0.10 (0.004)
X
Y
G
M
Y
M
0.25 (0.010)
Z
Y
M
0.25 (0.010)
Z
S
X
S
M
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Notes
NCP1570
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16
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V
2
is a trademark of Switch Power, Inc.
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