Semiconductor Components Industries, LLC, 2004

November, 2004 - Rev. 6

Publication Order Number

NCP1575/D

NCP1575

Low Voltage Synchronous
Buck Controller with
Adjustable Switching
Frequency

The NCP1575 is a low voltage buck controller. It provides the

control for a DC-DC power solution producing an output voltage as
low as 0.980 V over a wide current range. It contains all required
circuitry for a synchronous NFET buck regulator using the V

control method to achieve the fastest possible transient response and
best overall regulation. The NCP1575 operates at a default switching
frequency of 200 kHz, but switching frequency is user-programmable
with an additional resistor between R

OSC

and ground. This device

provides undervoltage lockout protection, soft-start, and built-in
adaptive nonoverlap and is assembled in an SOIC-8 package.

The NCP1575-based solution requires a bias supply of 12 V, and it

can convert from a bulk power supply ranging from 2 V to 12 V.
Conversion from bulk supplies greater than 7 V is best accomplished
by using an external doubler circuit to raise the enhancement voltage
for the external NFET switches.

Features

Pb-Free Packages are Available

0.980 V

1.0% Reference Voltage

Control Topology

200 ns Transient Response

Programmable Soft-Start

40 ns Gate Rise and Fall Times (3.3 nF Load)

Adaptive FET Nonoverlap Time

Default 200 kHz Oscillator Frequency (No External

Resistor Required)

User-Programmable Oscillator Frequency (One External

Resistor Required)

Undervoltage Lockout

On/Off Control Through Use of the COMP Pin

Overvoltage Protection through Synchronous MOSFETs

Synchronous N-Channel Buck Design

"12 V Only" or Dual Supply Operation

Device

Package

Shipping

ORDERING INFORMATION

NCP1575D

SOIC-8

98 Units/Rail

NCP1575DR2

2500 Tape & Reel

SOIC-8

D SUFFIX

CASE 751

= Assembly Location

= Wafer Lot

= Year

= Work Week

GATE(H)

COMP

GATE(L)

OSC

GND

PIN CONNECTIONS

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1575

ALYW

MARKING
DIAGRAM

NCP1575DG

SOIC-8

(Pb-Free)

98 Units/Rail

SOIC-8

(Pb-Free)

NCP1575DR2G

2500 Tape & Reel

For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

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MAXIMUM RATINGS

Rating

Value

Unit

Operating Junction Temperature

150

Storage Temperature Range

-65 to 150

ESD Susceptibility (Human Body Model)

2.0

ESD Susceptibility (Charged Device Model)

200

Lead Temperature Soldering:

Reflow: (Note 1)

230 peak

Moisture Sensitivity Level

Package Thermal Resistance, SOIC-8:

Junction-to-Case, R

Junction-to-Ambient, R

165

C/W

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. 60 second maximum above 183

MAXIMUM RATINGS

Pin Name

Symbol

MAX

MIN

SOURCE

SINK

IC Power Input

20 V

-0.5 V

N/A

1.5 A Peak, 450 mA DC

Compensation Capacitor

COMP

6.0 V

-0.5 V

10 mA

Voltage Feedback Input

6.0 V

-0.5 V

1.0 mA

Frequency Adjust

OSC

6.0 V

-0.5 V

1.0 mA

High-Side FET Driver

GATE(H)

20 V

-0.5 V, -2.0 V for 50 ns

1.5 A Peak, 200 mA DC

Low-Side FET Driver

GATE(L)

20 V

-0.5 V, -2.0 V for 50 ns

1.5 A Peak, 200 mA DC

Ground

GND

0.5 V

-0.5 V

1.5 A Peak, 450 mA DC

N/A

ELECTRICAL CHARACTERISTICS

C < T

< 125

C, 9.0 V < V

< 20 V, C

GATE(H)

= C

GATE(L)

= 3.3 nF,

COMP

= 0.1

F, R

OSC

= 74 k

; unless otherwise specified.) Note 2

Characteristic

Test Conditions

Min

Typ

Max

Unit

Error Amplifier

Bias Current

= 0 V

0.4

2.0

COMP Source Current

COMP = 1.5 V, V

= 0.8 V

COMP Sink Current

COMP = 1.5 V, V

= 1.2 V

Reference Voltage

COMP = V

< 25

0.970

0.965

0.980

0.990

0.995

COMP Max Voltage

= 0.8 V

2.4

3.1

COMP Min Voltage

= 1.2 V

0.1

0.2

COMP Fault Discharge Current at UVLO

COMP = 1.2 V, V

= 6.9 V

0.5

1.2

COMP Fault Discharge Threshold to

Reset UVLO

0.1

0.25

0.3

Open Loop Gain

Unity Gain Bandwidth

kHz

PSRR @ 1.0 kHz

Output Transconductance

mmho

Output Impedance

2.5

2. Characteristics at temperature extremes are guaranteed via correlation using quality statistical control methods.

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ELECTRICAL CHARACTERISTICS

C < T

< 125

C, 9.0 V < V

< 20 V, C

GATE(H)

= C

GATE(L)

= 3.3 nF,

COMP

= 0.1

F, R

OSC

= 74 k

; unless otherwise specified.) Note 3

Characteristic

Test Conditions

Min

Typ

Max

Unit

GATE(H) and GATE(L)

Rise Time

1.0 V < GATE(L), GATE(H) < V

- 2.0 V,

= 12 V

Fall Time

- 2.0 V < GATE(L), GATE(H) < 1.0 V,

= 12 V

GATE(H) to GATE(L) Delay

GATE(H) < 2.0 V, GATE(L) > 2.0 V

105

GATE(L) to GATE(H) Delay

GATE(L) < 2.0 V, GATE(H) > 2.0 V

105

Minimum Pulse Width

GATE(X) = 4.0 V

250

High Voltage (AC)

Measure GATE(L) or GATE(H)

0.5 nF < C

GATE(H)

= C

GATE(L)

< 10 nF, Note 4

0.5

Low Voltage (AC)

Measure GATE(L) or GATE(H)

0.5 nF < C

GATE(H)

= C

GATE(L)

< 10 nF, Note 4

0.5

GATE(H)/(L) Pull-Down

Resistance to GND. Note 4

115

PWM Comparator

PWM Comparator Offset

= 0 V, Increase COMP Until GATE(H)

Starts Switching

0.415

0.465

0.525

Ramp Max Duty Cycle

Artificial Ramp

Duty Cycle = 50%, R

OSC

= 74 k

Transient Response

COMP = 1.5 V, V

20 mV Overdrive. Note 4

200

300

Input Range

Note 4

1.4

Oscillator

Switching Frequency

OSC

Not Used

OSC

= 74 k

170

240

200

280

230

320

kHz

General Electrical Specifications

Supply Current

COMP = 0 V (No Switching)

9.0

Start Threshold

GATE(H) Switching, COMP Charging

8.0

8.5

9.0

Stop Threshold

GATE(H) Not Switching, COMP Discharging

7.0

7.5

8.0

Hysteresis

Start - Stop

0.75

1.0

1.25

3. Characteristics at temperature extremes are guaranteed via correlation using quality statistical control methods.
4. Guaranteed by design. Not tested in production.

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PACKAGE PIN DESCRIPTION

PIN #

PIN SYMBOL

FUNCTION

Power supply input.

OSC

Frequency adjust pin. If not used, oscillator frequency is nominally 200 kHz. Connecting R

OSC

to ground

through a single resistor will increase oscillator frequency.

No connect.

COMP

Error amp output. PWM comparator reference input. A capacitor to LGND provides error amp compensa-
tion and Soft-Start. Pulling pin < 0.415 V locks gate outputs to a zero percent duty cycle state.

GATE(H)

High-side switch FET driver pin. Capable of delivering peak currents of 1.5 A.

GATE(L)

Low-side synchronous FET driver pin. Capable of delivering peak currents of 1.5 A.

Error amplifier and PWM comparator input.

GND

Power supply return.

Oscillator

200 kHz

Figure 4. Block Diagram

UVLO Comp

UVLO Latch

GND

8.5 V/7.5 V

0.25 V

0.98 V

Error Amp

COMP

PWM Comp

- +

0.465 V

PWM Latch

Reset

Dominant

Set

Dominant

Frequency

Adjust

GATE(H)

GATE(L)

OSC

Nonoverlap

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5. Supply Current vs. Temperature

Figure 6. Oscillator Frequency vs. Temperature

(No R

OSC

)

Figure 7. Oscillator Frequency vs. R

OSC

Value

Figure 8. Oscillator Frequency (R

OSC

= 74 k

)

vs. Temperature

Figure 9. Artificial Ramp at 50% Duty Cycle

vs. R

OSC

Value

Figure 10. Reference Voltage vs. Temperature

(mA)

Temperature (

100

120

Oscillator Frequency (kHz)

202

Temperature (

204

206

208

210

212

214

216

120

100

0.976

Temperature (

100

120

0.984

0.983

0.982

0.981

0.980

0.979

0.978

0.977

Reference V

oltage (V)

Oscillator Frequency (kHz)

100

OSC

Value (k

)

200

300

400

500

600

100

1000

Oscillator Frequency (kHz)

270

Temperature (

275

280

285

290

295

300

120

100

Artificial Ramp (mV)

OSC

Value (k

)

100

1000

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 11. PWM Offset Voltage vs. Temperature

Figure 12. Undervoltage Lockout Thresholds vs.

Temperature

Figure 13. V

Bias Current vs. Temperature

Figure 14. Error Amp Output Currents vs. Temperature

Figure 15. COMP Voltages vs. Temperature

PWM Of

fset V

oltage (mV)

450

Temperature (

455

460

465

470

100

120

Start/Stop Threshold V

oltages (V)

7.2

Temperature (

7.4

7.6

7.8

8.0

8.2

8.4

8.6

120

100

Turn-On

Threshold

Turn-Off

Threshold

0.40

Temperature (

100

120

0.60

0.55

0.50

0.45

Bias Current (

Temperature (

100

120

Output Current (

Sink Current

Source Current

Temperature (

100

120

3.5

3.0

2.5

2.0

1.5

1.0

0.5

COMP V

oltages (V)

COMP Maximum

COMP Minimum

Voltage

COMP Fault

Threshold Voltage

Voltage

Figure 16. COMP Fault Mode Discharge Current vs.

Temperature

Discharge

Current (mA)

0.90

Temperature (

0.95

1.00

1.05

1.15

1.20

100

120

1.10

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APPLICATION INFORMATION

THEORY OF OPERATION

The NCP1575 is a simple, synchronous, fixed-frequency,

low-voltage buck controller using the V

control method.

Control Method

The V

control method uses a ramp signal generated by

the ESR of the output capacitors. This ramp is proportional
to the ac current through the main inductor and is offset by
the dc output voltage. This control scheme inherently
compensates for variation in either line or load conditions,
since the ramp signal is generated from the output voltage
itself. The V

method differs from traditional techniques

such as voltage mode control, which generates an artificial
ramp, and current mode control, which generates a ramp
using the inductor current.

Figure 20. V

Control with Slope Compensation

COMP

Reference

Voltage

PWM

RAMP

Error

Amplifier

Error

Signal

Output
Voltage

GATE(H)

GATE(L)

Slope

Compensation

The V

control method is illustrated in Figure 20. The

output voltage generates both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it
is affected by any change in the output, regardless of the
origin of that change. The ramp signal also contains the DC
portion of the output voltage, allowing the control circuit to
drive the main switch from 0% to 100% duty cycle as
required.

A variation in line voltage changes the current ramp in the

inductor, which causes the V

control scheme to compensate

the duty cycle. Since any variation in inductor current
modifies the ramp signal, as in current mode control, the V

control scheme offers the same advantages in line transient
response.

A variation in load current will affect the output voltage,

modifying the ramp signal. A load step immediately changes
the state of the comparator output, which controls the main
switch. The comparator response time and the transition
speed of the main switch determine the load transient
response. Unlike traditional control methods, the reaction
time to the output load step is not related to the crossover
frequency of the error signal loop.

The error signal loop can have a low crossover frequency,

since the transient response is handled by the ramp signal
loop. The main purpose of this `slow' feedback loop is to
provide dc accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be rolled
off at a low frequency. Enhanced noise immunity improves
remote sensing of the output voltage, since the noise
associated with long feedback traces can be effectively
filtered.

Line and load regulation are drastically improved because

there are two independent control loops. A voltage mode
controller relies on the change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains a fixed error signal during
line transients, since the slope of the ramp signal changes in
this case. However, regulation of load transients still requires
a change in the error signal. The V

method of control

maintains a fixed error signal for both line and load variation,
since the ramp signal is affected by both line and load.

The stringent load transient requirements of modern

microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope in the output ripple can
lead to pulse width jitter and variation caused by both random
and synchronous noise. A ramp waveform generated in the
oscillator is added to the ramp signal from the output voltage
to provide the proper voltage ramp at the beginning of each
switching cycle. This slope compensation increases the noise
immunity, particularly at duty cycles above 50%.

Startup

The NCP1575 features a programmable soft-start

function, which is implemented through the error amplifier
and the external compensation capacitor. This feature
prevents stress to the power components and limits output
voltage overshoot during startup. As power is applied to the
regulator, the NCP1575 undervoltage lockout circuit (UVL)
monitors the IC's supply voltage (V

). The UVL circuit

holds the GATE(H) output low and the GATE(L) output
high until V

exceeds the 8.5 V threshold. A hysteresis

function of 1.0 V improves noise immunity. The
compensation capacitor connected to the COMP pin is
charged by a 30

mA current source. When the capacitor

voltage exceeds the 0.465 V offset of the PWM comparator,
the PWM control loop will allow switching to occur. The
upper gate driver GATE(H) is activated, turning on the upper
MOSFET. The current ramps up through the main inductor
and linearly powers the output capacitors and load. When
the regulator output voltage exceeds the COMP pin voltage
minus the 0.465 V PWM comparator offset threshold and
the artificial ramp, the PWM comparator terminates the
initial pulse.

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Figure 21. Idealized Waveforms

8.5 V

0.465 V

COMP

GATE(H)

UVLO

STARTUP

NORMAL OPERATION

Normal Operation

During normal operation, the duty cycle of the gate drivers

remains approximately constant as the V

control loop

maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load conditions
will result in changes in duty cycle to maintain regulation.

Input Supplies

The NCP1575 can be used in applications where a 12 V

supply is available along with a lower voltage supply. Often
the lower voltage supply is 5 V, but it can be any voltage less
than the 12 V supply minus the required gate drive voltage
of the top MOSFET. The greater the difference between the
two voltages, the better the efficiency due to increasing V

available to turn on the upper MOSFET. In order to maintain
power supply stability, the lower supply voltage should be
at least 1.5 times the desired voltage.

Adding a few additional components allows the NCP1575

to convert power in a "12 V only" application. This circuit
is illustrated in Figure 1. Note that in all cases, the maximum
supply voltage specification of 20 V must not be exceeded.

Gate Charge Effect on Switching Times

When using the onboard gate drivers, the gate charge has

an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading.

Transient Response

The 200 ns reaction time of the control loop provides fast

transient response to any variations in input voltage and
output current. Pulse-by-pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.

Overvoltage Protection

Overvoltage protection is provided as a result of the

normal operation of the V

control method and requires no

additional external components. The control loop responds

to an overvoltage condition within 200 ns, turning off the
upper MOSFET and disconnecting the regulator from its
input voltage. This results in a crowbar action to clamp the
output voltage, preventing damage to the load. The regulator
remains in this state until the overvoltage condition ceases.

Shutdown

When the input voltage connected to V

falls through the

lower threshold of the UVLO comparator, a fault latch is set.
The fault latch provides a signal that forces both GATE(H)
low and GATE(L) high, producing a low-impedance current
sink to ground at the converter switch node. At the same
time, the latch also turns on a transistor which pulls down on
the COMP pin, quickly discharging the external capacitor,
and allowing COMP to fall.

CONVERTER DESIGN

Choosing the V

OUT

Resistor Divider Values

The NCP1575 has an internal 0.98 V reference. A resistor

divider is used to set the output voltage.

OUT

Figure 22.

The formula to set the output voltage is

VOUT

(R1 R2

)

(0.98 V)

Arbitrarily choose a value of R2 that is sufficiently low

that the V

bias current (typically 50 nA) will have

negligible effect on the output voltage. Solve the equation
above for the value of R1.

Choosing the Oscillator Frequency

The NCP1575 has an oscillator that is trimmed to 200 kHz

at the factory. The NCP1575 will operate at this frequency
without the addition of any external components. However,
the oscillator is user-programmable with a single resistor.
This resistor is connected between the R

OSC

pin and ground.

Adding this resistor will raise the frequency above 200 kHz.
A graph of oscillator frequency vs. R

OSC

resistance is

provided in the typical operating characteristics section of
this data sheet.

Selection of the Output Capacitors

These components must be selected and placed carefully

to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their Equivalent

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Series Resistance (ESR), and Equivalent Series Inductance
(ESL). For best transient response, a combination of low
value/high frequency and bulk capacitors placed close to the
load will be required.

In order to determine the number of output capacitors the

maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.

The voltage change during the load current transient is:

VOUT

+ D

IOUT

ESL

)

ESR

)

tTR

COUT

where:

OUT

Dt = load current slew rate;

OUT

= load transient;

Dt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,

circuit traces, and vias;

ESR = Maximum allowable ESR including capacitors

and circuit traces;

= output voltage transient response time.

The designer has to independently assign values for the

change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.

The maximum allowable ESR can then be determined

according to the formula:

ESRMAX

+ D

VESR

IOUT

where:

ESR

= change in output voltage due to ESR (assigned

by the designer)

Once the maximum allowable ESR is determined, the

number of output capacitors can be found by using the
formula:

Number of capacitors

ESRCAP

ESRMAX

where:

ESR

CAP

= maximum ESR per capacitor (specified in

manufacturer's data sheet).

ESR

MAX

= maximum allowable ESR.

The actual output voltage deviation due to ESR can then

be verified and compared to the value assigned by the
designer:

VESR

+ D

IOUT

ESRMAX

Similarly, the maximum allowable ESL is calculated from

the following formula:

ESLMAX

+ D

VESL

Selection of the Input Inductor

A common requirement is that the buck controller must

not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor's limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.

The minimum inductance value for the input inductor is

therefore:

LIN

(dI dt)MAX

where:

= input inductor value;

DV = voltage seen by the input inductor during a full load

swing;

(dI/dt)

MAX

= maximum allowable input current slew rate.

The designer must select the LC filter pole frequency so

that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double-pole network
with a slope of -2.0, a roll-off rate of -40 dB/dec, and a
corner frequency:

where:

L = input inductor;
C = input capacitor(s).

Selection of the Output Inductor

There are many factors to consider when choosing the

output inductor. Maximum load current, core and winding
losses, ripple current, short circuit current, saturation
characteristics, component height and cost are all variables
that the designer should consider. However, the most
important consideration may be the effect inductor value has
on transient response.

The amount of overshoot or undershoot exhibited during

a current transient is defined as the product of the current
step and the output filter capacitor ESR. Choosing the
inductor value appropriately can minimize the amount of
energy that must be transferred from the inductor to the
capacitor or vice-versa. In the subsequent paragraphs, we
will determine the minimum value of inductance required
for our system and consider the trade-off of ripple current
vs. transient response.

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In order to choose the minimum value of inductance, input

voltage, output voltage and output current must be known.
Most computer applications use reasonably well regulated
bulk power supplies so that, while the equations below
specify V

IN(MAX)

or V

IN(MIN)

, it is possible to use the

nominal value of V

in these calculations with little error.

Current in the inductor while operating in the continuous

current mode is defined as the load current plus ripple
current.

ILOAD

)

IRIPPLE

The ripple current waveform is triangular, and the current

is a function of voltage across the inductor, switch FET
on-time and the inductor value. FET on-time can be defined
as the product of duty cycle and switch frequency, and duty
cycle can be defined as a ratio of V

OUT

to V

. Thus,

IRIPPLE

(VIN

VOUT)VOUT

(fOSC)(L)(VIN)

Peak inductor current is defined as the load current plus

half of the peak current. Peak current must be less than the
maximum rated FET switch current, and must also be less
than the inductor saturation current. Thus, the maximum
output current can be defined as:

IOUT(MAX)

ISWITCH(MAX)

VIN(MAX)

VOUT VOUT

2 fOSC L VIN(MAX)

Since the maximum output current must be less than the

maximum switch current, the minimum inductance required
can be determined.

L(MIN)

(VIN(MIN)

VOUT)VOUT

(fOSC)(ISWITCH(MAX))(VIN(MIN))

This equation identifies the value of inductor that will

provide the full rated switch current as inductor ripple
current, and will usually result in inefficient system
operation. The system will sink current away from the load
during some portion of the duty cycle unless load current is
greater than half of the rated switch current. Some value
larger than the minimum inductance must be used to ensure
the converter does not sink current. Choosing larger values
of inductor will reduce the ripple current, and inductor value
can be designed to accommodate a particular value of ripple
current by replacing I

SWITCH(MAX)

with a desired value of

RIPPLE

L(RIPPLE)

(VIN(MIN)

VOUT)VOUT

(fOSC)(IRIPPLE)(VIN(MIN))

However, reducing the ripple current will cause transient

response times to increase. The response times for both
increasing and decreasing current steps are shown below.

TRESPONSE(INCREASING)

(L)(

IOUT)

(VIN

VOUT)

TRESPONSE(DECREASING)

(L)(

IOUT)

(VOUT)

Inductor value selection also depends on how much output

ripple voltage the system can tolerate. Output ripple voltage
is defined as the product of the output ripple current and the
output filter capacitor ESR.

Thus, output ripple voltage can be calculated as:

VRIPPLE

ESRC IRIPPLE

ESRC VIN

VOUT VOUT

fOSC L VIN

Finally, we should consider power dissipation in the

output inductors. Power dissipation is proportional to the
square of inductor current:

2
L

)(ESRL)

The temperature rise of the inductor relative to the air

surrounding it is defined as the product of power dissipation
and thermal resistance to ambient:

T(inductor)

(Ra)(PD)

Ra for an inductor designed to conduct 20 A to 30 A is

approximately 45

C/W. The inductor temperature is given as:

T(inductor)

+ D

T(inductor)

)

Tambient

Bypass Filtering

A small RC filter should be added between module V

and the V

input to the IC. A 10

W resistor and a 0.47 mF

capacitor should be sufficient to ensure the controller IC does
not operate erratically due to injected noise, and will also
supply reserve charge for the onboard gate drivers.

Input Filter Capacitors

The input filter capacitors provide a charge reservoir that

minimizes supply voltage variations due to changes in current
flowing through the switch FETs. These capacitors must be
chosen primarily for ripple current rating.

Figure 23.

OUT

IN(AVE)

RMS(CIN)

CONTROL

INPUT

OUT

Consider the schematic shown in Figure 23. The average

current flowing in the input inductor L

for any given

output current is:

IIN(AVE)

IOUT

VOUT

VIN

Input capacitor current is positive into the capacitor when

the switch FETs are off, and negative out of the capacitor
when the switch FETs are on. When the switches are off,
I

IN(AVE)

flows into the capacitor. When the switches are on,

capacitor current is equal to the per-phase output current

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minus I

IN(AVE)

. If we ignore the small current variation due

to the output ripple current, we can approximate the input
capacitor current waveform as a square wave. We can then
calculate the RMS input capacitor ripple current:

IRMS(CIN)

2
IN(AVE)

)

VOUT

VIN

IOUT per phase

IIN(AVE) 2

2
IN(AVE)

The input capacitance must be designed to conduct the

worst case input ripple current. This will require several
capacitors in parallel. In addition to the worst case current,
attention must be paid to the capacitor manufacturer's
derating for operation over temperature.

As an example, let us define the input capacitance for a

5 V to 3.3 V conversion at 10 A at an ambient temperature
of 60

C. Efficiency of 80% is assumed. Average input

current in the input filter inductor is:

IIN(AVE)

(10 A)(3.3 V 5 V)

6.6 A

Input capacitor RMS ripple current is then

IIN(RMS)

6.62

)

3.3 V

5 V

[(10 A

6.6 A)2

6.6 A2]

4.74 A

If we consider a Rubycon MBZ series capacitor, the ripple

current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at
100 kHz and 105

C. We determine the number of input

capacitors by dividing the ripple current by the
per-capacitor current rating:

Number of capacitors

4.74 A 2.0 A

2.3

A total of at least 3 capacitors in parallel must be used to

meet the input capacitor ripple current requirements.

Output Switch FETs

Output switch FETs must be chosen carefully, since their

properties vary widely from manufacturer to manufacturer.
The NCP1575 system is designed assuming that n-channel
FETs will be used. The FET characteristics of most concern
are the gate charge/gate-source threshold voltage, gate
capacitance, on-resistance, current rating and the thermal
capability of the package.

The onboard FET driver has a limited drive capability. If

the switch FET has a high gate charge, the amount of time
the FET stays in its ohmic region during the turn-on and
turn-off transitions is larger than that of a low gate charge
FET, with the result that the high gate charge FET will
consume more power. Similarly, a low on-resistance FET
will dissipate less power than will a higher on-resistance

FET at a given current. Thus, low gate charge and low
R

DS(ON)

will result in higher efficiency and will reduce

generated heat.

It can be advantageous to use multiple switch FETs to

reduce power consumption. By placing a number of FETs in
parallel, the effective R

DS(ON)

is reduced, thus reducing the

ohmic power loss. However, placing FETs in parallel
increases the gate capacitance so that switching losses
increase. As long as adding another parallel FET reduces the
ohmic power loss more than the switching losses increase,
there is some advantage to doing so. However, at some point
the law of diminishing returns will take hold, and a marginal
increase in efficiency may not be worth the board area
required to add the extra FET. Additionally, as more FETs
are used, the limited drive capability of the FET driver will
have to charge a larger gate capacitance, resulting in
increased gate voltage rise and fall times. This will affect the
amount of time the FET operates in its ohmic region and will
increase power dissipation.

The following equations can be used to calculate power

dissipation in the switch FETs.

For ohmic power losses due to R

DS(ON)

PON(TOP)

(RDS(ON)(TOP))(IRMS(TOP))2

(number of topside FETs)

PON(BOTTOM)

RDS(ON)(BOTTOM) IRMS(BOTTOM) 2

number of bottom-side FETs

Note that R

DS(ON)

increases with temperature. It is good

practice to use the value of R

DS(ON)

at the FET's maximum

junction temperature in the calculations shown above.

IRMS(TOP)

2
PK

(IPK)(IRIPPLE)

)

2
RIPPLE

IRMS(BOTTOM)

2
PK

(IPKIRIPPLE)

)

2
RIPPLE

IRIPPLE

(VIN

VOUT)(VOUT)

(fOSC)(L)(VIN)

IPEAK

ILOAD

)

IRIPPLE

IOUT

)

IRIPPLE

where:

D = Duty cycle.
For switching power losses:

nCV2(fOSC)

where:

n = number of switch FETs (either top or bottom),
C = FET gate capacitance,
V = maximum gate drive voltage (usually V

OSC

= switching frequency.

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Layout Considerations

1. The fast response time of V

technology increases

the IC's sensitivity to noise on the V

line.

Fortunately, a simple RC filter, formed by the
feedback network and a small capacitor (100 pF
works well) placed between V

and GND filters

out most noise and provides a system practically
immune to jitter. This capacitor should be located
as close as possible to the IC.

2. The COMP capacitor should be connected via its

own path to the IC ground. The COMP capacitor
is sensitive to the intermittent ground drops caused

by switching currents. A separate ground path will
reduce the potential for jitter.

3. The V

bypass capacitor (0.1

mF or greater)

should be located as close as possible to the IC.
This capacitor's connection to GND must be as
short as possible. A 10

W resistor should be placed

close to the V

pin.

4. The IC should not be placed in the path of

switching currents. If a ground plane is used, care
should be taken by the designer to ensure that the
IC is not located over a ground or other current
return path.

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PACKAGE DIMENSIONS

SOIC-8

D SUFFIX

CASE 751-07

ISSUE AC

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

SEATING
PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751-01 THRU 751-06 ARE OBSOLETE. NEW

STANDARD IS 751-07.

0.10 (0.004)

DIM

MIN

MAX

MIN

MAX

INCHES

4.80

5.00

0.189

0.197

MILLIMETERS

3.80

4.00

0.150

0.157

1.35

1.75

0.053

0.069

0.33

0.51

0.013

0.020

1.27 BSC

0.050 BSC

0.10

0.25

0.004

0.010

0.19

0.25

0.007

0.010

0.40

1.27

0.016

0.050

0.25

0.50

0.010

0.020

5.80

6.20

0.228

0.244

-X-

-Y-

0.25 (0.010)

-Z-

0.25 (0.010)

1.52

0.060

7.0

0.275

0.6

0.024

1.270
0.050

4.0

0.155

inches

SCALE 6:1

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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Phone: 81-3-5773-3850

NCP1575/D

is a trademark of Switch Power, Inc.

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