Semiconductor Components Industries, LLC, 2006

May, 2006 - Rev. 1

Publication Order Number:

NCP3163/D

NCP3163

3.4 A, Step-Up/Down/

Inverting 50-300 kHz

Switching Regulator

The NCP3163 Series is a performance enhancement to the popular

MC33163 and MC34163 monolithic DC-DC converters. These
devices consist of an internal temperature compensated reference,
comparator, controlled duty cycle oscillator with an active current
limit circuit, driver and high current output switch. This controller was
specifically designed to be incorporated in step-down, step-up, or
voltage-inverting applications with a minimum number of external
components. The NCP3163 comes in an exposed pad package which
can greatly increase the power dissipation of the built in power switch.

Features

Output Switch Current in Excess of 3.0 A

3.4 A Peak Switch Current

Frequency is Adjustable from 50 kHz to 300 kHz

Operation from 2.5 V to 40 V Input

Externally Adjustable Operating Frequency

Precision 2% Reference for Accurate Output Voltage Control

Driver with Bootstrap Capability for Increased Efficiency

Cycle-by-Cycle Current Limiting

Internal Thermal Shutdown Protection

Low Voltage Indicator Output for Direct Microprocessor Interface

Exposed Pad Power Package

Low Standby Current

This is a Pb-Free Device

LVI

Oscillator

+
+
-

Current

Limit

Figure 1. Typical Buck Application Circuit

(Bottom View)

+
+
-

Thermal

out

See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

NCP3163x = Specific Device Code
A

= Assembly Location

WL = Wafer Lot
YY = Year
WW = Work Week
G

= Pb-Free Package

SOIC-16W

EXPOSED PAD

PW SUFFIX

CASE 751AG

http://onsemi.com

NCP3163xPW

AWLYYWWG

*For additional information on our Pb-Free strategy

and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

18-LEAD DFN

MN SUFFIX

CASE 505

NCP3163x

AWLYYWW

(Note: Microdot may be in either location)

NCP3163

http://onsemi.com

LVI

Oscillator

+
+
-

Current

Limit

Figure 2. Representative Block Diagram

(Bottom View)

+
+
-

Thermal

Driver Collector

Switch Collector

0.25 V

Switch Emitter

Bootstrap Input

Voltage Feedback 1

Voltage Feedback 2

LVI Output

Gnd

PKsense

Timing Capacitor

2.0 mA

7.0 V

1.125 V

15 k

1.25 V

Feedback

Comparator

Shutdown

45 k

Latch

= Sink Only
Positive True Logic

PIN FUNCTION DESCRIPTION

SOIC16

DFN18

PIN NAME

DESCRIPTION

LVI Output

This pin will sink current when FB1 and FB2 are less than the LVI threshold (V

Voltage Feedback 2

Connecting this pin to a resistor divider off of the output will regulate the application
according to the V

out

design equation in Figure 22.

Voltage Feedback 1

Connecting this pin directly to the output will regulate the device to 5.05 V.

GND

Ground pin for all internal circuits and power switch.

Timing Capacitor

Connect a capacitor to this pin to set the frequency. The addition of a parallel resis-
tor will decrease the maximum duty cycle and increase the frequency.

Power pin for the IC.

Sense

When (V

-V

IPKsense

) > 250 mV the circuit resets the output driver on a pulse by

pulse basis.

Drive Collector

Voltage driver collector

10,11

6,7,8,9

Switch Collector

Internal switch transistor collector

14,15

10,11,12,13

Switch Emitter

Internal switch transistor emitter

Bootstrap Input

Connect this pin to V

for operation at low V

levels. For some topologies, a

series resistor and capacitor can be utilized to improve the converter efficiency.

5,12,13

No Connect

These pins have no connection.

Exposed

Pad

Exposed

Pad

Exposed Pad

The exposed pad beneath the package must be connected to GND (pin 4). Addi-
tionally, using proper layout techniques, the exposed pad can greatly enhance the
power dissipation capabilities of the NCP3163.

NCP3163

http://onsemi.com

MAXIMUM RATINGS

(Note 1)

Rating

Symbol

Value

Unit

Power Supply Voltage

0 to +40

Switch Collector Voltage Range

CSW

-1.0 to +40

Switch Emitter Voltage Range

ESW

-2.0 to +40

Switch Collector to Emitter Voltage

CESW

+40

Switch Current

3.4

Driver Collector Voltage (Pin 8)

-1.0 to +40

Driver Collector Current (Pin 8)

150

Bootstrap Input Current Range

BST

-100 to +100

Current Sense Input Voltage Range

IPKSNS

- 7.0) to (V

+ 1.0)

Feedback and Timing Capacitor Input Voltage Range

-1.0 to +7.0

Low Voltage Indicator Output Voltage Range

CLVI

-1.0 to +40

Low Voltage Indicator Output Sink Current

CLVI

Power Dissipation and Thermal Characteristics

Thermal Characteristics

Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Air

15
56

C/W

Storage Temperature Range

stg

-65 to +150

Maximum Junction Temperature

Jmax

+150

Operating Ambient Temperature (Note 3)

NCP3163PW
NCP3163BPW

0 to +70

-40 to +85

PIN CONNECTIONS

N/C

GND
Voltage Feedback 1

LVI Output

Bootstrap Input

Switch Emitter

Voltage Feedback 2

Timing Capacitor

N/C

Sense

Switch Collector

Driver Collector

1
2
3

4
5
6
7

16
15

14
13
12

11
10

Note: Pin 18 must be tied to EP Flag on PCB

GND

EP Flag

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:

Human Body Model 1500 V per MIL-STD-883, Method 3015.
Machine Model Method 150 V.

2. This device contains latch-up protection and exceeds 100 mA per JEDEC Standard JESD78.
3. Maximum package power dissipation limits must be observed. Maximum Junction Temperature must not be exceeded.
4. The pins which are not defined may not be loaded by external signals.

(Top View)

LVI Output

Voltage Feedback 2

Voltage Feedback 1

GND

Timing Capacitor

Sense

Bootstrap Input

Switch
Emitter

N/C

Switch Collector

Driver Collector

NCP3163

http://onsemi.com

ELECTRICAL CHARACTERISTICS

= 15 V, Pin 16 = V

, C

= 270 pF, R

= 15 k

, for typical values T

= 25

C, for min/max

values T

is the operating ambient temperature range that applies (Note 5), unless otherwise noted.)

Characteristic

Symbol

Min

Typ

Max

Unit

OSCILLATOR

Frequency

= 25

C, V

= 15 V

Total Variation over V

= 2.5 V to 40 V and Temperature (Note 5)

OSC

225
212

250
250

275
288

kHz

Charge Current

chg

225

Discharge Current

dischg

Charge to Discharge Current Ratio

chg

dischg

8.0

9.0

Sawtooth Peak Voltage

OSC(P)

1.25

Sawtooth Valley Voltage

OSC(V)

0.55

FEEDBACK COMPARATOR 1

Threshold Voltage

= 25

Total Variation over V

= 2.5 V to 40 V and Temperature (Note 5)

th(FB1)

4.9

4.85

5.05

5.2

5.25

Threshold Voltage

Line Regulation (V

= 2.5 V to 40 V, T

= 25

REGline

(FB1)

0.008

0.03

%/V

Input Bias Current (V

FB1

= 5.05 V)

IB(FB1)

100

200

FEEDBACK COMPARATOR 2

Threshold Voltage

= 25

C, V

= 15 V

Total Variation over V

= 2.5 V to 40 V and Temperature (Note 5)

th(FB2)

1.225
1.213

1.25

1.275
1.287

Threshold Voltage

Line Regulation (V

= 2.5 V to 40 V, T

= 25

REGline

(FB1)

0.008

0.03

%/V

Input Bias Current (V

FB2

= 1.25 V)

IB(FB2)

- 0.4

0.4

CURRENT LIMIT COMPARATOR

Threshold Voltage

= 25

Total Variation over V

= 2.5 V to 40 V, and Temperature (Note 5)

th(Sense)

230

250

270

Input Bias Current (V

Ipk (Sense)

= 15 V)

IB(Sense)

1.0

DRIVER AND OUTPUT SWITCH (Note 6)

Saturation Voltage (I

= 2.5 A, Pins 14, 15 grounded)

Non-Darlington Connection (R

Pin 9

= 110

to V

, I

DRV

20)

Darlington Connection (Pins 9, 10, 11 connected) (Note 7)

CE(sat)

-
-

0.6
1.0

1.0
1.4

Collector Off-State Leakage Current (V

= 40 V)

C(off)

0.02

100

Bootstrap Input Current Source (V

= V

+ 5.0 V)

source(DRV)

0.5

2.0

4.0

Bootstrap Input Zener Clamp Voltage (I

= 25 mA)

+ 6.0

+ 7.0

+ 9.0

LOW VOLTAGE INDICATOR

Input Threshold (V

FB2

Increasing)

1.07

1.125

1.18

Input Hysteresis (V

FB2

Decreasing)

Output Sink Saturation Voltage (I

sink

= 2.0 mA)

OL(LVI)

0.15

0.4

Output Off-State Leakage Current (V

= 15 V)

0.01

5.0

TOTAL DEVICE

Standby Supply Current (V

= 2.5 V to 40 V, Pin 8 = V

Pins 6, 14, 15 = GND, remaining pins open)

6.0

5. Maximum package power dissipation limits must be observed.
6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
7. T

low

= 0

C for NCP3163

high

= + 70

C for NCP3163

= - 40

C for NCP3163B

= + 85

C for NCP3163B

NCP3163

http://onsemi.com

Figure 3. Oscillator Frequency vs. Timer

Capacitance (C

)

300

, TIMER CAPACITANCE (pF)

FREQUENCY

(kHz)

200

100

200

300

400

500

600

700

= 15 V

= 25

°C

Figure 4. Oscillator Frequency Change vs.

Temperature when only C

is connected to Pin 6

2.0

- 55

, AMBIENT TEMPERATURE (

°C)

f OSC

OSCILLA

FREQUENCY

CHANGE (%)

- 2.0

- 4.0

- 6.0

- 25

100

125

= 15 V

= 620 pF

Figure 5. Oscillator Frequency Change vs.

Temperature when C

and R

are connected to Pin 6

4.0

- 50

TEMPERATURE (

°C)

f OSC

OSCILLA

FREQUENCY

CHANGE (%)

- 2.0

- 8.0

- 10

- 25

100

125

- 6.0

- 4.0

2.0

= 15 V

= 230 pF

= 20 k

150

250

= 15 k

= open

Figure 6. Feedback Comparator 1 Input Bias

Current vs. Temperature

Figure 7. Feedback Comparator 2 Threshold

Voltage vs. Temperature

I IB

INPUT

BIAS CURRENT

(A)

140

- 55

, AMBIENT TEMPERATURE (

°C)

120

100

- 25

100

125

th(FB2)

, COMP

ARA

THRESHOLD

VOL

T
AGE (mV)

1300

1280

1260

1240

1220

1200

- 55

, AMBIENT TEMPERATURE (

°C)

- 25

100

125

Typ = 1250 mV

Min = 1225 mV

= 15 V

FB1

= 5.05 V

Max = 1275 mV

= 15 V

NCP3163

http://onsemi.com

2.8

2.4

2.0

1.6

1.2

- 55

- 25

100

125

, AMBIENT TEMPERATURE (

°C)

I source (DR

BOOTSTRAP

INPUT

CURRENT

SOURCE (m

= 15 V

Pin 16 = V

+ 5.0 V

7.6

7.4

7.2

7.0

6.8

- 55

- 25

100

125

, AMBIENT TEMPERATURE (

°C)

= 25 mA

BOOTSTRAP

INPUT

ZENER CLAMP

VOL

T
AGE

(
V

Figure 8. Bootstrap Input Current

Source vs. Temperature

Figure 9. Bootstrap Input Zener Clamp

Voltage vs. Temperature

CE (sat)

- 0.4

0.8

2.4

3.2

, EMITTER CURRENT (A)

, SOURCE SA

TURA

TION

(V)

- 0.8

-1.2

-1.6

- 2.0

1.2

1.0

, COLLECTOR CURRENT (A)

0.8

0.6

0.4

0.2

GND

CE (sat)

, SINK SA

TURA

TION (V)

1.6

Bootstrapped, Pin 16 = V

+ 5.0 V

Non-Bootstrapped, Pin 16 = V

0.8

2.4

3.2

1.6

Figure 10. Output Switch Source Saturation

vs. Emitter Current

Figure 11. Output Switch Sink Saturation

vs. Collector Current

Darlington, Pins 9, 10, 11 Connected

Grounded Emitter Configuration
Collector Sinking Current From V

Pins 7, 8 = V

= 15 V

Pins 4, 5, 12, 13, 14, 15 = GND
T

= 25

°C, (Note 2)

Saturated Switch, R

Pin9

= 110

W to V

Darlington Configuration
Emitter Sourcing Current to GND
Pins 7, 8, 10, 11 = V

Pins 4, 5, 12, 13 = GND
T

= 25

°C, (Note 2)

Figure 12. Output Switch Negative Emitter

Voltage vs. Temperature

Figure 13. Low Voltage Indicator Output Sink

Saturation Voltage vs. Sink Current

, EMITTER VOL

T
AGE

(V)

- 0.4

- 0.8

- 1.2

- 1.6

- 2.0

- 55

- 25

100

125

, AMBIENT TEMPERATURE (

°C)

= 10 mA

VI)

, OUTPUT

TURA

TION VOL

T
AGE

(V) 0.5

0.4

2.0

4.0

6.0

8.0

sink

, OUTPUT SINK CURRENT (mA)

0.3

0.2

0.1

= 5 V

= 25

°C

GND

= 10

= 15 V

Pins 7, 8, 9, 10, 16 = V

Pins 4, 6 = GND
Pin 14 Driven Negative

NCP3163

http://onsemi.com

Figure 14. Current Limit Comparator Threshold

Voltage vs. Temperature

Figure 15. Current Limit Comparator Input Bias

Current vs. Temperature

th (Ipk Sense)

, THRESHOLD

VOL

T
AGE

(mV

254

252

250

248

246

- 55

- 25

100

125

, AMBIENT TEMPERATURE (

°C)

I IB (Sense)

INPUT

BIAS

CURRENT

(

1.6

1.4

1.2

1.0

0.8

- 55

- 25

100

125

, AMBIENT TEMPERATURE (

°C)

0.6

= 15 V

Ipk (Sense)

= 15 V

I CC

, SUPPL

CURRENT

(mA)

Figure 16. Standby Supply Current

vs. Supply Voltage

Figure 17. Standby Supply Current

vs. Temperature

I CC

, SUPPL

CURRENT

(mA)

8.0

6.0

4.0

2.0

, SUPPLY VOLTAGE (V)

Pins 7, 8, 16 = V

Pins 4, 6, 14 = GND
Remaining Pins Open
T

= 25

°C

7.2

6.4

5.6

4.8

- 55

- 25

100

125

, AMBIENT TEMPERATURE (

°C)

4.0

= 15 V

Pins 7, 8, 16 = V

Pins 4, 6, 14 = GND
Remaining Pins Open

Figure 18. Minimum Operating Supply

Voltage vs. Temperature

3.0

2.6

2.2

1.8

1.4

1.0

- 55

- 25

100

125

, AMBIENT TEMPERATURE (

°C)

CC(min)

, MINIMUM OPERA

TING

SUPPL

VOL

T
AGE

(V)

Pin 16 Open

= 620 pF

Pins 7,8 = V

Pins 4, 14 = GND
Pin 9 = 1.0 k

W to 15 V

Pin 10 = 100

W to 15 V

Pin 16 = V

NCP3163

http://onsemi.com

INTRODUCTION

The NCP3163 is a monolithic power switching regulator

optimized for DC-to-DC converter applications. The
combination of its features enables the system designer to
directly implement step-up, step-down, and voltage-
inverting converters with a minimum number of external
components. Potential applications include cost sensitive
consumer products as well as equipment for the automotive,
computer, and industrial markets. A representative block
diagram is shown in Figure 2.

OPERATING DESCRIPTION

The NCP3163 operates as a fixed on-time, variable

off-time voltage mode ripple regulator. In general, this
mode of operation is somewhat analogous to a capacitor
charge pump and does not require dominant pole loop
compensation for converter stability. The Typical Operating
Waveforms are shown in Figure 19. The output voltage
waveform shown is for a step-down converter with the
ripple and phasing exaggerated for clarity. During initial
converter startup, the feedback comparator senses that the
output voltage level is below nominal. This causes the
output switch to turn on and off at a frequency and duty cycle
controlled by the oscillator, thus pumping up the output filter
capacitor. When the output voltage level reaches nominal,
the feedback comparator sets the latch, immediately
terminating switch conduction. The feedback comparator
will inhibit the switch until the load current causes the output
voltage to fall below nominal. Under these conditions,
output switch conduction can be inhibited for a partial

oscillator cycle, a partial cycle plus a complete cycle,
multiple cycles, or a partial cycle plus multiple cycles.

Oscillator

The oscillator frequency and on-time of the output switch

are programmed by the value selected for timing capacitor
C

. Capacitor C

is charged and discharged by a 9 to 1 ratio

internal current source and sink, generating a negative going
sawtooth waveform at Pin 6. As C

charges, an internal

pulse is generated at the oscillator output. This pulse is
connected to the NOR gate center input, preventing output
switch conduction, and to the AND gate upper input,
allowing the latch to be reset if the comparator output is low.
Thus, the output switch is always disabled during ramp-up
and can be enabled by the comparator output only at the start
of ramp-down. The oscillator peak and valley thresholds are
1.25 V and 0.55 V, respectively, with a charge current of
225

mA and a discharge current of 25 mA, yielding a

maximum on-time duty cycle of 90%. A reduction of the
maximum duty cycle may be required for specific converter
configurations. This can be accomplished with the addition
of an external deadtime resistor (R

) placed across C

. The

resistor increases the discharge current which reduces the
on-time of the output switch. The converter output can be
inhibited by clamping C

to ground with an external NPN

small-signal transistor. To calculate the frequency when
only C

is connected to Pin 6, use the equations found in

Figure 22. When R

is also used, the frequency and

maximum duty cycle can be calculated with the NCP3163
design tool found at www.onsemi.com.

Comparator Output

Timing Capacitor C

Oscillator Output

Output Switch

Output Voltage

Nominal Output

Voltage Level

1.25 V

0.55 V

Off

Figure 19. Typical Operating Waveforms

Startup

Quiescent Operation

NCP3163

http://onsemi.com

Feedback and Low Voltage Indicator Comparators

Output voltage control is established by the Feedback

comparator. The inverting input is internally biased at 1.25 V
and is not pinned out. The converter output voltage is
typically divided down with two external resistors and
monitored by the high impedance noninverting input at Pin 2.
The maximum input bias current is

±0.4 mA, which can cause

an output voltage error that is equal to the product of the input
bias current and the upper divider resistance value. For
applications that require 5.0 V, the converter output can be
directly connected to the noninverting input at Pin 3. The high
impedance input, Pin 2, must be grounded to prevent noise
pickup. The internal resistor divider is set for a nominal
voltage of 5.05 V. The additional 50 mV compensates for a
1.0% voltage drop in the cable and connector from the
converter output to the load. The Feedback comparator's

output state is controlled by the highest voltage applied to
either of the two noninverting inputs.

The Low Voltage Indicator (LVI) comparator is designed

for use as a reset controller in microprocessor-based
systems. The inverting input is internally biased at 1.125 V,
which sets the noninverting input thresholds to 90% of
nominal. The LVI comparator has 15 mV of hysteresis to
prevent erratic reset operation. The Open Collector output is
capable of sinking in excess of 6.0 mA (see Figure 13). An
external resistor (R

LVI

) and capacitor (C

DLY

)

can be used to

program a reset delay

time (t

DLY

) by the formula shown

below, where V

th(MPU)

is the microprocessor reset input

threshold. Refer to Figure 20.

DLY

= R

LVI

DLY

1 -

th(MPU)

out

Figure 20. Partial Application Schematic Showing

Implementation of LVI Delay with R

LVI

and C

DLY

LVI

+
+
-

(Bottom View)

+
+
-

1.125 V

1.25 V

Feedback
Comparator

out

Low Voltage

Indicator Output

DLY

LVI

Current Limit Comparator, Latch and Thermal
Shutdown

With a voltage mode ripple converter operating under

normal conditions, output switch conduction is initiated by
the oscillator and terminated by the Voltage Feedback
comparator. Abnormal operating conditions occur when the
converter output is overloaded or when feedback voltage
sensing is lost. Under these conditions, the Current Limit
comparator will protect the Output Switch.

The switch current is converted to a voltage by inserting

a fractional ohm resistor, R

, in series with V

and output

switch transistor Q

. The voltage drop across R

monitored by the Current Sense comparator. If the voltage
drop exceeds 250 mV with respect to V

, the comparator

will set the latch and terminate output switch conduction on
a cycle-by-cycle basis. This Comparator/Latch
configuration ensures that the Output Switch has only a
single on-time during a given oscillator cycle. The
calculation for a value of R

is:

RSC

0.25 V

Ipk (Switch)

Figures 14 and 15 show that the Current Sense comparator

threshold is tightly controlled over temperature and has a
typical input bias current of 1.0

mA. The propagation delay

from the comparator input to the Output Switch is typically

200 ns. The parasitic inductance associated with R

and the

circuit layout should be minimized. This will prevent
unwanted voltage spikes that may falsely trip the Current
Limit comparator.

Internal thermal shutdown circuitry is provided to protect

the IC in the event that the maximum junction temperature
is exceeded. When activated, typically at 170

°C, the Latch

is forced into the "Set" state, disabling the Output Switch.
This feature is provided to prevent catastrophic failures from
accidental device overheating. It is not intended to be used
as a replacement for proper heatsinking.

Driver and Output Switch

To aid in system design flexibility and conversion

efficiency, the driver current source and collector, and
output switch collector and emitter are pinned out
separately. This allows the designer the option of driving the
output switch into saturation with a selected force gain or
driving it near saturation when connected as a Darlington.
The output switch has a typical current gain of 70 at 2.5 A
and is designed to switch a maximum of 40 V collector to
emitter, with up to 3.4 A peak collector current. The
minimum value for R

is:

RSC(min)

0.25 V

3.4 A

0.0735

NCP3163

http://onsemi.com

When configured for step-down or voltage-inverting

applications (see application notes at the end of this
document) the inductor will forward bias the output rectifier
when the switch turns off. Rectifiers with a high forward
voltage drop or long turn-on delay time should not be used.
If the emitter is allowed to go sufficiently negative, collector
current will flow, causing additional device heating and
reduced conversion efficiency.

Figure 12 shows that by clamping the emitter to 0.5 V, the

collector current will be in the range 10

mA over

temperature. A 1N5822 or equivalent Schottky barrier
rectifier is recommended to fulfill these requirements.

A bootstrap input is provided to reduce the output switch

saturation voltage in step-down and voltage-inverting
converter applications. This input is connected through a
series resistor and capacitor to the switch emitter and is used
to raise the internal 2.0 mA bias current source above V

An internal zener limits the bootstrap input voltage to V

+7.0 V. The capacitor's equivalent series resistance must
limit the zener current to less than 100 mA. An additional
series resistor may be required when using tantalum or other

low ESR capacitors. The equation below is used to calculate
a minimum value bootstrap capacitor based on a minimum
zener voltage and an upper limit current source.

CB(min)

4.0 mA

ton

4.0 V

0.001 ton

Parametric operation of the NCP3163 is guaranteed over

a supply voltage range of 2.5 V to 40 V. When operating
below 3.0 V, the Bootstrap Input should be connected to
V

. Figure 18 shows that functional operation down to

1.7 V at room temperature is possible.

Package

The NCP3163 is contained in a heatsinkable 16-lead

plastic package in which the die is mounted on a special heat
tab copper alloy pad. This pad is designed to be soldered
directly to a GND connection on the printed circuit board to
improve thermal conduction. Since this pad directly
contacts the substrate of the die, it is important that this pad
be always soldered to GND, even if surface mount heat
sinking is not being used. Figure 21 shows recommended
layout techniques for this package.

Figure 21. Layout Guidelines to Obtain Maximum

Package Power Dissipation

Flare Metal for Maximum Heat Sinking

0.145

0.175

Exposed Pad

0.188

Vias to 2nd Layer Metal
for Maximum Heat Sinking

Minimum
Recommended
Exposed Copper

APPLICATIONS

Figures 23 through 30 show the simplicity and flexibility

of the NCP3163. Three main converter topologies are
demonstrated with actual test data shown below each of the
circuit diagrams. Figure 22 gives the relevant design

equations for the key parameters. Additionally, a complete
application design aid for the NCP3163 can be found at
www.onsemi.com.

NCP3163

http://onsemi.com

Calculation

Step-Down

Step-Up

Voltage-Inverting

ton
toff

(See Notes 1,2,3)

Vout

)

Vsat

Vout

)

Vsat

|Vout|

)

Vsat

ton

ton
t

off

ton
t

off

)

ton
t

off

ton
t

off

)

ton
t

off

ton
t

off

)

32.143 · 10

IL(avg)

Iout

ton
t

off

)

Iout

ton
t

off

)

Ipk (Switch)

IL(avg)

)

IL(avg)

)

IL(avg)

)

RSC

0.25

Ipk (Switch)

0.25

Ipk (Switch)

0.25

Ipk (Switch)

Vsat

Vout

ton

Vsat

ton

Vsat

ton

ripple(pp)

)

(ESR)2

[

ton Iout

[

ton Iout

Vout

ref

)

ref

)

ref

)

out

ripple(pp)

Nominal operating input voltage.
Desired output voltage.
Desired output current.
Desired peak-to-peak inductor ripple current. For maximum output current it is suggested that

be chosen to be less

than 10% of the average inductor current I

L(avg)

. This will help prevent I

pk (Switch)

from reaching the current limit

threshold set by R

. If the design goal is to use a minimum inductance value, let

= 2(I

L(avg)

). This will

proportionally reduce converter output current capability.
Maximum output switch frequency.
Desired peak-to-peak output ripple voltage. For best performance the ripple voltage should be kept to a low value
since it will directly affect line and load regulation. Capacitor C

should be a low equivalent series resistance (ESR)

electrolytic designed for switching regulator applications.

The following Converter Characteristics must be chosen:

NOTES: 1. V

sat

- Saturation voltage of the output switch, refer to Figures 10 and 11.

NOTES:

2. V

- Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V.

NOTES:

3. The calculated t

off

must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum

NOTES: 3.

operating input voltage.

Figure 22. Design Equations

NCP3163

http://onsemi.com

LVI

+
+
-

Current

Limit

(Bottom View)

+
+
-

0.25 V

1.125 V

15 k

1.25 V

45 k

Feedback
Comparator

out

-
+

Thermal

Oscillator

Latch

2.0 mA

7.0 V

Figure 23. Typical Buck Application Schematic

Value of Components

Name

Value

2 A, 40 V Schottky Rectifier

F, 35 V

out

100

F, 10 V

270 pF

10%

15 k

Name

Value

15 k

24.9 k

80 m

, 1 W

4.7 nF

200

Test Results for V

out

= 3.3 V

Test

Condition

Results

Line Regulation

= 8.0 V to 24 V, I

out

= 2.5 A

13 mV

Load Regulation

= 12 V, I

out

= 0 to 2.5 A

25 mV

Output Ripple

= 12 V, I

out

= 0 to 2.5 A

100 mVpp

Efficiency

= 12 V, I

out

= 2.5 A

70.3%

Short Circuit Current

= 12 V, R

= 0.1

3.1 A

Test Results for V

out

= 5.05 V

Test

Condition

Results

Line Regulation

= 10.2 V to 24 V, I

out

= 2.5 A

54 mV

Load Regulation

= 12 V, I

out

= 0 to 2.5 A

28 mV

Output Ripple

= 12 V, I

out

= 0 to 2.5 A

150 mVpp

Efficiency

= 12 V, I

out

= 2.5 A

75.5%

Short Circuit Current

= 12 V, R

= 0.1

3.1 A

NCP3163

http://onsemi.com

LVI

+
+
-

Current

Limit

(Bottom View)

+
+
-

0.25 V

1.125 V

15 k

1.25 V

45 k

Feedback
Comparator

out

-
+

Thermal

Oscillator

Latch

2.0 mA

7.0 V

Figure 26. Typical Boost Application Schematic

Value of Components for V

out

= 24 V

Name

Value

2 A, 40 V Schottky Rectifier

330

F, 35 V

270 pF

10%

15 k

Name

Value

42.2 k

2.32 k

out

330

F, 25 V

80 m

, 1 W

Test Results for V

out

= 24 V

Test

Condition

Results

Line Regulation

= 10 V to 20 V, I

out

= 700 mA

90 mV

Load Regulation

= 12 V, I

out

= 0 to 700 mA

80 mV

Output Ripple

= 12 V, I

out

= 0 to 700 mA

300 mVpp

Efficiency

= 12 V, I

out

= 700 mA

83%

Short Circuit Current

= 12 V, R

= 0.1

3.1 A

NCP3163

http://onsemi.com

LVI

+
+
-

Current

Limit

(Bottom View)

+
+
-

0.25 V

1.125 V

15 k

1.25 V

45 k

Feedback
Comparator

out

-
+

Thermal

Oscillator

Latch

2.0 mA

7.0 V

Figure 29. Typical Voltage Inverting Application Schematic

Value of Components for V

out

= -15 V

Name

Value

2 A, 40 V Schottky Rectifier

270

F, 16 V

out

2 X 270

F, 16 V

150 pF

10%

Name

Value

1.07 k

11.8 k

80 m

, 1 W

4.7 nF

200 m

Test Results for V

out

= -15 V

Test

Condition

Results

Line Regulation

= 7.0 V to 16 V, I

out

= 500 mA

35 mV

Load Regulation

= 12 V, I

out

= 0 to 500 mA

20 mV

Output Ripple

= 12 V, I

out

= 0 to 500 mA

100 mVpp

Efficiency

= 12 V, I

out

= 500 mA

68%

Short Circuit Current

= 12 V, R

= 0.1

3.1 A

NCP3163

http://onsemi.com

PACKAGE DIMENSIONS

SOIC 16 LEAD WIDE BODY, EXPOSED PAD

PW SUFFIX

CASE 751AG-01

ISSUE O

-W-

-U-

0.25 (0.010)

-T-

SEATING
PLANE

16 PL

0.25 (0.010)

DETAIL E

R x 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.

6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.

14 PL

PIN 1 I.D.

TOP SIDE

0.10 (0.004) T

EXPOSED PAD

BACK SIDE

DIM

MIN

MAX

MIN

MAX

INCHES

10.15

10.45

0.400

0.411

MILLIMETERS

7.40

7.60

0.292

0.299

2.35

2.65

0.093

0.104

0.35

0.49

0.014

0.019

0.50

0.90

0.020

0.035

1.27 BSC

0.050 BSC

3.31

3.51

0.130

0.138

0.25

0.32

0.010

0.012

0.00

0.10

0.000

0.004

4.58

4.78

0.180

0.188

10.05

10.55

0.395

0.415

0.25

0.75

0.010

0.029

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.350

0.175

0.050

0.376

0.188

0.200

0.074

DIMENSIONS: MILLIMETERS

0.024

0.145

Exposed
Pad

NCP3163

http://onsemi.com

PACKAGE DIMENSIONS

18-LEAD DFN, 5 x 6 mm

MN SUFFIX

CASE 505-01

ISSUE B

0.15

18X

NOTES:

1. DIMENSIONS AND TOLERANCING PER

ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

DIM

MIN

MAX

MILLIMETERS

0.80

1.00

0.00

0.05

0.20 REF

0.18

0.30

6.00 BSC

3.98

4.28

5.00 BSC

2.98

3.28

0.50 BSC

0.20

---

0.45

0.65

0.15

PIN 1 LOCATION

(A3)

SEATING

PLANE

0.08

0.10

18X

0.10

0.05 C

NOTE 3

18X

SIDE VIEW

TOP VIEW

BOTTOM VIEW

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800-282-9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81-3-5773-3850

NCP3163/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local
Sales Representative

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NCP3163PWG

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: NCP3163PWG