Semiconductor Components Industries, LLC, 2004
May, 2004 - Rev. 10
1
Publication Order Number:
NCP3418/D
NCP3418, NCP3418A
Dual Bootstrapped 12 V
MOSFET Driver with
Output Disable
The NCP3418 and NCP3418A are dual MOSFET gate drivers
optimized to drive the gates of both high-side and low-side power
MOSFETs in a synchronous buck converter. Each of the drivers is
capable of driving a 3000 pF load with a 25 ns propagation delay and a
20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal,
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418A is identical to the NCP3418 except that there is no
internal charge pump diode.
The NCP3418 is pin-to-pin compatible with Analog Devices
ADP3418 with the following advantages:
Faster Rise and Fall Times
Internal Charge Pump Diode Reduces Cost and Parts Count
Thermal Shutdown for System Protection
Integrated OVP
Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
Features
Anti Cross-Conduction Protection Circuitry
Floating Top Driver Accommodates Boost Voltages of up to 30 V
One Input Signal Controls Both the Upper and Lower Gate Outputs
Output Disable Control Turns Off Both MOSFETs
Complies with VRM 10.x Specifications
Undervoltage Lockout
Thermal Shutdown
Thermally Enhanced Package Available
Device
Package
Shipping
ORDERING INFORMATION
SO-8
98 Units/Rail
SO-8
2500 Tape & Reel
NCP3418D
NCP3418DR2
A = Assembly Location
L
= Wafer Lot
Y = Year
W = Work Week
MARKING
DIAGRAMS
PIN CONNECTIONS
SO-8
D SUFFIX
CASE 751
1
3418
ALYW
8
1
8
DRVL
V
CC
1
8
PGND
OD
SW
IN
DRVH
BST
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1
3418A
ALYW
8
SO-8
2500 Tape & Reel
NCP3418ADR2
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
SO-8
2500 Tape & Reel
NCP3418ADR2G
SO-8 EP
PD SUFFIX
CASE 751AC
SO-8 EP
98 Units/Rail
NCP3418PD
SO-8 EP 2500 Tape & Reel
NCP3418PDR2
SO-8 EP 2500 Tape & Reel
NCP3418APDR2
1
8
3418A
ALYW
1
8
3418
ALYW
1
8
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Figure 1. NCP3418/A Block Diagram
100 k
8
1
4
7
+
-
1.5 V
Nonoverlap
120 k
5
6
+
-
4 V
2
3
V
CC
DRVH
BST
SW
DRVL
PGND
OD
IN
Not present in
the NCP3418A
PIN DESCRIPTION
Pin
Symbol
Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this
bootstrap voltage for the high-side MOSFET as it is switched. The recommended capacitor value is between
100 nF and 1.0
m
F. An external diode will be needed with the NCP3418A.
2
IN
Logic-Level Input. This pin has primary control of the drive outputs.
3
OD
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
4
V
CC
Input Supply. A 1.0
m
F ceramic capacitor should be connected from this pin to PGND.
5
DRVL
Output drive for the lower MOSFET.
6
PGND
Power Ground. Should be closely connected to the source of the lower MOSFET.
7
SW
Switch Node. Connect to the source of the upper MOSFET.
8
DRVH
Output drive for the upper MOSFET.
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3
MAXIMUM RATINGS*
Rating
Value
Unit
Operating Ambient Temperature, T
A
0 to 85
C
Operating Junction Temperature, T
J
(Note 1)
0 to 150
C
Package Thermal Resistance: SO-8
Junction-to-Case, R
q
JC
Junction-to-Ambient, R
q
JA
(2-Layer Board)
45
123
C/W
C/W
Package Thermal Resistance: SO-8 EP
Junction-to-Ambient, R
q
JA
(Note 2)
50
C/W
Storage Temperature Range, T
S
-65 to 150
C
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
Standard (Note 3)
Lead Free (Note 4)
240 peak
260 peak
C
JEDEC Moisture Sensitivity Level
SO-8 (240 peak profile)
SO-8 (260 peak profile)
SO-8 EP (240 peak profile)
SO-8 EP (260 peak profile)
1
1
1
3
-
1. Internally limited by thermal shutdown, 150
C min.
2. Rating applies when soldered to an appropriate thermal area on the PCB.
3. 60 - 180 seconds minimum above 183
C.
4. 60 - 180 seconds minimum above 237
C.
*The maximum package power dissipation must be observed.
NOTE:
This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol
Pin Name
V
MAX
V
MIN
V
CC
Main Supply Voltage Input
15 V
-0.3 V
BST
Bootstrap Supply Voltage Input
30 V wrt/PGND
35 V
v
50 ns wrt/PGND
15 V wrt/SW
-0.3 V wrt/SW
SW
Switching Node
(Bootstrap Supply Return)
30 V
-1.0 V DC
-10 V< 200 ns
DRVH
High-Side Driver Output
BST + 0.3 V
35 V
v
50 ns wrt/PGND
15 V wrt/SW
-0.3 V wrt/SW
DRVL
Low-Side Driver Output
V
CC
+ 0.3 V
-0.3 V DC
-2.0 V < 200 ns
IN
DRVH and DRVL Control Input
V
CC
+ 0.3 V
-0.3 V
OD
Output Disable
V
CC
+ 0.3 V
-0.3 V
PGND
Ground
0 V
0 V
NOTE:
All voltages are with respect to PGND except where noted.
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NCP3418-SPECIFICATIONS
(Note 5)
(V
CC
= 12 V, T
A
= 0
C to +85
C, T
J
= 0
C to +125
C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Supply
Supply Voltage Range
V
CC
-
4.6
-
13.2
V
Supply Current
I
SYS
BST = 12 V, IN = 0 V
-
2.0
6.0
mA
OD Input
Input Voltage High
-
-
2.0
-
-
V
Input Voltage Low
-
-
-
-
0.8
V
Input Current
-
-
-1.0
-
+1.0
m
A
Propagation Delay Time (Note 6)
t
pdlOD
t
pdhOD
See Figure 2
-
-
40
40
60
60
ns
ns
PWM Input
Input Voltage High
-
-
2.0
-
-
V
Input Voltage Low
-
-
-
-
0.8
V
Input Current
-
-
-1.0
-
+1.0
m
A
High-Side Driver
Output Resistance, Sourcing Current
-
V
BST
- V
SW
= 12 V (Note 8)
-
1.8
3.0
W
Output Resistance, Sinking Current
-
V
BST
- V
SW
= 12 V (Note 8)
-
1.0
2.5
W
Transition Times (Note 6)
t
rDRVH
t
fDRVH
V
BST
- V
SW
= 12 V, C
LOAD
= 3.0 nF,
See Figure 3
-
-
18
10
25
15
ns
ns
Propagation Delay (Notes 6 & 7)
t
pdhDRVH
t
pdlDRVH
V
BST
- V
SW
= 12 V
-
-
30
25
60
45
ns
ns
Low-Side Driver
Output Resistance, Sourcing Current
-
V
CC
= 12 V (Note 8)
-
1.8
3.0
W
Output Resistance, Sinking Current
-
V
CC
- V
SW
= 12 V (Note 8)
-
1.0
2.5
W
Transition Times
t
rDRVL
t
fDRVL
C
LOAD
= 3.0 nF, See Figure 3
-
-
16
11
25
15
ns
ns
Propagation Delay
t
pdhDRVL
t
pdlDRVL
See Figure 3
-
-
30
20
60
30
ns
ns
Undervoltage Lockout
UVLO
-
-
3.9
4.3
4.6
V
Hysteresis
-
(Note 8)
0.5
V
Thermal Shutdown
Over Temperature Protection
-
(Note 8)
150
170
C
Hysteresis
(Note 8)
20
C
5. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
6. AC specifications are guaranteed by characterization, but not production tested.
7. For propagation delays, "t
pdh
'' refers to the specified signal going high; "t
pdl
'' refers to it going low.
8. GBD: Guaranteed by design; not tested in production.
Specifications subject to change without notice.
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5
Figure 2. Output Disable Timing Diagram
DRVH
or
DRVL
OD
t
pdlOD
90%
t
pdhOD
10%
Figure 3. Nonoverlap Timing Diagram (timing is referenced to the 90% and 10% points unless otherwise noted)
t
fDRVH
t
rDRVL
t
pdlDRVH
t
fDRVL
t
pdlDRVL
t
pdhDRVH
t
rDRVH
4 V
t
pdhDRVL
DRVH-SW
SW
DRVL
IN
10%
10%
90%
10%
1.5 V
10%
90%
90%
90%
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6
APPLICATIONS INFORMATION
Figure 4. DRVH Rise and DRVL Fall Times
Figure 5. DRVH Fall and DRVL Rise Times
IN
DRVL
DRVH
IN
DRVL
DRVH
SUPPL
Y CURRENT (mA)
F
ALL TIME (ns)
0
60
IN FREQUENCY (kHz)
50
40
30
10
200
400
600
800
1000
1200
20
0
15
1
40
LOAD CAPACITANCE (nF)
30
5
20
0
10
2
3
4
5
0
1
2
3
4
5
LOAD CAPACITANCE (nF)
10
Figure 6. Rise Time vs. Load Capacitance
Figure 7. Fall Time vs. Load Capacitance
Figure 8. V
CC
Supply Current vs. IN Frequency
trTG
T
A
= 25
C
V
CC
= 12 V
C
load
= 3.3 nF
I
CC
RISE TIME (ns)
trBG
trTG
trBG
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APPLICATIONS INFORMATION
Theory of Operation
The NCP3418 and NCP3418A are single phase MOSFET
drivers optimized for driving two N-channel MOSFETs in
a synchronous buck converter topology. The NCP3418
features an internal diode, while the NCP3418A requires an
external BST diode for the floating top gate driver. A single
PWM input signal is all that is required to properly drive the
high-side and the low-side MOSFETs. Each driver is
capable of driving a 3.3 nF load at frequencies up to 500 kHz.
Low-Side Driver
The low-side driver is designed to drive a
ground-referenced low R
DS(on)
N-Channel MOSFET. The
voltage rail for the low-side driver is internally connected to
the V
CC
supply and PGND.
When the NCP3418 is enabled, the low-side driver's
output is 180
_ out of phase with the PWM input. When the
device is disabled, the low-side gate is held low.
High-Side Driver
The high-side driver is designed to drive a floating low
R
DS(on)
N-channel MOSFET. The bias voltage for the high
side driver is developed by a bootstrap circuit referenced to
SW. The bootstrap capacitor should be connected between
the BST and SW pins.
The bootstrap circuit comprises an internal or external
diode, D1 (in which the anode is connected to V
CC
), and an
external bootstrap capacitor, C
BST
. When the NCP3418 is
starting up, the SW pin is at ground, so the bootstrap capacitor
will charge up to V
CC
through D1. When the PWM input goes
high, the high-side driver will begin to turn on the high-side
MOSFET by pulling charge out of C
BST
. As the high-side
MOSFET turns on, the SW pin will rise to V
IN
, forcing the
BST pin to V
IN
+ V
CC
, which is enough gate-to-source
voltage to hold the MOSFET on. To complete the cycle, the
high-side MOSFET is switched off by pulling the gate down
to the voltage at the SW pin. When low-side MOSFET turns
on, the SW pin is held at ground. This allows the bootstrap
capacitor to charge up to V
CC
again.
The high-side driver's output is in phase with the PWM input.
When the device is disabled, the high side gate is held low.
Safety Timer and Overlap Protection Circuit
The overlap protection circuit prevents both the high-side
MOSFET and the low-side MOSFET from being on at the
same time, and minimizes the associated off times. This will
reduce power losses in the switching elements. The overlap
protection circuit accomplishes this by controlling the delay
from turning off the high-side MOSFET to turning on the
low-side MOSFET.
To prevent cross conduction during the high-side
MOSFET's turn-off and the low-side MOSFET's turn-on,
the overlap circuit monitors the voltage at the SW pin. When
the PWM input signal goes low, DRVH will go low after a
propagation delay (t
pdlDRVH
), turning the high-side
MOSFET off. However, before the low-side MOSFET can
turn on, the overlap protection circuit waits for the voltage at
the SW pin to fall below 4.0 V. Once SW falls below the 4.0 V
threshold, DRVL will go high after a propagation delay
(t
pdhDRVL
), turning the low-side MOSFET on. However, if
SW does not fall below 4.0 V in 300 ns, the safety timer
circuit will override the normal control scheme and drive
DRVL high. This will help insure that if the high-side
MOSFET fails to turn off it will not produce an over-voltage
at the output.
Similarly, to prevent cross conduction during the
low-side MOSFET's turn-off and the high-side
MOSFET's
turn-on, the overlap circuit monitors the voltage
at the gate of the low-side MOSFET through the DRVL pin.
When the PWM signal goes high, DRVL will go low after
a propagation delay (t
pdlDRVL
), turning the low-side
MOSFET off. However, before the high-side MOSFET can
turn on, the overlap protection circuit waits for the voltage
at DRVL to drop below 1.5 V. Once this has occurred, DRVH
will go high after a propagation delay (t
pdhDRVH
), turning
the high-side MOSFET on.
Application Information
Supply Capacitor Selection
For the supply input (V
CC
) of the NCP3418, a local bypass
capacitor is recommended to reduce noise and supply peak
currents during operation. Use a 1.0 to 4.7
mF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors
provide the best combination of low ESR and small size.
Keep the ceramic capacitor as close as possible to the V
CC
and PGND pins.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C
BST
) and the internal (or an external) diode. Selection of
these components can be done after the high-side MOSFET
has been chosen.
The bootstrap capacitor must have a voltage rating that is
able to withstand twice the maximum supply voltage. A
minimum 50 V rating is recommended. The capacitance is
determined using the following equation:
CBST
+
QGATE
D
VBST
(eq. 1)
where Q
GATE
is the total gate charge of the high-side
MOSFET, and
DV
BST
is the voltage droop allowed on the
high-side MOSFET drive. For example, a NTD60N03 has
a total gate charge of about 30 nC. For an allowed droop of
300 mV, the required bootstrap capacitance is 100 nF. A
good quality ceramic capacitor should be used.
If an external Schottky diode will be used for bootstrap,
it must be rated to withstand the maximum supply voltage
plus any peak ringing voltages that may be present on SW.
The average forward current can be estimated by:
IF(AVG)
+
QGATE
fMAX
(eq. 2)
where f
MAX
is the maximum switching frequency of the
controller. The peak surge current rating should be checked
in-circuit, since this is dependent on the source impedance
of the 12 V supply and the ESR of C
BST.
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8
PACKAGE DIMENSIONS
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
SOLDERING FOOTPRINT
SOIC-8
D SUFFIX
CASE 751-07
ISSUE AB
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PACKAGE DIMENSIONS
SOIC-8 EP
PD SUFFIX
CASE 751AC-01
ISSUE O
H
C
0.10
D
E1
A
D
PIN ONE LOCATION
2 X
8 X
SEATING
PLANE
EXPOSED
GAUGE
PLANE
1
4
5
8
D
C
0.10
A-B
2 X
E
B
e
C
0.10
2 X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
DETAIL A
END VIEW
SECTION A-A
8 X
b
A-B
0.25
D
C
C
C
0.10
C
0.20
A
A2
G
F
1
4
5
8
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS (ANGLES
IN DEGREES).
3. DIMENSION b DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE
0.08 MM TOTAL IN EXCESS OF THE "b"
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
4. DATUMS A AND B TO BE DETERMINED
AT DATUM PLANE H.
DIM
MIN
MAX
MILLIMETERS
A
1.35
1.75
A1
0.00
0.10
A2
1.35
1.65
b
0.31
0.51
b1
0.28
0.48
c
0.17
0.25
c1
0.17
0.23
D
4.90 BSC
E
6.00 BSC
e
1.27 BSC
L
0.40
1.27
L1
1.04 REF
F
2.24
3.20
G
1.55
2.51
h
0.25
0.50
q
0
8
h
A
A
DETAIL A
(b)
b1
c
c1
0.25
L
(L1)
q
PAD
E1
3.90 BSC
_
_
A1
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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NCP3418/D
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