Semiconductor Components Industries, LLC, 2005

March, 2005 - Rev. P7

Publication Order Number:

NCV7356/D

NCV7356

Advance Information

Single Wire CAN Transceiver

The NCV7356 is a physical layer device for a single wire data link

capable of operating with various Carrier Sense Multiple Access
with Collision Resolution (CSMA/CR) protocols such as the Bosch
Controller Area Network (CAN) version 2.0. This serial data link
network is intended for use in applications where high data rate is not
required and a lower data rate can achieve cost reductions in both the
physical media components and in the microprocessor and/or
dedicated logic devices which use the network.

The network shall be able to operate in either the normal data rate

mode or a high-speed data download mode for assembly line and
service data transfer operations. The high-speed mode is only
intended to be operational when the bus is attached to an off-board
service node. This node shall provide temporary bus electrical loads
which facilitate higher speed operation. Such temporary loads should
be removed when not performing download operations.

The bit rate for normal communications is typically 33 kbit/s, for

high-speed transmissions like described above a typical bit rate of
83 kbit/s is recommended. The NCV7356 is designed in accordance
to the Single Wire CAN Physical Layer Specification GMW3089
V2.4 and supports many additional features like undervoltage
lockout, timeout for faulty blocked input signals, output blanking
time in case of bus ringing and a very low sleep mode current.

Features

Fully Compatible with J2411 Single Wire CAN Specification

mA (max) Sleep Mode Current

Operating Voltage Range 5.0 to 27 V

Up to 100 kbps High-Speed Transmission Mode

Up to 40 kbps Bus Speed

Selective BUS Wake-Up

Logic Inputs Compatible with 3.3 V and 5 V Supply Systems

Control Pin for External Voltage Regulators (14 Pin Package Only)

Standby to Sleep Mode Timeout

Low RFI Due to Output Wave Shaping

Fully Integrated Receiver Filter

Bus Terminals Short-Circuit and Transient Proof

Loss of Ground Protection

Protection Against Load Dump, Jump Start

Thermal Overload and Short Circuit Protection

ESD Protection of 4.0 kV on CAN Pin (2.0 kV on Any Other Pin)

Undervoltage Lock Out

Bus Dominant Timeout Feature

NCV Prefix for Automotive and Other Applications Requiring Site

and Change Control

Pb-Free Package is Available

This document contains information on a new product. Specifications and information
herein are subject to change without notice.

SOIC-14

D SUFFIX

CASE 751A

PIN CONNECTIONS

Device

Package

Shipping

ORDERING INFORMATION

NCV7356D1G

SOIC-8

98 Units / Rail

http://onsemi.com

MARKING DIAGRAMS

NCV7356

AWLYWW

(Top View)

TxD

MODE1

CANH

MODE0

RxD

BAT

LOAD

GND

INH

GND

NCV7356D1RG

SOIC-8

2500 Tape & Reel

For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

NCV7356D2

SOIC-14

55 Units / Rail

NCV7356D2R2

SOIC-14

2500 Tape & Reel

SOIC-8

D SUFFIX

CASE 751

V7356

ALYW

= Assembly Location

WL, L

= Wafer Lot

YY, Y

= Year

WW, W = Work Week

= Pb-Free Package

TxD

8 GND

MODE0

MODE1

RxD

7 CANH

6 LOAD

5 V

BAT

(Top View)

NCV7356

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Electrical Specification

All voltages are referenced to ground (GND). Positive

currents flow into the IC. The maximum ratings given in
the table below are limiting values that do not lead to a

permanent damage of the device but exceeding any of these
limits may do so. Long term exposure to limiting values
may affect the reliability of the device.

MAXIMUM RATINGS

Rating

Symbol

Condition

Min

Max

Unit

Supply Voltage, Normal Operation

BAT

-0.3

Short-Term Supply Voltage, Transient

BAT.LD

Load Dump; t < 500 ms

(peak)

Jump Start; t < 1.0 min

Transient Supply Voltage

BAT.TR1

ISO 7637/1 Pulse 1 (Note 2)

-50

Transient Supply Voltage

BAT.TR2

ISO 7637/1 Pulses 2 (Note 2)

100

Transient Supply Voltage

BAT.TR3

ISO 7637/1 Pulses 3A, 3B

-200

200

CANH Voltage

CANH

BAT

< 27 V

-20

BAT

= 0 V

-40

Transient Bus Voltage

CANHTR1

ISO 7637/1 Pulse 1 (Note 3)

-50

Transient Bus Voltage

CANHTR2

ISO 7637/1 Pulses 2 (Note 3)

100

Transient Bus Voltage

CANHTR3

ISO 7637/1 Pulses 3A, 3B (Note 3)

-200

200

DC Voltage on Pin LOAD

LOAD

Via RT > 2.0 k

-40

DC Voltage on Pins TxD, MODE1, MODE0, RxD

-0.3

7.0

ESD Capability of CANH

ESDBUS

Human Body Model
Eq. to Discharge 100 pF with 1.5 k

-4000

4000

ESD Capability of Any Other Pins

ESD

Human Body Model
Eq. to Discharge 100 pF with 1.5 k

-2000

2000

Maximum Latchup Free Current at Any Pin

LATCH

-500

500

Storage Temperature

STG

-55

150

Junction Temperature

-40

150

Lead Temperature Soldering

Reflo

(SMD st les onl )

SOIC-14

sld

60 s - 150 s above 183

240 peak

Reflow: (SMD styles only)

SOIC-8

60 s - 150 s above 217

260 peak

Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values
(not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage
may occur and reliability may be affected.
2. ISO 7637 test pulses are applied to V

BAT

via a reverse polarity diode and >1.0

F blocking capacitor.

3. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF.
4. ESD measured per Q100-002 (EIA/JESD22-A114-A).

TYPICAL THERMAL CHARACTERISTICS

Test Condition, Typical Value

Parameter

Min Pad Board

Pad Board

Unit

SOIC-8

Junction-to-Lead (psi-JL8,

JL8

)

35 (Note 5)

37 (Note 6)

C/W

Junction-to-Ambient (R

)

172 (Note 5)

115 (Note 6)

C/W

SOIC-14

Junction-to-Lead (psi-JL8,

JL8

)

30 (Note 7)

30 (Note 8)

C/W

Junction-to-Ambient (R

)

122 (Note 7)

84 (Note 8)

C/W

5. 1 oz copper, 53 mm

coper area, 0.062

thick FR4.

6. 1 oz copper, 716 mm

coper area, 0.062

thick FR4.

7. 1 oz copper, 94 mm

coper area, 0.062

thick FR4.

8. 1 oz copper, 767 mm

coper area, 0.062

thick FR4.

NCV7356

http://onsemi.com

ELECTRICAL CHARACTERISTICS

BAT

= 5.0 to 27 V, T

= -40 to +125

C, unless otherwise specified.)

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

GENERAL

Undervoltage Lock Out

BATuv

3.5

4.8

Supply Current, Recessive,

All Acti e Modes

BATN

BAT

= 18 V,

T D Open

Not High Speed Mode

5.0

6.0

All Active Modes

TxD Open

High Speed Mode

8.0

Normal Mode Supply Current,

Dominant

BATN

(Note 9)

BAT

= 27 V, MODE0 = MODE1 = H,

TxD = L, R

load

= 200

High-Speed Mode Supply Current,

Dominant

BATN

(Note 9)

BAT

= 16 V, MODE0 = H, MODE1 = L,

TxD = L, R

load

= 75

Wake-Up Mode Supply Current,

Dominant

BATW

(Note 9)

BAT

= 27 V, MODE0 = L, MODE1 = H,

TxD = L, R

load

= 200

Sleep Mode Supply Current

BATS

BAT

= 18 V, TxD, RxD, MODE0,

MODE1 Open

Thermal Shutdown (Note 9)

155

180

Thermal Recovery (Note 9)

REC

126

150

CANH

Bus Output Voltage

> 200

, Normal Mode

6.0 V < V

BAT

< 27 V

4.4

5.1

Bus Output Voltage

Low Battery

> 200

, Normal High-Speed Mode

5.0 V < V

BAT

< 6.0 V

3.4

5.1

Bus Output Voltage

High-Speed Mode

> 75

, High-Speed Mode

8.0 V < V

BAT

< 16 V

4.2

5.1

Fixed Wake-Up

Output High Voltage

ohWuFix

Wake-Up Mode, R

> 200

11.4 V < V

BAT

< 27 V

9.9

12.5

Offset Wake-Up

Output High Voltage

ohWuOffset

Wake-Up Mode, R

> 200

5.0 V < V

BAT

< 11.4 V

BAT

1.5

BAT

Recessive State

Output Voltage

Recessive State or Sleep Mode,

load

= 6.5 k

-0.20

0.20

Bus Short Circuit Current

-I

CAN_SHORT

CANH

= 0 V, V

BAT

= 27 V, TxD = 0 V

350

Bus Leakage Current

During Loss of Ground

LKN_CAN

(Note 10)

Loss of Ground, V

CANH

= 0 V

-50

Bus Leakage Current, Bus Positive

LKP_CAN

TxD High

-10

Bus Input Threshold

Normal, High-Speed Mode,

6.0

BAT

27 V

2.0

2.1

2.2

Bus Input Threshold Low Battery

ihlb

Normal, V

BAT

= 5.0 V to 6.0 V

1.6

1.7

2.2

Fixed Wake-Up

Input High Voltage Threshold

ihWuFix

(Note 9)

Sleep Mode, V

BAT

> 10.9 V

6.6

7.9

Offset Wake-Up

Input High Voltage Threshold

ihWuOffset

(Note 9)

Sleep Mode

BAT

-4.3

BAT

-3.25

LOAD

Voltage on Switched Ground Pin

LOAD_1mA

LOAD

= 1.0 mA

0.1

Voltage on Switched Ground Pin

LOAD

= 5.0 mA

0.5

Voltage on Switched Ground Pin

LOAD_LOB

LOAD

= 7.0 mA, V

BAT

= 0 V

1.0

Load Resistance During Loss of

Battery

LOAD_LOB

BAT

= 0

LOAD

-10%

LOAD

+35%

9. Thresholds not tested in production, guaranteed by design.
10. Leakage current in case of loss of ground is the summary of both currents I

LKN_CAN

and

LKN_LOAD

NCV7356

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ELECTRICAL CHARACTERISTICS

(continued) (V

BAT

= 5.0 to 27 V, T

= -40 to +125

C, unless otherwise specified.)

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

TXD, MODE0, MODE1

High Level Input Voltage

5.0 < V

BAT

< 27 V

2.0

Low Level Input Voltage

5.0 < V

BAT

< 27 V

0.8

TxD Pullup Current

-I

IL_TXD

TxD = L, MODE0 and 1 = H

5.0 < V

BAT

< 27 V

MODE0 and 1 Pulldown Resistor

MODE_pd

RXD

Low Level Output Voltage

ol_rxd

RxD

= 2.0 mA

0.4

High Level Output Leakage

ih_rxd

RxD

= 5.0 V

-10

RxD Output Current

Irxd

RxD

= 5.0 V

INH (14 Pin Package Only)

High Level Output Voltage

oh_INH

INH

= -180

BAT

-0.8

BAT

-0.5

BAT

Leakage Current

INH_lk

MODE0 = MODE1 = L, INH = 0 V

-5.0

5.0

NCV7356

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TIMING MEASUREMENT LOAD CONDITIONS

Normal and High Voltage Wake-Up Mode

High-Speed Mode

min load / min tau

3.3 kohm / 540 pF

Additional 140 ohm tool resistance

to ground in parallel

min load / max tau

3.3 kohm / 1.2 nF

to ground in parallel

max load / min tau

200 ohm / 5.0 nF

Additional 120 ohm tool resistance

to ground in parallel

max load / max tau

200 ohm / 20 nF

to ground in parallel

ELECTRICAL CHARACTERISTICS

(5.0 V

BAT

27 V, -40

125

C, unless otherwise specified.)

AC CHARACTERISTICS (See Figures 3, 4, and 5)

Characteristic

Symbol

Condition

Min

Typ

Max

Unit

Transmit Delay in Normal and Wake-Up

Mode, Bus Rising Edge (Note 11)

Min and Max Loads per Timing

Measurement Load Conditions

2.0

6.3

Transmit Delay in Wake-Up Mode to V

ihWU

Bus Rising Edge (Note 12)

TWUr

Min and Max Loads per Timing

Measurement Load Conditions

2.0

Transmit Delay in Normal Mode,

Bus Falling Edge (Note 13)

Min and Max Loads per Timing

Measurement Load Conditions

1.8

Transmit Delay in Wake-Up Mode,

Bus Falling Edge (Note 13)

TWU1f

Min and Max Loads per Timing

Measurement Load Conditions

3.0

13.7

Transmit Delay in High-Speed Mode,

Bus Rising Edge (Note 14)

THSr

Min and Max Loads per Timing

Measurement Load Conditions

0.1

1.5

Transmit Delay in High-Speed Mode,

Bus Falling Edge (Note 15)

THSf

Min and Max Loads per Timing

Measurement Load Conditions

0.04

3.0

Receive Delay, All Active Modes (Note 16)

CANH High to Low Transition

0.3

1.0

Receive Delay, All Active Modes (Note 16)

CANH Low to High Transition

0.3

1.0

Input Minimum Pulse Length,

All Active Modes (Note 16)

mpDR

mpRD

CANH High to Low Transition

CANH Low to High Transition

0.15
0.15

-
-

1.0
1.0

Wake-Up Filter Time Delay

WUF

See Figure 4

Receive Blanking Time

After

TxD L-H

Transition

See Figure 5

0.5

6.0

TxD Timeout Reaction Time

tout

Normal and High-Speed Mode

TxD Timeout Reaction Time

toutwu

Wake-Up Mode

Delay from Normal to High-Speed and

High Voltage Wake-Up Mode

dnhs

Delay from High-Speed and High Voltage

Wake-Up to Normal Mode

dhsn

Delay from Normal to Standby Mode

dsby

BAT

= 6.0 V to 27 V

500

Delay from Sleep to Normal Mode

dsnwu

BAT

= 6.0 V to 27 V

Delay from Standby to Sleep Mode (Note 17)

dsleep

BAT

= 6.0 V to 27 V

100

250

500

11. The maximum signal delay time for a bus rising edge is measured from V

cmos_il

on the TxD input pin to the V

ihMax

+ V

goff

max level on CANH

at maximum network time constant, minimum signal delay time for a bus rising edge is measured from V

cmos_ih

on the TxD input pin to 1 V

on CANH at minimum network time constant. These definitions are valid in both normal and High Voltage Wake-Up (HVWU) mode.

12. The maximum signal delay time for a bus rising edge in HVWU mode is measured from V

cmos_il

on the TxD input pin to the V

ihWuMax

+ V

goff

max level on CANH at maximum network time constant, minimum signal delay time for a bus rising edge is measured from V

cmos_ih

on the

TxD input pin to 1 V on CANH at minimum network time constant.

13. Maximum signal delay time for a bus falling edge is measured from V

cmos_ih

on the TxD input pin to 1 V on CANH at maximum network time

constant, minimum signal delay time for a bus falling edge is measured from V

cmos_ih

on the TxD input pin to the V

ihMax

+ V

goff

max level on

CANH. These definitions are valid in both normal and HVWU mode.

14. The signal delay time in high-speed mode for a bus rising edge is measured from V

cmos_il

on the TxD input pin to the V

ihMax

+ V

goff

max level

on CANH at maximum high-speed network time constant.

15. The signal delay time in high-speed mode for a bus falling edge is measured from V

cmos_ih

on the TxD input pin to 1 V on CANH at maximum

high-speed network time constant.

16. Receive delay time is measured from the rising / falling edge crossing of the nominal V

value on CANH to the falling (V

cmos_il_max

) / rising

cmos_ih_min

) edge of RxD. This parameter is tested by applying a square wave signal to CANH. The minimum slew rate for the bus rising

and falling edges is 50 V/

s. The low level on bus is always 0 V. For normal mode and high-speed mode testing the high level on bus is 4 V.

For HVWU mode testing the high level on bus is V

BAT

- 2 V.

17. Tested on 14 Pin package only.

NCV7356

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BUS LOADING REQUIREMENTS

Characteristic

Symbol

Min

Typ

Max

Unit

Number of System Nodes

Network Distance Between Any Two ECU Nodes

Bus Length

Node Series Inductor Resistance (If required)

ind

3.5

Ground Offset Voltage

goff

1.5

Ground Offset Voltage, Low Battery

gofflowbat

0.1 x V

BAT

0.7

Device Capacitance (Unit Load)

135

150

300

Network Total Capacitance

396

19000

Device Resistance (Unit Load)

6435

6490

6565

Device Resistance (Min Load)

min

2000

Network Total Resistance

200

4596

Network Time Constant (Note 18)

1.0

4.0

Network Time Constant in High-Speed Mode

1.5

High-Speed Mode Network Resistance to GND

load

135

18. The network time constant incorporates the bus wiring capacitance. The minimum value is selected to limit radiated emission. The maximum

value is selected to ensure proper communication modes. Not all combinations of R and C are possible.

TIMING DIAGRAMS

Figure 3. Input/Output Timing

max + V

goff

max

CANH

RxD

1 V

50%

TxD

50%

NCV7356

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FUNCTIONAL DESCRIPTION

TxD Input Pin

TxD Polarity

TxD = logic 1 (or floating) on this pin produces an
undriven or recessive bus state (low bus voltage)

TxD = logic 0 on this pin produces either a bus normal
or a bus high voltage dominant state depending on the
transceiver mode state (high bus voltage)

If the TxD pin is driven to a logic low state while the sleep

mode (Mode 0 = 0 and Mode 1 = 0) is activated, the
transceiver can not drive the CANH pin to the dominant
state.

The transceiver provides an internal pullup current on the

TxD pin which will cause the transmitter to default to the
bus recessive state when TxD is not driven.

TxD input signals are standard CMOS logic levels.

Timeout Feature

In case of a faulty blocked dominant TxD input signal,

the CANH output is switched off automatically after the
specified TxD timeout reaction time to prevent a dominant
bus.

The transmission is continued by next TxD L to H

transition without delay.

MODE0 and MODE1 Pins

The transceiver provides a weak internal pulldown

current on each of these pins which causes the transceiver
to default to sleep mode when they are not driven. The
mode input signals are standard CMOS logic level for
3.3 V and 5 V supply voltages.

MODE0

MODE1

Mode

Sleep Mode

High-Speed Mode

High Voltage Wake-Up

Normal Mode

Sleep Mode

Transceiver is in low power state, waiting for wake-up

via high voltage signal or by mode pins change to any state
other than 0,0. In this state, the CANH pin is not in the
dominant state regardless of the state of the TxD pin.

High-Speed Mode

This mode allows high-speed download with bit rates up

to 100 Kbit/s. The output wave shapingaping circuit is
disabled in this mode. Bus transmitter drive circuits for
those nodes which are required to communicate in
high-speed mode are able to drive reduced bus resistance
in this mode.

High Voltage Wake-Up Mode

This bus includes a selective node awake capability,

which allows normal communication to take place among
some nodes while leaving the other nodes in an undisturbed
sleep state. This is accomplished by controlling the signal
voltages such that all nodes must wake-up when they
receive a higher voltage message signal waveform. The
communication system communicates to the nodes
information as to which nodes are to stay operational
(awake) and which nodes are to put themselves into a non
communicating low power "sleep" state. Communication
at the lower, normal voltage levels shall not disturb the
sleeping nodes.

Normal Mode

Transmission bit rate in normal communication is

33 Kbits/s. In normal transmission mode the NCV7356
supports controlled waveform rise and overshoot times.
Waveform trailing edge control is required to assure that
high frequency components are minimized at the
beginning of the downward voltage slope. The remaining
fall time occurs after the bus is inactive with drivers off and
is determined by the RC time constant of the total bus load.

RxD Output Pin

Logic data as sensed on the single wire CAN bus.

RxD Polarity

RxD = logic 1 on this pin indicates a bus recessive
state (low bus voltage)

RxD = logic 0 on this pin indicates a bus normal or
high voltage bus dominant state

RxD in Sleep Mode

RxD does not pass signals to the microprocessor while in

sleep mode until a valid wake-up bus voltage level is
received or the MODE0 and MODE 1 pins are not 0, 0
respectively. When the valid wake-up bus voltage signal
awakens the transceiver, the RxD pin signals an interrupt
(logic 0). If there is no mode change within 250 ms (typ),
the transceiver re-enters the sleep mode.

When not in sleep mode all valid bus signals will be sent

out on the RxD pin.

RxD will be placed in the undriven or off state when in

sleep mode.

RxD Typical Load

Resistance: 2.7 k

Capacitance: < 25 pF

NCV7356

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Bus LOAD Pin
Resistor ground connection with internal open-on-loss-
of-ground protection

When the ECU experiences a loss of ground condition,

this pin is switched to a high impedance state.

The ground connection through this pin is not interrupted

in any transceiver operating mode including the sleep
mode. The ground connection only is interrupted when
there is a valid loss of ground condition.

This pin provides the bus load resistor with a path to

ground which contributes less than 0.1 V to the bus offset
voltage when sinking the maximum current through one
unit load resistor. This path exists in all operating modes,
including the sleep mode.

The transceiver's maximum bus leakage current

contribution to V

from the LOAD pin when in a loss of

ground state is 50

mA over all operating temperatures and

3.5 < V

BAT

< 27 V.

BAT

Input Pin

Vehicle Battery Voltage

The transceiver is fully operational as described in the

Electrical Characteristics Table over the range 6.0 V <
V

BAT

< 18 V as measured between the GND pin and the

BAT

pin.

For 5.0 V < V

Bat

< 6.0 V, the bus operates in normal

mode with reduced dominant output voltage and reduced
receiver input voltage. High voltage wake-up is not
possible (dominant output voltage is the same as in normal
or high-speed mode).

The transceiver operates in normal mode when 18 V <

Bat

< 27 V at 85

C for one minute.

For 0 < V

BAT

< 4.0 V, the bus is passive (not driven

dominant) and RxD is undriven (high), regardless of the
state of the TxD pin (undervoltage lockout).

CAN BUS

Input/Output Pin

Wave Shaping in Normal and High Voltage Wake-Up
Mode

Wave shaping is incorporated into the transmitter to

minimize EMI radiated emissions. An important
contributor to emissions is the rise and fall times during
output transitions at the "corners" of the voltage waveform.
The resultant waveform is one half of a sin wave of

frequency 50-65 kHz at the rising waveform edge and one
quarter of this sin wave at falling or trailing edge.

Wave Shaping in High-Speed Mode

Wave shaping control of the rising and falling waveform

edges are disabled during high-speed mode. EMI
emissions requirements are waived during this mode. The
waveform rise time in this mode is less than 1.0

ms.

Short Circuits

If the CAN BUS pin is shorted to ground for any duration

of time, the current is limited as specified in the Electrical
Characteristics Table until an overtemperature shutdown
circuit disables the output high side drive source transistor
preventing damage to the IC.

Loss of Ground

In case of a valid loss of ground condition, the LOAD pin

is switched into high impedance state. The CANH
transmission is continued until the undervoltage lock out
voltage threshold is detected.

Loss of Battery

In case of loss of battery (V

BAT

= 0 or open) the

transceiver does not disturb bus communication. The
maximum reverse current into the power supply system
(V

BAT

) doesn't exceed 500

mA.

INH Pin (14 pin package only)

The INH pin is a high-voltage highside switch used to

control the ECU's regulated microcontroller power supply.
After power-on, the transceiver automatically enters an
intermediate standby mode, the INH output will go high
(up to V

BAT

) turning on the external voltage regulator. The

external regulator provides power to the ECU. If there is no
mode change within 250 ms (typ), the transceiver re-enters
the sleep mode and the INH output goes to logic 0
(floating).

When the transceiver has detected a valid wake-up

condition (bus HVWU traffic which exceeds the wake-up
filter time delay) the INH output will become high (up to
V

BAT

) again and the same procedure starts as described

after power-on. In case of a mode change into any active
mode, the sleep timer is stopped and INH stays high (up to
V

BAT

). If the transceiver enters the sleep mode, INH goes

to logic 0 (floating) after 250 ms (typ) when no wake-up
signal is present.

NCV7356

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Table 1. SOIC-8 Thermal RC Network Models*

54 mm

714 mm

Copper Area

54 mm

714 mm

Copper Area

Cauer Network

Foster Network

C's

Units

Tau

Units

3.13E-05

W-s/C

1.00E-06

sec

1.23E-04

W-s/C

1.00E-05

sec

3.70E-04

W-s/C

1.00E-04

sec

1.28E-03

W-s/C

0.002

0.003

sec

4.55E-03

4.83E-03

W-s/C

0.038

0.041

sec

1.69E-02

1.75E-02

W-s/C

0.386

0.413

sec

5.86E-02

6.35E-02

W-s/C

2.21

2.29

sec

0.197

0.333

W-s/C

16.24

9.32

sec

1.50

2.81

W-s/C

54.81

68.9

sec

431

W-s/C

94.1

sec

R's

0.041

C/W

2.44E-02

C/W

0.093

C/W

5.28E-02

C/W

0.263

C/W

1.67E-01

C/W

1.868

1.976

C/W

1.0

1.1

C/W

8.332

8.627

C/W

4.7

4.8

C/W

23.944

24.484

C/W

12.9

13.4

C/W

37.864

33.670

C/W

26.2

26.7

C/W

71.762

23.952

C/W

55.6

36.7

C/W

28.053

21.501

C/W

71.4

27.6

C/W

0.212

C/W

4.2

C/W

*Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network

are computed by the square root of time constant R(t) = 24.4 * sqrt(time(sec)). The constant is derived based on the active area of the device
with silicon and epoxy at the interface of the heat generation.

The Cauer networks generally have physical

significance and may be divided between nodes to separate
thermal behavior due to one portion of the network from
another. The Foster networks, though when sorted by time
constant (as above) bear a rough correlation with the Cauer
networks, are really only convenient mathematical models.
Both Foster and Cauer networks can be easily implemented

using circuit simulating tools, whereas Foster networks
may be more easily implemented using mathematical tools
(for instance, in a spreadsheet program), according to the
following formula:

R(t)

Ri 1-e

-t taui

Junction

Ambient

(thermal ground)

Time constants are

not simple RC products.

Amplitudes of mathematical solution are

not the resistance values.

Figure 13. Grounded Capacitor Thermal Network ("Cauer" Ladder)

Figure 14. Non-Grounded Capacitor Thermal Ladder ("Foster" Ladder)

Junction

Ambient

(thermal ground)

Each rung is exactly characterized by its RC-product time constant; Am-

plitudes are the resistances

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SOIC-14 Thermal Information

Test Condition, Typical Value

Parameter

Min Pad Board

(Note 21)

Pad Board

(Note 22)

Unit

Junction-to-Lead (psi-JL8,

JL8

)

C/W

Junction-to-Ambient (R

)

122

C/W

21. 1 oz copper, 94 mm

coper area, 0.062

thick FR4.

22. 1 oz copper, 767 mm

coper area, 0.062

thick FR4.

Figure 17. Internal construction of the package

simulation.

Figure 18. Min pad is shown as the red traces.

1 inch pad includes the yellow area. Pin 1, 7, 8

and 14 are connected to flag internally to the

package and externally to the heat spreading area.

100

110

120

130

140

150

100

200

300

400

500

600

800

2.0 oz. Cu

(

C/W)

Copper Area (mm

)

1.0 oz. Cu

700

Figure 19. SOIC-14,

as a Function of the Pad Copper Area Including Traces,

Board Material

900

Sim 1.0 oz.
Sim 2.0 oz.

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Table 2. SOIC-8 Thermal RC Network Models*

96 mm

767 mm

Copper Area

96 mm

767 mm

Copper Area

Cauer Network

Foster Network

C's

Units

Tau

Units

3.12E-05

W-s/C

1.00E-06

sec

1.21E-04

W-s/C

1.00E-05

sec

3.53E-04

3.50E-04

W-s/C

1.00E-04

sec

1.19E-03

W-s/C

0.028

0.001

sec

4.86E-03

5.05E-03

W-s/C

0.001

0.009

sec

2.17E-02

7.16E-03

W-s/C

0.280

0.047

sec

8.94E-02

3.51E-02

W-s/C

2.016

0.875

sec

0.304

0.262

W-s/C

16.64

7.53

sec

1.71

2.43

W-s/C

59.47

68.4

sec

411

W-s/C

92.221

sec

R's

0.041

C/W

2.44E-02

C/W

0.095

0.096

C/W

5.28E-02

C/W

0.279

0.281

C/W

1.67E-01

C/W

1.154

0.995

C/W

3.5

0.7

C/W

5.621

6.351

C/W

0.7

0.1

C/W

13.180

1.910

C/W

8.7

5.8

C/W

23.823

21.397

C/W

15.9

16.4

C/W

53.332

27.150

C/W

31.9

27.1

C/W

24.794

25.276

C/W

61.3

29.0

C/W

0.218

C/W

4.3

C/W

*Bold face items in the Cauer network above, represent the package without the external thermal system. The Bold face items in the Foster network

The Cauer networks generally have physical

using circuit simulating tools, whereas Foster networks
may be more easily implemented using mathematical tools
(for instance, in a spreadsheet program), according to the
following formula:

R(t)

Ri 1-e

-t taui

Junction

Ambient

(thermal ground)

Time constants are

not simple RC products.

Amplitudes of mathematical solution are

not the resistance values.

Figure 20. Grounded Capacitor Thermal Network ("Cauer" Ladder)

Figure 21. Non-Grounded Capacitor Thermal Ladder ("Foster" Ladder)

Junction

Ambient

(thermal ground)

Each rung is exactly characterized by its RC-product time constant; Am-

plitudes are the resistances

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PACKAGE DIMENSIONS

SOIC-8

D SUFFIX

CASE 751-07

ISSUE AE

SEATING
PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751-01 THRU 751-06 ARE OBSOLETE. NEW

STANDARD IS 751-07.

0.10 (0.004)

DIM

MIN

MAX

MIN

MAX

INCHES

4.80

5.00

0.189

0.197

MILLIMETERS

3.80

4.00

0.150

0.157

1.35

1.75

0.053

0.069

0.33

0.51

0.013

0.020

1.27 BSC

0.050 BSC

0.10

0.25

0.004

0.010

0.19

0.25

0.007

0.010

0.40

1.27

0.016

0.050

0.25

0.50

0.010

0.020

5.80

6.20

0.228

0.244

-X-

-Y-

0.25 (0.010)

-Z-

0.25 (0.010)

1.52

0.060

7.0

0.275

0.6

0.024

1.270
0.050

4.0

0.155

inches

SCALE 6:1

*For additional information on our Pb-Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

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PACKAGE DIMENSIONS

SOIC-14

D SUFFIX

CASE 751A-03

ISSUE G

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

-A-

-B-

7 PL

0.25 (0.010)

-T-

X 45

SEATING
PLANE

14 PL

DIM

MIN

MAX

MIN

MAX

INCHES

MILLIMETERS

8.55

8.75

0.337

0.344

3.80

4.00

0.150

0.157

1.35

1.75

0.054

0.068

0.35

0.49

0.014

0.019

0.40

1.25

0.016

0.049

1.27 BSC

0.050 BSC

0.19

0.25

0.008

0.009

0.10

0.25

0.004

0.009

5.80

6.20

0.228

0.244

0.25

0.50

0.010

0.019

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
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or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
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