Semiconductor Components Industries, LLC, 2004
January, 2004 - Rev. 14
1
Publication Order Number:
NCV8503/D
NCV8503 Series
Micropower 400 mA LDO
Linear Regulators
with ENABLE, DELAY,
Adjustable RESET, and
General Use Comparator
The NCV8503 is a family of precision micropower voltage
regulators. Their output current capability is 400 mA. The family has
output voltage options for Adjustable, 2.5 V, 3.3 V and 5.0 V.
The output voltage is accurate within
2.0% with a maximum
dropout voltage of 0.6 V at 400 mA. Low quiescent current is a feature
drawing less than 1.0
A with ENABLE = 0 V. With ENABLE = 5.0 V,
the part only draws 200
A with 100
A load. This part is ideal for any
and all battery operated microprocessor equipment.
Microprocessor control logic includes an active RESET (with
DELAY).
The active RESET circuit operates correctly at an output voltage as
low as 1.0 V. The RESET function is activated during the power up
sequence or during normal operation if the output voltage drops below
the regulation limits.
The reset threshold voltage can be decreased by the connection of
external resistor divider to R
ADJ
lead.
The general use comparator (FLAG/Monitor) is referenced to a
temperature stable voltage and provides 1.0 mA of drive current at its
open collector output.
The regulator is protected against reverse battery, short circuit, and
thermal overload conditions. The device can withstand load dump
transients making it suitable for use in automotive environments. The
device has also been optimized for EMC conditions.
Features
Output Voltage Options: Adjustable, 2.5 V, 3.3 V, 5.0 V
2.0% Output
Low < 1.0
A Sleep Current
Low 200
A Quiescent Current
Fixed or Adjustable Output Voltage
Active RESET
Adjustable Reset
ENABLE
400 mA Output Current Capability
Fault Protection
+60 V Peak Transient Voltage
-15 V Reverse Voltage
Short Circuit
Thermal Overload
General Use Comparator
NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
x
= Voltage Ratings as Indicated Below:
A = Adjustable
2 = 2.5 V
3 = 3.3 V
5 = 5.0 V
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
SOIC 16 LEAD
WIDE BODY
EXPOSED PAD
PDW SUFFIX
CASE 751R
1
16
NCV8503x
AWLYYWW
1
16
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2
PIN CONNECTIONS
FIXED OUTPUT
R
ADJ
MON
1
16
DELAY
V
IN
NC
NC
NC
NC
GND
NC
ENABLE
NC
RESET
V
OUT
FLAG
V
ADJ
R
ADJ
MON
1
16
DELAY
V
IN
NC
NC
NC
NC
GND
NC
ENABLE
NC
RESET
V
OUT
FLAG
SENSE
ADJUSTABLE OUTPUT
V
OUT
GND
V
IN
NCV8503
33
F
5.1 k
R
RST
RESET
10
F
Microprocessor
DELAY
C
DELAY
V
BAT
V
DD
FLAG
Figure 1. Application Diagram
MON
R
FLG
5.1 k
V
ADJ
(Adjustable
Output Only)
I/O
I/O
ENABLE
SENSE
(Fixed Output Only)
Monitor
R
ADJ
(V
O
)
I
Q
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3
MAXIMUM RATINGS*
{
Rating
Value
Unit
V
IN
(DC)
-15 to 45
V
Peak Transient Voltage (46 V Load Dump @ V
IN
= 14 V)
60
V
Operating Voltage
45
V
V
OUT
(DC)
16
V
Voltage Range (RESET, FLAG, R
ADJ
, DELAY)
-0.3 to 10
V
Input Voltage Range:
MON
V
ADJ
-0.3 to 10
-0.3 to 16
V
V
Input Voltage Range (ENABLE)
-0.3 to 10**
V
ESD Susceptibility
(Human Body Model)
(Machine Model)
4.0
200
kV
V
Junction Temperature, T
J
-40 to +150
C
Storage Temperature, T
S
-55 to 150
C
Package Thermal Resistance, SOW-16 E PAD:
Junction-to-Case, R
JC
Junction-to-Ambient, R
JA
16
57
C/W
C/W
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
240 peak (Note 2)
C
1. 60 second maximum above 183
C.
2. -5
C/+0
C allowable conditions.
*The maximum package power dissipation must be observed.
During the voltage range which exceeds the maximum tested voltage of V
IN
, operation is assured, but not specified. Wider limits may apply.
Thermal dissipation must be observed closely.
**Reference Figure 15 for switched-battery ENABLE application.
ELECTRICAL CHARACTERISTICS
(I
OUT
= 1.0 mA, ENABLE = 5.0 V, -40
C
T
J
150
C; V
IN
= dependent on voltage option
(Note 3); unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage
Output Voltage for 2.5 V Option (V
O
)
6.5 V < V
IN
< 16 V, 1.0 mA
I
OUT
400 mA
4.5 V < V
IN
< 26 V, 1.0 mA
I
OUT
400 mA
2.450
2.425
2.5
2.5
2.550
2.575
V
V
Output Voltage for 3.3 V Option (V
O
)
7.3 V < V
IN
< 16 V, 1.0 mA
I
OUT
400 mA
4.5 V < V
IN
< 26 V, 1.0 mA
I
OUT
400 mA
3.234
3.201
3.3
3.3
3.366
3.399
V
V
Output Voltage for 5.0 V Option (V
O
)
9.0 V < V
IN
< 16 V, 1.0 mA
I
OUT
400 mA
6.0 V < V
IN
< 26 V, 1.0 mA
I
OUT
400 mA
4.90
4.85
5.0
5.0
5.10
5.15
V
V
Output Voltage for Adjustable Option
(V
O
)
V
OUT
= V
ADJ
(Unity Gain)
6.5 V < V
IN
< 16 V, 1.0 mA < I
OUT
< 400 mA
4.5 V < V
IN
< 26 V, 1.0 mA < I
OUT
< 400 mA
1.274
1.261
1.300
1.300
1.326
1.339
V
V
Dropout Voltage (V
IN
- V
OUT
)
(5.0 V and Adj. > 5.0 V Options Only)
I
OUT
= 400 mA
I
OUT
= 1.0 mA
-
-
400
30
600
150
mV
mV
Load Regulation
V
IN
= 14 V, 5.0 mA
I
OUT
400 mA
-30
5.0
30
mV
Line Regulation (2.5 V, 3.3 V, and
Adjustable Options)
4.5 V < V
IN
< 26 V, I
OUT
= 1.0 mA
-
5.0
25
mV
Line Regulation (5.0 V Option)
6.0 V < V
IN
< 26 V, I
OUT
= 1.0 mA
-
5.0
25
mV
Quiescent Current, (I
Q
) Active Mode
I
OUT
= 100
A, V
IN
= 12 V, MON = 3.0 V
I
OUT
= 75 mA, V
IN
= 14 V, MON = 3.0 V
I
OUT
400 mA, V
IN
= 14 V, MON = 3.0 V
-
-
-
200
2.5
25
350
5.0
45
A
mA
mA
Quiescent Current, (I
Q
) Sleep Mode
ENABLE = 0 V, V
IN
= 12 V, -40
C
T
J
125
C
-
-
1.0
A
Current Limit
-
425
800
-
mA
Short Circuit Output Current
V
OUT
= 0 V
100
500
-
mA
Thermal Shutdown
(Guaranteed by Design)
150
180
-
C
3. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type.
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4
ELECTRICAL CHARACTERISTICS (continued)
(I
OUT
= 1.0 mA, ENABLE = 5.0 V, -40
C
T
J
150
C; V
IN
= dependent on
voltage option (Note 4); unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Reset Function (RESET)
RESET Threshold for 2.5 V Option
HIGH (V
RH
)
LOW (V
RL
)
Hysteresis
V
IN
= 4.5 V (Note 5) (Note 6)
V
OUT
Increasing
V
OUT
Decreasing
2.35
2.30
25
-
-
-
1.0
V
O
-
-
V
V
mV
RESET Threshold for 3.3 V Option
HIGH (V
RH
)
LOW (V
RL
)
Hysteresis
V
IN
= 4.5 V (Note 5) (Note 6)
V
OUT
Increasing
V
OUT
Decreasing
3.10
3.00
35
-
-
-
1.0
V
O
-
-
V
V
mV
RESET Threshold for 5.0 V Option
HIGH (V
RH
)
LOW (V
RL
)
Hysteresis
V
IN
= 6.0 V (Note 6)
V
OUT
Increasing
V
OUT
Decreasing
4.70
4.60
50
-
-
-
1.0
V
O
-
-
V
V
mV
RESET Threshold for Adjustable Option
HIGH (V
RH
)
LOW (V
RL
)
Hysteresis
V
IN
= 4.5 V (Note 5) (Note 6)
V
OUT
Increasing
V
OUT
Decreasing
1.22
1.19
10
-
-
-
1.0
V
O
-
-
V
V
mV
Output Voltage
Low (V
RLO
)
V
IN
= Minimum (Note 6) (Note 7)
1.0 V
V
OUT
V
RL
, R
RESET
= 5.1 k
-
0.1
0.4
V
DELAY Switching Threshold (V
DT
)
(2.5 V, 3.3 V, and 5.0 V Options)
V
IN
= Minimum (Note 6) (Note 7)
1.4
1.8
2.2
V
DELAY Switching Threshold (V
DT
)
(Adjustable Option)
V
IN
= Minimum (Note 6) (Note 7)
1.0
1.3
1.6
V
DELAY Low Voltage
V
IN
= Minimum (Note 6) (Note 7)
V
OUT
< RESET Threshold Low(min)
-
-
0.2
V
DELAY Charge Current
V
IN
= Minimum (Note 6) (Note 7)
DELAY = 1.0 V, V
OUT
> V
RH
2.5
4.0
5.5
A
DELAY Discharge Current
V
IN
= Minimum (Note 6) (Note 7)
DELAY = 1.0 V, V
OUT
< V
RL
5.0
-
-
mA
Reset Adjust Switching Voltage (V
R(ADJ)
)
Hysteresis
V
IN
= Minimum (Note 6) (Note 7)
Increasing and Decreasing
1.16
20
1.25
50
1.34
100
V
mV
FLAG/Monitor
Monitor Threshold
V
IN
= Minimum (Note 6) (Note 7)
Increasing and Decreasing
1.20
1.28
1.36
V
Hysteresis
V
IN
= Minimum (Note 6) (Note 7)
10
35
75
mV
Input Current
MON = 2.0 V
-0.5
0.1
0.5
A
Output Saturation Voltage
MON = 0 V, I
FLAG
= 1.0 mA,
V
IN
= Minimum (Note 6) (Note 7)
-
0.1
0.4
V
Voltage Adjust (Adjustable Output only)
Input Current
V
ADJ
= 1.25 V, V
IN
= Minimum (Note 6) (Note 7)
-0.5
-
0.5
A
ENABLE
Input Threshold
Low, V
IN
= 14 V (Note 6)
High, V
IN
= 14 V (Note 6)
-
2.0
-
-
1.0
-
V
V
Input Current
ENABLE = 5.0 V, V
IN
= 14 V (Note 6)
-
30
75
A
4. Voltage range specified in the Output Stage of the Electrical Characteristics in boldface type.
5. For V
IN
4.5 V, a RESET = Low may occur with the output in regulation.
6. Part is guaranteed by design to meet specification over the entire V
IN
voltage range, but is production tested only at the specified V
IN
voltage.
7. Minimum V
IN
= 4.5 V for 2.5 V, 3.3 V, and Adjustable options. Minimum V
IN
= 6.0 V for 5.0 V option.
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5
PACKAGE PIN DESCRIPTION, ADJUSTABLE OUTPUT
Pin Number
Pin Symbol
Function
1
V
ADJ
Voltage Adjust. A resistor divider from V
OUT
to this lead sets the output voltage.
2
V
OUT
2.0%, 400 mA output.
3-6, 11, 12
NC
No connection.
7
V
IN
Input Voltage.
8
MON
Monitor. Input to comparator. If not needed connect to V
OUT.
9
R
ADJ
Reset adjust. If not needed connect to ground.
10
DELAY
Timing capacitor for RESET function.
13
GND
Ground. All GND leads must be connected to Ground
.
14
ENABLE
ENABLE control for the IC. A high powers the device up.
15
RESET
Active reset (accurate to V
OUT
1.0 V)
16
FLAG
Open collector output from comparator.
NOTE:
Tentative pinout for SOW-16 E Pad.
PACKAGE PIN DESCRIPTION, FIXED OUTPUT
Pin Number
Pin Symbol
Function
1
SENSE
Kelvin connection which allows remote sensing of output voltage for improved regulation. If
remote sensing is not desired, connect to V
OUT
.
2
V
OUT
2.0%, 400 mA output.
3-6, 11, 12
NC
No connection.
7
V
IN
Input Voltage.
8
MON
Monitor. Input to comparator. If not needed connect to V
OUT.
9
R
ADJ
Reset adjust. If not needed connect to ground.
10
DELAY
Timing capacitor for RESET function.
13
GND
Ground. All GND leads must be connected to Ground
.
14
ENABLE
ENABLE control for the IC. A high powers the device up.
15
RESET
Active reset (accurate to V
OUT
1.0 V)
16
FLAG
Open collector output from comparator.
NOTE:
Tentative pinout for SOW-16 E Pad.
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6
V
IN
RESET
V
OUT
FLAG
DELAY
Figure 2. Block Diagram
GND
MON
Current Source
(Circuit Bias)
Current Limit
Sense
Error Amplifier
V
BG
I
BIAS
V
BG
V
BG
I
BIAS
I
BIAS
V
BG
- 18 mV
I
BIAS
+ -
+
-
+
-
+
-
+
Bandgap
Reference
Thermal
Protection
1.8 V
(Fixed Versions)
1.3 V
(Adjustable Version)
4.0
A
15 k
Adjustable
Version only
V
ADJ
ENABLE
Fixed Versions only
R
ADJ
SENSE
+
-
1.5 V
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7
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. 5 V Output Voltage vs Temperature
0
0
I
out
, OUTPUT CURRENT (mA)
50
100
150
200
250
700
DROPOUT VOL
T
AGE (mV)
400
300
200
100
5 V and Adj. > 5 V options only
Figure 4. 3.3 V Output Voltage vs Temperature
Figure 5. 2.5 V Output Voltage vs Temperature
Figure 6. Dropout Voltage vs Output Current
0.01
I
out
, OUTPUT CURRENT (mA)
50
100
150
200
250
350
400
100
ESR (
W
)
10
1.0
0.1
0
Figure 7. Output Stability with Output Voltage Change
Figure 8. Output Stability with Output Capacitor Change
500
600
125
C
-40
V
out
, OUTPUT VOL
T
AGE (V)
4.90
TEMPERATURE (
C)
4.98
5.00
5.08
5.10
-20
140
0
20
40
60
80
120
100
V
OUT
= 5.0 V
V
IN
= 14 V
I
OUT
= 5.0 mA
4.96
5.06
4.94
5.04
4.92
5.02
160
-40
V
out
, OUTPUT VOL
T
AGE (V)
3.23
TEMPERATURE (
C)
3.31
3.33
3.35
-20
140
0
20
40
60
80
120
100
V
OUT
= 3.3 V
V
IN
= 14 V
I
OUT
= 5.0 mA
3.29
3.27
3.25
160
-40
V
out
, OUTPUT VOL
T
AGE (V)
2.45
TEMPERATURE (
C)
2.49
2.50
2.54
2.55
-20
140
0
20
40
60
80
120
100
V
OUT
= 2.5 V
V
IN
= 14 V
I
OUT
= 5.0 mA
2.48
2.53
2.47
2.52
2.46
2.51
160
300
350
400
25
C
-40
C
300
V
IN
= 14 V
C
VOUT
= 10
m
F
Unstable Region
Stable Region
2.5 V
3.3 V
5.0 V
0.1
I
out
, OUTPUT CURRENT (mA)
50
100
150
200
250
350
400
100
ESR (
W
)
10
1.0
0
300
5 V version
Unstable Region
Stable Region
C
VOUT
= 0.1
m
F
Unstable Region
C
VOUT
= 33
m
F*
*There is no unstable lower
region for the 33
m
F capacitor
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8
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. Quiescent Current vs Output Current
Figure 10. Quiescent Current vs Output Current
Figure 11. Quiescent Current vs Input Voltage
0
I
Q
, QUIESCENT CURRENT (mA)
0.0
I
OUT
, OUTPUT CURRENT (mA)
0.2
0.4
0.6
0.8
1.0
1.2
2.0
5
10
15
20
30
25
+25
C
+125
C
-40
C
Figure 12. Quiescent Current vs Input Voltage
35
40
50
45
1.4
1.6
1.8
0
I
Q
, QUIESCENT CURRENT (mA)
0
I
OUT
, OUTPUT CURRENT (mA)
10
20
30
40
50
60
50
100
150 200
300
250
+25
C
+125
C
-40
C
350
400
500
450
6
I
Q
, QUIESCENT CURRENT (mA)
0
V
IN
, INPUT VOLTAGE (V)
2
4
6
8
10
12
8
10
12
14
18
16
T = 25
C
I
out
= 200 mA
20
22
26
24
I
out
= 100 mA
I
out
= 50 mA
I
out
= 10 mA
6
I
Q
, QUIESCENT CURRENT (
m
A)
175
V
IN
, INPUT VOLTAGE (V)
180
185
190
195
200
210
8
10
12
14
18
16
T = 25
C
20
22
26
24
I
out
= 100
m
A
205
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9
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV8503 contains the microprocessor compatible
control function RESET (Figure 13).
Figure 13. Reset and Delay Circuit Wave Forms
V
IN
V
OUT
RESET
DELAY
(V
DT
)
Threshold
DELAY
Threshold
RESET
T
d
T
d
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until V
OUT
is within 1.5% of the regulated output
voltage, or when V
OUT
drops out of regulation,and is lower
than 4.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET signal is valid for V
OUT
as low
as 1.0 V.
Adjustable Reset Function
The reset threshold can be made lower by connecting an
external resistor divider to the R
ADJ
lead from the V
OUT
lead, as displayed in Figure 14. This lead is grounded to
select the default value of 4.6 V (on the 5.0 V option).
Figure 14. Adjustable RESET
R
ADJ
to
P and
System
Power
R
RST
V
OUT
C
OUT
RESET
C
DELAY
DELAY
NCV8503
to
P and
RESET
Port
V
R(ADJ)
ENABLE Function
The part stays in a low I
Q
sleep mode when the ENABLE
pin is held low. The part has an internal pull down if the pin
is left floating.
The integrity of the ENABLE pin allows it to be tied to the
battery line through an external resistor. It will withstand
load dump potentials in this configuration.
Figure 15. ENABLE Function
V
IN
V
OUT
GND
NCV8503
ENABLE
V
BAT
Up to 45 V
10 k
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET output lead.
The DELAY lead provides source current (typically 4.0
A)
to the external DELAY capacitor during the following
proceedings:
1. During Power Up (once the regulation threshold
has been verified).
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET threshold)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
FLAG/Monitor Comparator
A general use comparator is included whose positive input
terminal is tied to the on-chip band gap voltage reference.
This provides a very temperature stable referenced
comparator with versatile uses in any system. The trip point
can be programmed externally using a resistor divider to the
input monitor (MON) (Figure 16). The typical threshold is
1.28 V on the MON pin.
Figure 16. Flag/Monitor Function
V
BAT
V
IN
MON
V
OUT
C
OUT
V
CC
I/O
RESET
P
FLAG
RESET
GND
DELAY
NCV8503
R
ADJ
V
MON
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10
Voltage Adjust
Figure 17 shows the device setup for a user configurable
output voltage. The feedback to the V
ADJ
pin is taken from
a voltage divider referenced to the output voltage. The loop
is balanced around the Unity Gain threshold (1.30 V
typical).
Figure 17. Adjustable Output
Voltage
V
OUT
V
ADJ
NCV8503
15 k
5.1 k
C
OUT
5.0 V
1.28 V
APPLICATION NOTES
FLAG MONITOR
Figure 18 shows the FLAG Monitor waveforms as a result
of the circuit depicted in Figure 16. As the input voltage falls
(V
MON
), the Monitor threshold is crossed. This causes the
voltage on the FLAG output to go low.
Figure 18. FLAG Monitor Circuit Waveform
V
MON
MON
Flag Monitor
Ref. Voltage
FLAG
SETTING THE DELAY TIME
The delay time is controlled by the Reset Delay Low
Voltage, Delay Switching Threshold, and the Delay Charge
Current. The delay follows the equation:
tDELAY
+
[CDELAY(Vdt
*
Reset Delay Low Voltage)]
Delay Charge Current
Example:
Using C
DELAY
= 33 nF.
Assume reset Delay Low Voltage = 0.
Use the typical value for V
dt
= 1.8 V (2.5 V, 3.3 V, and
5.0 V options).
Use the typical value for Delay Charge Current = 4.2
A.
tDELAY
+
[33 nF(1.8
*
0)]
4.2
m
A
+
14 ms
STABILITY CONSIDERATIONS
The output or compensation capacitor helps determine
three main characteristics of a linear regulator: start-up
delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (-25
C to -40
C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor C
OUT
shown in Figure 19
should work for most applications, however it is not
necessarily the optimized solution.
Figure 19. Test and Application Circuit Showing
Output Compensation
V
IN
V
OUT
C
OUT
**
33
F
R
RST
RESET
C
IN
*
0.1
F
NCV8503
*C
IN
required if regulator is located far from the power supply filter
**C
OUT
required for stability. Capacitor must operate at minimum
temperature expected
NCV8503 Series
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Figure 20. 16 Lead SOW (Exposed Pad),
q
JA as a
Function of the Pad Copper Area (2 oz. Cu
Thickness), Board Material = 0.0625
,
G-10/R-4
40
70
90
100
Thermal
Resistance,
Junction to Ambient, R
q
JA
, (
C/W)
0
Copper Area (mm
2
)
200
400
800
80
60
50
600
CALCULATING POWER DISSIPATION IN A
SINGLE OUTPUT LINEAR REGULATOR
The maximum power dissipation for a single output
regulator (Figure 21) is:
PD(max)
+
[VIN(max)
*
VOUT(min)]IOUT(max)
(1)
)
VIN(max)IQ
where:
V
IN(max)
is the maximum input voltage,
V
OUT(min)
is the minimum output voltage,
I
OUT(max)
is the maximum output current for the
application, and
I
Q
is the quiescent current the regulator consumes at
I
OUT(max)
.
Once the value of P
D(max)
is known, the maximum
permissible value of R
qJA
can be calculated:
R
q
JA
+
150
C
*
TA
PD
(2)
The value of R
qJA
can then be compared with those in the
package section of the data sheet. Those packages with
R
qJA
's less than the calculated value in equation 2 will keep
the die temperature below 150
C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
SMART
REGULATOR
I
Q
Control
Features
I
OUT
I
IN
Figure 21. Single Output Regulator with Key
Performance Parameters Labeled
V
IN
V
OUT
}
HEAT SINKS
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of R
qJA
:
R
q
JA
+
R
q
JC
)
R
q
CS
)
R
q
SA
(3)
where:
R
qJC
= the junction-to-case thermal resistance,
R
qCS
= the case-to-heatsink thermal resistance, and
R
qSA
= the heatsink-to-ambient thermal resistance.
R
qJC
appears in the package section of the data sheet. Like
R
qJA
, it too is a function of package type. R
qCS
and R
qSA
are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
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12
ORDERING INFORMATION
Device
Output Voltage
Package
Shipping
NCV8503PWADJ
Adjustable
47 Units/Rail
NCV8503PWADJR2
Adjustable
1000 Tape & Reel
NCV8503PW25
2 5 V
47 Units/Rail
NCV8503PW25R2
2.5 V
SOW 16 Exposed Pad
1000 Tape & Reel
NCV8503PW33
3 3 V
SOW-16 Exposed Pad
47 Units/Rail
NCV8503PW33R2
3.3 V
1000 Tape & Reel
NCV8503PW50
5 0 V
47 Units/Rail
NCV8503PW50R2
5.0 V
1000 Tape & Reel
NCV8503 Series
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13
PACKAGE DIMENSIONS
SOIC 16 LEAD WIDE BODY
EXPOSED PAD
PDW SUFFIX
CASE 751R-02
ISSUE A
G
-W-
-U-
P
M
0.25 (0.010)
W
-T-
SEATING
PLANE
K
D
16 PL
C
M
0.25 (0.010)
T U
W
S
S
M
F
DETAIL E
DETAIL E
R x 45
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE
0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
6. 751R-01 OBSOLETE, NEW STANDARD 751R-02.
J
M
14 PL
PIN 1 I.D.
8
1
16
9
TOP SIDE
0.10 (0.004) T
16
EXPOSED PAD
1
8
BACK SIDE
L
H
DIM
A
MIN
MAX
MIN
MAX
INCHES
10.15
10.45
0.400
0.411
MILLIMETERS
B
7.40
7.60
0.292
0.299
C
2.35
2.65
0.093
0.104
D
0.35
0.49
0.014
0.019
F
0.50
0.90
0.020
0.035
G
1.27 BSC
0.050 BSC
H
3.76
3.86
0.148
0.152
J
0.25
0.32
0.010
0.012
K
0.10
0.25
0.004
0.009
L
4.58
4.78
0.180
0.188
M
0
7
0
7
P
10.05
10.55
0.395
0.415
R
0.25
0.75
0.010
0.029
_
_
_
_
A
B
9
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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81-3-5773-3850
NCV8503/D
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLIC).
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