Semiconductor Components Industries, LLC, 2002
June, 2002 Rev. 1
1
Publication Order Number:
NLAS4052/D
NLAS4052
Analog Multiplexer/
Demultiplexer
DoublePole, 4Position
Plus Common Off
The NLAS4052 is an improved version of the MC14052 and
MC74HC4052 fabricated in submicron Silicon Gate CMOS
technology for lower R
DS(on)
resistance and improved linearity with
low current. This device may be operated either with a single supply or
dual supply up to
3 V to pass a 6 V
PP
signal without coupling
capacitors.
When operating in single supply mode, it is only necessary to tie
V
EE
, pin 7 to ground. For dual supply operation, V
EE
is tied to a
negative voltage, not to exceed maximum ratings.
Improved R
DS(on)
Specifications
Pin for Pin Replacement for MAX4052 and MAX4052A
One Half the Resistance Operating at 5.0 Volts
Single or Dual Supply Operation
Single 2.55 Volt Operation, or Dual
3 Volt Operation
With V
CC
of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
No Translators Needed
Address and Inhibit pins are Logic is OverVoltage Tolerant and
May Be Driven Up +6 V Regardless of V
CC
Address and Inhibit pins are Standard TTL Compatible
Greatly Improved Noise Margin Over MAX4052 and MAX4052A
Improved Linearity Over Standard HC4052 Devices
Popular SOIC, and Space Saving TSSOP, and QSOP 16 Pin
Packages
SO16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
1
8
9
16
NLAS4052
AWLYWW
MARKING DIAGRAMS
NLAS
4052
ALYW
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
NLAS4052DR2
SO16
2500 Units/Reel
NLAS4052DTR2
TSSOP16
2500 Units/Reel
NLAS4052QSR
QSOP16
2500 Units/Reel
QSOP16
QS SUFFIX
CASE 492
NLAS
4052
ALYW
1
8
16
9
1
8
16
9
http://onsemi.com
NLAS4052
http://onsemi.com
2
Figure 1. Pin Connection
(Top View)
Figure 2. Logic Diagram
15
16
14
13
12
11
10
2
1
3
4
5
6
7
V
CC
9
8
NO
1A
NO
2A
COM
A
NO
0A
NO
3A
ADD
B
ADD
A
NO
0B
NO
1B
COM
B
NO
3B
NO
2B
Inhibit V
EE
GND
COM
A
NO
2A
NO
3A
Inhibit
NO
0B
NO
0A
NO
1A
NO
1B
COM
B
NO
3B
NO
2B
ADD
A
LOGIC
ADD
B
TRUTH TABLE
Address
Inhibit
B
A
ON SWITCHES*
1
X
don't care
X
don't care
All switches open
0
0
0
COM
A
NO
0A
,
COM
B
NO
0B
0
0
1
COM
A
NO
1A
,
COM
B
NO
1B
0
1
0
COM
A
NO
2A
,
COM
B
NO
2B
0
1
1
COM
A
NO
3A
,
COM
B
NO
3B
*NO and COM pins are identical and interchangeable. Either may be
considered an input or output; signals pass equally well in either direction.
NLAS4052
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3
MAXIMUM RATINGS
(Note 1)
Symbol
Parameter
Value
Unit
V
EE
Negative DC Supply Voltage
(Referenced to GND)
7.0 to
)
0.5
V
V
CC
Positive DC Supply Voltage (Note 2)
(Referenced to GND)
(Referenced to V
EE
)
0.5 to
)
7.0
0.5 to
)
7.0
V
V
IS
Analog Input Voltage
V
EE
0.5 to V
CC
)
0.5
V
V
IN
Digital Input Voltage
(Referenced to GND)
0.5 to 7.0
V
I
DC Current, Into or Out of Any Pin
$
50
mA
T
STG
Storage Temperature Range
65 to
)
150
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
260
C
T
J
Junction Temperature under Bias
)
150
C
q
JA
Thermal Resistance
SOIC
TSSOP
QSOP
143
164
164
C/W
P
D
Power Dissipation in Still Air,
SOIC
TSSOP
QSOP
500
450
450
mW
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating
Oxygen Index: 30% 35%
UL 94 V0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
u
2000
u
200
u
1000
V
I
LATCHUP
LatchUp Performance
Above V
CC
and Below GND at 125
C (Note 6)
$
300
mA
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximumrated
conditions is not implied.
2. The absolute value of V
CC
$
|V
EE
|
7.0.
3. Tested to EIA/JESD22A114A.
4. Tested to EIA/JESD22A115A.
5. Tested to JESD22C101A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
EE
Negative DC Supply Voltage
(Referenced to GND)
5.5
GND
V
V
CC
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to V
EE
)
2.5
2.5
5.5
6.6
V
V
IS
Analog Input Voltage
V
EE
V
CC
V
V
IN
Digital Input Voltage
(Note 7) (Referenced to GND)
0
5.5
V
T
A
Operating Temperature Range, All Package Types
55
125
C
t
r
, t
f
Input Rise/Fall Time
V
CC
= 3.0 V
$
0.3 V
(Channel Select or Enable Inputs)
V
CC
= 5.0 V
$
0.5 V
0
0
100
20
ns/V
7. Unused digital inputs may not be left open. All digital inputs must be tied to a highlogic voltage level or a lowlogic input voltage level.
NLAS4052
http://onsemi.com
4
DC CHARACTERISTICS Digital Section
(Voltages Referenced to GND)
Guaranteed Max Limit
Symbol
Parameter
Condition
V
CC
55 to 25
5
C
<85
5
C
<125
5
C
Unit
V
IH
Minimum HighLevel Input Voltage,
Enable Inputs
2.5
3.0
4.5
5.5
1.75
2.1
3.15
3.85
1.75
2.1
3.15
3.85
1.75
2.1
3.15
3.85
V
V
IL
Maximum LowLevel Input Voltage,
Enable Inputs
2.5
3.0
4.5
5.5
0.45
0.9
1.35
1.65
0.45
0.9
1.35
1.65
0.45
0.9
1.35
1.65
V
I
IN
Maximum Input Leakage Current,
Address or Inhibit Inputs
V
IN
= 6.0 or GND
0 V to 6.0 V
$
0.1
$
1.0
$
1.0
m
A
I
CC
Maximum Quiescent Supply
Current (per Package)
Address, Inhibit and
V
IS
= V
CC
or GND
6.0
4.0
40
80
m
A
DC ELECTRICAL CHARACTERISTICS Analog Section
V
CC
V
EE
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
V
EE
V
55 to 25
C
v
85
C
v
125
C
Unit
R
ON
Maximum "ON" Resistance
(Note 8)
V
IN
= V
IL
or V
IH
V
IS
= V
EE
to V
CC
|I
S
| = 10 mA
(Figures 4 thru 9)
3.0
4.5
3.0
0
0
3.0
86
37
26
108
46
33
120
55
37
W
D
R
ON
Maximum Difference in "ON"
Resistance Between Any
Two Channels in the Same
Package
V
IN
= V
IL
or V
IH,
V
IS
= 2.0 V
V
IS
= 3.5 V
|I
S
| = 10 mA, V
IS
= 2.0 V
3.0
4.5
3.0
0
0
3.0
15
13
10
20
18
15
20
18
15
W
R
flat(ON)
ON Resistance Flatness
|I
S
| = 10 mA
V
com
1, 2, 3.5 V
V
com
2, 0, 2 V
4.5
3.0
3.0
4
2
4
2
5
3
W
I
NC(OFF)
I
NO(OFF)
Maximum OffChannel
Leakage Current
Switch Off
V
IN
= V
IL
or V
IH
V
IO
= V
CC
1.0 V or V
EE
+1.0 V
(Figure 17)
6.0
3.0
0
3.0
0.1
0.1
5.0
5.0
100
100
nA
I
COM(ON)
Maximum OnChannel
Leakage Current, Channel
toChannel
Switch On
V
IO
= V
CC
1.0 V or V
EE
+1.0 V
(Figure 17)
6.0
3.0
0
3.0
0.1
0.1
5.0
5.0
100
100
nA
8. At supply voltage (V
CC
) approaching 2.5 V the analog switch onresistance becomes extremely nonlinear. Therefore, for low voltage
operation it is recommended that these devices only be used to control digital signals.
NLAS4052
http://onsemi.com
5
AC CHARACTERISTICS
(Input t
r
= t
f
= 3 ns)
Guaranteed Limit
V
CC
V
EE
55 to 25
C
Symbol
Parameter
Test Conditions
V
CC
V
V
EE
V
Min
Typ*
v
85
C
v
125
C
Unit
t
BBM
Minimum BreakBeforeMake
Time
V
IN
= V
IL
or V
IH
V
IS
= V
CC
R
L
= 300
W,
C
L
= 35 pF
(Figure 19)
3.0
4.5
3.0
0.0
0.0
3.0
1.0
1.0
1.0
6.5
5.0
3.5
ns
*Typical Characteristics are at 25
C.
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 3 ns)
Guaranteed Limit
V
CC
V
EE
55 to 25
C
v
85
C
v
125
C
Symbol
Parameter
V
CC
V
V
EE
V
Min
Typ
Max
Min
Max
Min
Max
Unit
t
TRANS
Transition Time
(Address Selection Time)
(Figure 18)
2.5
3.0
4.5
3.0
0
0
0
3.0
22
20
16
16
40
28
23
23
45
30
25
25
50
35
30
28
ns
t
ON
Turnon Time
(Figures 14, 15, 20, and 21)
Inhibit to N
O
or N
C
2.5
3.0
4.5
3.0
0
0
0
3.0
22
20
16
16
40
28
23
23
45
30
25
25
50
35
30
28
ns
t
OFF
Turnoff Time
(Figures 14, 15, 20, and 21)
Inhibit to N
O
or N
C
2.5
3.0
4.5
3.0
0
0
0
3.0
22
20
16
16
40
28
23
23
45
30
25
25
50
35
30
28
ns
Typical @ 25
C, V
CC
= 5.0 V
C
IN
Maximum Input Capacitance,Select Inputs
8
pF
C
NO
or C
NC
Analog I/O
10
C
COM
Common I/O
10
C
(ON)
Feedthrough
1.0
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