Semiconductor Components Industries, LLC, 2002
March, 2002 Rev. 1
1
Publication Order Number:
NTP27N06L/D
NTP27N06L, NTB27N06L
Power MOSFET
27 Amps, 60 Volts, Logic Level
NChannel TO220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters, power motor controls and bridge circuits.
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
MAXIMUM RATINGS
(TC = 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
DraintoSource Voltage
VDSS
60
Vdc
DraintoGate Voltage (RGS = 10 M
)
VDGR
60
Vdc
GatetoSource Voltage
Continuous
NonRepetitive (tp
v
10 ms)
VGS
VGS
"
15
"
20
Vdc
Drain Current
Continuous @ TA = 25
C
Continuous @ TA 100
C
Single Pulse (tp
v
10
s)
ID
ID
IDM
27
15
80
Adc
Apk
Total Power Dissipation @ TA = 25
C
Derate above 25
C
PD
88.2
0.59
W
W/
C
Operating and Storage Temperature Range
TJ, Tstg
55 to
+175
C
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25
C
(VDD = 50 Vdc, VGS = 5.0 Vdc,
L = 0.3 mH, IL(pk) = 25 A,VDS = 60 Vdc)
EAS
94
mJ
Thermal Resistance JunctiontoCase
R
JC
1.7
C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8
from case for 10 seconds
TL
260
C
27 AMPERES
60 VOLTS
RDS(on) = 48 m
Device
Package
Shipping
ORDERING INFORMATION
NTP27N06L
TO220AB
50 Units/Rail
TO220AB
CASE 221A
STYLE 5
1
2
3
4
http://onsemi.com
NChannel
D
S
G
MARKING DIAGRAMS
& PIN ASSIGNMENTS
NTx27N06L = Device Code
x
= B or P
LL
= Location Code
Y
= Year
WW
= Work Week
NTx27N06L
LLYWW
1
Gate
3
Source
4
Drain
2
Drain
NTx27N06L
LLYWW
1
Gate
3
Source
4
Drain
2
Drain
1
2
3
4
D2PAK
CASE 418B
STYLE 2
NTB27N06L
D2PAK
50 Units/Rail
NTB27N06LT4
D2PAK
800/Tape & Reel
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2
ELECTRICAL CHARACTERISTICS
(TC = 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage (Note 1)
(VGS = 0 Vdc, ID = 250
Adc)
Temperature Coefficient (Positive)
V(BR)DSS
60
71
68
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ =150
C)
IDSS
1.0
10
Adc
GateBody Leakage Current (VGS =
15
Vdc, VDS = 0 Vdc)
IGSS
100
nAdc
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage (Note 1)
(VDS = VGS, ID = 250
Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
1.0
1.6
4.6
2.0
Vdc
mV/
C
Static DraintoSource OnResistance (Note 1)
(VGS = 5.0 Vdc, ID = 13.5 Adc)
RDS(on)
37
48
m
Static DraintoSource OnResistance (Note 1)
(VGS = 5.0 Vdc, ID = 27 Adc)
(VGS = 5.0 Vdc, ID = 13.5 Adc, TJ = 150
C)
VDS(on)
0.91
0.95
1.56
Vdc
Forward Transconductance (Note 1) (VDS = 4.0 Vdc, ID = 10 Adc)
gFS
19.4
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
25 Vd
V
0 Vd
Ciss
707
990
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
227
320
Transfer Capacitance
f = 1.0 MHz)
Crss
74
105
SWITCHING CHARACTERISTICS (Note 2)
TurnOn Delay Time
td(on)
10.8
22
ns
Rise Time
(VDD = 30 Vdc, ID = 27 Adc,
tr
115
230
TurnOff Delay Time
(VDD 30 Vdc, ID 27 Adc,
VGS = 5.0 Vdc, RG = 9.1
) (Note 1)
td(off)
21
40
Fall Time
tf
65
130
Gate Charge
(V
48 Vd
I
27 Ad
QT
15.2
32
nC
(VDS = 48 Vdc, ID = 27 Adc,
VGS = 5.0 Vdc) (Note 1)
Q1
4.7
VGS = 5.0 Vdc) (Note 1)
Q2
7.8
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage
(IS = 27 Adc, VGS = 0 Vdc) (Note 1)
(IS = 27 Adc, VGS = 0 Vdc, TJ = 150
C)
VSD
0.91
0.86
1.25
Vdc
Reverse Recovery Time
(I
27 Ad
V
0 Vd
trr
42
ns
(IS = 27 Adc, VGS = 0 Vdc,
dlS/dt = 100 A/
s) (Note 1)
ta
27
dlS/dt = 100 A/
s) (Note 1)
tb
15
Reverse Recovery Stored Charge
QRR
0.056
C
1. Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
2. Switching characteristics are independent of operating junction temperature.
NTP27N06L, NTB27N06L
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3
0
40
3
20
2
1
I D
, DRAIN CURRENT (AMPS)
0
VGS, GATETOSOURCE VOLTAGE (VOLTS)
I D
, DRAIN CURRENT (AMPS)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (
)
60
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
10
30
50
6
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (
)
2
1.8
1.4
1.6
1.2
1
0.6
100
10
1000
10000
0.02
Figure 1. OnRegion Characteristics
Figure 2. Transfer Characteristics
0
40
30
20
10
50
60
Figure 3. OnResistance versus
GatetoSource Voltage
ID, DRAIN CURRENT (AMPS)
Figure 4. OnResistance versus Drain Current
and Gate Voltage
ID, DRAIN CURRENT (AMPS)
Figure 5. OnResistance Variation with
Temperature
TJ, JUNCTION TEMPERATURE (
C)
Figure 6. DraintoSource Leakage Current
versus Voltage
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
I DSS
, LEAKAGE (nA)
50
50
25
0
25
75
100
1
1.5
6
0.05
0
0.07
0.1
0
40
50
30
20
10
60
40
20
0
60
10
30
50
2
2.5
3
3.5
4
4.5
5.5
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (NORMALIZED)
0.8
175
150
125
0.02
0.05
0
0.08
0.1
0
40
30
20
10
50
60
VGS = 5 V
ID = 27 A
VGS = 5 V
VDS
w
10 V
TJ = 25
C
TJ = 55
C
TJ = 100
C
TJ = 100
C
TJ = 150
C
VGS = 0 V
TJ = 25
C
TJ = 100
C
TJ = 55
C
VGS = 10 V
5
0.01
0.03
0.04
0.06
0.07
0.09
0.01
0.03
0.04
0.06
0.08
0.09
4 V
4.5 V
5 V
3.5 V
3 V
VGS = 10 V
6 V
8 V
TJ = 25
C
TJ = 100
C
TJ = 55
C
4
5
NTP27N06L, NTB27N06L
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4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
Crss
10
0
10
15
20
25
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
Figure 7. Capacitance Variation
600
200
0
VGS
VDS
300
100
5
5
VGS = 0 V
VDS = 0 V
TJ = 25
C
Ciss
Coss
Crss
Ciss
400
500
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5
28
0
0.56
DRAINTOSOURCE DIODE CHARACTERISTICS
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
Figure 8. GateToSource and DrainToSource
Voltage versus Total Charge
I S
, SOURCE CURRENT
(AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (
)
1
10
100
1000
1
t, TIME
(ns)
VGS = 0 V
TJ = 25
C
Figure 10. Diode Forward Voltage versus Current
V
GS
, GA
TET
OSOURCE VOL
T
AGE (VOL
TS)
0
5
3
1
0
QG, TOTAL GATE CHARGE (nC)
6
4
2
6
10
100
4
12
8
16
0.6 0.64 0.68 0.72 0.76
0.96
8
16
4
12
20
24
ID = 27 A
TJ = 25
C
VGS
Q2
Q1
QT
tr
td(off)
td(on)
tf
10
VDS = 30 V
ID = 27 A
VGS = 5 V
0.8 0.84 0.88
2
14
0.92
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25
C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal Resistance
General Data and Its Use."
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10
s. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) TC)/(R
JC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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6
SAFE OPERATING AREA
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
t, TIME (s)
1
0.1
1
10
0.1
0.01
0.0001
TJ, STARTING JUNCTION TEMPERATURE (
C)
E
AS
, SINGLE PULSE DRAINT
OSOURCE
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1
1
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 13. Thermal Response
1
100
A
V
ALANCHE ENERGY
(mJ)
I D
, DRAIN CURRENT
(AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0
25
50
75
100
125
20
ID = 25 A
10
10
175
Figure 14. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
10
50
40
30
100
VGS = 20 V
SINGLE PULSE
TC = 25
C
60
1 ms
100
s
10 ms
dc
10
s
150
r(t), EFFECTIVE TRANSIENT THERMAL
RESIST
ANCE (NORMALIZED)
0.001
D = 0.5
0.2
0.1
0.05
0.01
SINGLE PULSE
70
80
90
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7
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
mm
inches
0.33
8.38
0.08
2.032
0.04
1.016
0.63
17.02
0.42
10.66
0.12
3.05
0.24
6.096
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8
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC59, SC70/SOT323, SOD123, SOT23, SOT143,
SOT223, SO8, SO14, SO16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the drain pad, misalignment and/or
"tombstoning" may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 15 shows a
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
Figure 15. Typical Stencil for DPAK and
D2PAK Packages
SOLDER PASTE
OPENINGS
STENCIL
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
Always preheat the device.
The delta temperature between the preheat and
soldering should be 100
C or less.*
When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10
C.
The soldering temperature and time shall not exceed
260
C for more than 10 seconds.
When shifting from preheating to soldering, the
maximum temperature gradient shall be 5
C or less.
After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
Mechanical stress or shock should not be applied
during cooling.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* * Due to shadowing and the inability to set the wave
height to incorporate other surface mount components, the
D2PAK is not recommended for wave soldering.
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9
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating "profile" for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177189
C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joint.
STEP 1
PREHEAT
ZONE 1
"RAMP"
STEP 2
VENT
"SOAK"
STEP 3
HEATING
ZONES 2 & 5
"RAMP"
STEP 4
HEATING
ZONES 3 & 6
"SOAK"
STEP 5
HEATING
ZONES 4 & 7
"SPIKE"
STEP 6
VENT
STEP 7
COOLING
200
C
150
C
100
C
5
C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205
TO 219
C
PEAK AT
SOLDER
JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
100
C
150
C
160
C
170
C
140
C
Figure 16. Typical Solder Heating Profile
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10
PACKAGE DIMENSIONS
D2PAK
CASE 418B03
ISSUE D
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
S
G
D
T
M
0.13 (0.005)
T
2
3
1
4
3 PL
K
J
H
V
E
C
A
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.340
0.380
8.64
9.65
B
0.380
0.405
9.65
10.29
C
0.160
0.190
4.06
4.83
D
0.020
0.035
0.51
0.89
E
0.045
0.055
1.14
1.40
G
0.100 BSC
2.54 BSC
H
0.080
0.110
2.03
2.79
J
0.018
0.025
0.46
0.64
K
0.090
0.110
2.29
2.79
S
0.575
0.625
14.60
15.88
V
0.045
0.055
1.14
1.40
B
M
B
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11
PACKAGE DIMENSIONS
TO220
CASE 221A09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.570
0.620
14.48
15.75
B
0.380
0.405
9.66
10.28
C
0.160
0.190
4.07
4.82
D
0.025
0.035
0.64
0.88
F
0.142
0.147
3.61
3.73
G
0.095
0.105
2.42
2.66
H
0.110
0.155
2.80
3.93
J
0.018
0.025
0.46
0.64
K
0.500
0.562
12.70
14.27
L
0.045
0.060
1.15
1.52
N
0.190
0.210
4.83
5.33
Q
0.100
0.120
2.54
3.04
R
0.080
0.110
2.04
2.79
S
0.045
0.055
1.15
1.39
T
0.235
0.255
5.97
6.47
U
0.000
0.050
0.00
1.27
V
0.045
---
1.15
---
Z
---
0.080
---
2.04
B
Q
H
Z
L
V
G
N
A
K
F
1 2 3
4
D
SEATING
PLANE
T
C
S
T
U
R
J
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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12
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4321 NishiGotanda, Shinagawaku, Tokyo, Japan 1410031
Phone: 81357402700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
NTP27N06L/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 3036752175 or 8003443860 Toll Free USA/Canada
Fax: 3036752176 or 8003443867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
N. American Technical Support: 8002829855 Toll Free USA/Canada
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