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Электронный компонент: NTD14N03R

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Semiconductor Components Industries, LLC, 2003
April, 2003 - Rev. 2
1
Publication Order Number:
NTD14N03R/D
NTD14N03R
Power MOSFET
14 Amps, 25 Volts
N-Channel DPAK
Features
Planar HD3e Process for Fast Switching Performance
Low R
DS(on)
to Minimize Conduction Loss
Low C
iss
to Minimize Driver Loss
Low Gate Charge
Optimized for High Side Switching Requirements in
High-Ef ficiency DC-DC Converters
MAXIMUM RATINGS
(T
J
= 25
C unless otherwise specified)
Parameter
Symbol
Value
Unit
Drain-to-Source Voltage
V
DSS
25
V
dc
Gate-to-Source Voltage - Continuous
V
GS
20
V
dc
Thermal Resistance - Junction-to-Case
Total Power Dissipation @ T
A
= 25
C
Drain Current - Continuous @ T
A
= 25
C, Chip
- Continuous @ T
A
= 25
C, Limited by Package
- Single Pulse (tp
10
m
s)
R
q
JC
P
D
I
D
I
D
I
D
6.0
20.8
14
11.4
28
C/W
W
A
A
A
Thermal Resistance - Junction-to-Ambient
(Note 1)
Total Power Dissipation @ T
A
= 25
C
Drain Current - Continuous @ T
A
= 25
C
R
q
JA
P
D
I
D
80
1.56
3.1
C/W
W
A
Thermal Resistance - Junction-to-Ambient
(Note 2)
Total Power Dissipation @ T
A
= 25
C
Drain Current - Continuous @ T
A
= 25
C
R
q
JA
P
D
I
D
120
1.04
2.5
C/W
W
A
Operating and Storage Temperature Range
T
J
, T
stg
-55 to
150
C
Maximum Lead Temperature for Soldering
Purposes, 1/8
from case for 10 seconds
T
L
260
C
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using minimum recommended pad
size.
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14 AMPERES, 25 VOLTS
R
DS(on)
= 70.4 m
W
(Typ)
D
S
G
N-CHANNEL
Device
Package
Shipping
ORDERING INFORMATION
DPAK
75 Units/Rail
MARKING DIAGRAM
& PIN ASSIGNMENTS
14N03
= Device Code
Y
= Year
WW
= Work Week
CASE 369C
YWW
T14
N03
NTD40N03R-1
DPAK
Straight Lead
75 Units/Rail
NTD40N03RT4
DPAK
2500 Tape & Reel
4 Drain
3
Source
1
Gate
2
Drain
DPAK
(Surface Mount)
STYLE 2
CASE 369D
DPAK
(Straight Lead)
STYLE 2
1 2
3
4
4 Drain
1
Gate
2
Drain
3
Source
4
1
2
3
NTD14N03R
YWW
T14
N03
NTD14N03R
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2
ELECTRICAL CHARACTERISTICS
(T
J
= 25
C unless otherwise specified)
Characteristics
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage (Note 3)
(V
GS
= 0 Vdc, I
D
= 250
m
Adc)
Temperature Coefficient (Positive)
V(br)
DSS
25
-
28
-
-
-
Vdc
mV/
C
Zero Gate Voltage Drain Current
(V
DS
= 20 Vdc, V
GS
= 0 Vdc)
(V
DS
= 20 Vdc, V
GS
= 0 Vdc, T
J
= 150
C)
I
DSS
-
-
-
-
1.0
10
m
Adc
Gate-Body Leakage Current
(V
GS
=
20 Vdc, V
DS
= 0 Vdc)
I
GSS
-
-
100
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(V
DS
= V
GS
, I
D
= 250
m
Adc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
1.0
-
1.5
-
2.0
-
Vdc
mV/
C
Static Drain-to-Source On-Resistance (Note 3)
(V
GS
= 4.5 Vdc, I
D
= 5 Adc)
(V
GS
= 10 Vdc, I
D
= 5 Adc)
R
DS(on)
-
-
117
70.4
130
95
m
W
Forward Transconductance (Note 3)
(V
DS
= 10 Vdc, I
D
= 5 Adc)
g
FS
-
7.0
-
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
-
115
-
pF
Output Capacitance
(V
DS
= 20 Vdc, V
GS
= 0 V, f = 1 MHz)
C
oss
-
62
-
Transfer Capacitance
(
DS
,
GS
,
)
C
rss
-
33
-
SWITCHING CHARACTERISTICS (Note 4)
Turn-On Delay Time
t
d(on)
-
3.8
-
ns
Rise Time
(V
GS
= 10 Vdc, V
DD
= 10 Vdc,
t
r
-
27
-
Turn-Of f Delay Time
(V
GS
= 10 Vdc, V
DD
= 10 Vdc,
I
D
= 5 Adc, R
G
= 3
W
)
t
d(off)
-
9.6
-
Fall Time
t
f
-
2.0
-
Gate Charge
Q
T
-
1.8
-
nC
(V
GS
= 5 Vdc, I
D
= 5 Adc,
V
DS
= 10 Vdc) (Note 3)
Q
1
-
0.8
-
V
DS
= 10 Vdc) (Note 3)
Q
2
-
0.7
-
SOURCE-DRAIN DIODE CHARACTERISTICS
Forward On-Voltage
(I
S
= 5 Adc, V
GS
= 0 Vdc) (Note 3)
V
SD
-
0 93
1 2
Vdc
(I
S
= 5 Adc, V
GS
= 0 Vdc) (Note 3)
(I
S
= 5 Adc, V
GS
= 0 Vdc, T
J
= 125
C)
-
-
0.93
0.82
1.2
-
dc
Reverse Recovery Time
t
rr
-
6.6
-
ns
(I
S
= 5 Adc, V
GS
= 0 Vdc,
t
a
-
4.75
-
(I
S
= 5 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/
m
s) (Note 3)
t
b
-
1.88
-
Reverse Recovery Stored Charge
Q
RR
-
0.002
-
m
C
3. Pulse Test: Pulse Width
300
m
s, Duty Cycle
2%.
4. Switching characteristics are independent of operating junction temperatures.
NTD14N03R
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3
1.8
1.6
1.2
1.4
1
0.8
0.6
100
10
1000
8
4
12
2
6
0
14
0.08
0
10
10
4
4
2
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
0
V
GS
, GATE-T O-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
I
D
, DRAIN CURRENT (AMPS)
0
0.16
0.20
8
6
4
0.12
0.08
0.04
0
2
10
12
Figure 3. On-Resistance versus Drain Current
and Temperature
I
D
, DRAIN CURRENT (AMPS)
Figure 4. On-Resistance versus Drain Current
and Temperature
I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE
(
)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE
(
)
Figure 5. On-Resistance Variation with
Temperature
T
J
, JUNCTION TEMPERATURE (
C)
Figure 6. Drain-to-Source Leakage Current
versus Voltage
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE
(NORMALIZED)
I
DSS
, LEAKAGE (nA)
14
-50
50
25
0
-25
75
125
100
0
3
4
2
1
5
0
6
8
4
10
2
12
0
0.04
0.12
0.20
0
20
25
15
10
5
V
GS
= 2.5 V
6
2
6
8
V
DS
10 V
T
J
= 25
C
T
J
= -55
C
T
J
= 125
C
6
T
J
= 25
C
T
J
= -55
C
T
J
= 125
C
V
GS
= 10 V
V
GS
= 4.5 V
150
V
GS
= 0 V
T
J
= 150
C
T
J
= 125
C
I
D
= 5 A
V
GS
= 10 V
0.16
T
J
= 25
C
T
J
= -55
C
T
J
= 125
C
14
14
10
8
12
7 V
5 V
10 V
3.5 V
4 V
4.5 V
8 V
6 V
3 V
NTD14N03R
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4
100
10
1
8
6
4
2
0
70
60
50
40
30
0
10
10
200
15
5
0
20
GATE-T O-SOURCE OR DRAIN-TO-SOURCE VOLTAGE
(VOLTS)
C, CAP
ACIT
ANCE (pF)
160
120
80
40
0
5
Q
g
, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and
Drain-to-Source Voltage versus Total Charge
V
GS
, GA
TE-T
O-SOURCE
VOL
T
AGE (VOL
TS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
R
G
, GATE RESISTANCE (
)
Figure 10. Diode Forward Voltage versus
Current
V
SD
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
I
S
, SOURCE CURRENT (AMPS)
t, TIME (ns)
0
1.6
2.0
1.2
0.8
0.4
1
10
100
0
0.4
0.2
0.8
1.0
I
D
= 5 A
T
J
= 25
C
V
GS
V
GS
= 0 V
V
DS
= 0 V
T
J
= 25
C
C
rss
C
iss
C
oss
C
rss
20
10
0.6
Q
2
C
iss
V
DS
= 10 V
I
D
= 5 A
V
GS
= 10 V
V
GS
= 0 V
t
r
t
d(off)
t
d(on)
t
f
V
GS
V
DS
Q
1
Q
T
T
J
= 25
C
T
J
= 150
C
RECOMMENDED FOOTPRINTS FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
NTD14N03R
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5
PACKAGE DIMENSIONS
CASE 369C
ISSUE O
DPAK (SINGLE GAUGE)
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
D
A
K
B
R
V
S
F
L
G
2 PL
M
0.13 (0.005)
T
E
C
U
J
H
-T-
SEATING
PLANE
Z
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.22
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.180 BSC
4.58 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.102
0.114
2.60
2.89
L
0.090 BSC
2.29 BSC
R
0.180
0.215
4.57
5.45
S
0.025
0.040
0.63
1.01
U
0.020
---
0.51
---
V
0.035
0.050
0.89
1.27
Z
0.155
---
3.93
---
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
1
2
3
4
CASE 369D
ISSUE O
DPAK (SINGLE GAUGE)
SCALE 1:1
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
1
2
3
4
V
S
A
K
-T-
SEATING
PLANE
R
B
F
G
D
3 PL
M
0.13 (0.005)
T
C
E
J
H
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.35
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.090 BSC
2.29 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.350
0.380
8.89
9.65
R
0.180
0.215
4.45
5.45
S
0.025
0.040
0.63
1.01
V
0.035
0.050
0.89
1.27
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
Z
0.155
---
3.93
---
NTD14N03R
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6
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be
validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
NTD14N03R/D
Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: ONlit@hibbertco.com
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