Semiconductor Components Industries, LLC, 2005
February, 2005 - Rev. 0
1
Publication Order Number:
NTD78N03/D
NTD78N03
Power MOSFET
25 V, 78 A, Single N-Channel, DPAK
Features
Low R
DS(on)
Optimized Gate Charge
Pb-Free Packages are Available
Applications
Desktop VCORE
DC-DC Converters
Low Side Switch
MAXIMUM RATINGS
(T
J
= 25
C unless otherwise noted)
Parameter
Symbol
Value
Unit
Drain-to-Source Voltage
V
DSS
25
V
Gate-to-Source Voltage
V
GS
"
20
V
Continuous Drain
Current (Note 1)
T
A
= 25
C
I
D
14.8
A
Current (Note 1)
T
A
= 85
C
11.5
Power Dissipation
(Note 1)
T
A
= 25
C
P
D
2.3
W
Continuous Drain
Current (Note 2)
T
A
= 25
C
I
D
11.4
A
Current (Note 2)
Steady
St t
T
A
= 85
C
8.8
Power Dissipation
(Note 2)
y
State
T
A
= 25
C
P
D
1.4
W
Continuous Drain
Current (R
)
T
C
= 25
C
I
D
78
A
Current (R
q
JC
)
T
C
= 85
C
56
Power Dissipation
(R
q
JC
)
T
C
= 25
C
P
D
64
W
Pulsed Drain Current
t
p
= 10
m
s
I
DM
88
A
Current Limited by Package
T
A
= 25
C
I
DmaxPkg
32
A
Drain to Source dV/dt
dV/dt
2.0
V/ns
Operating Junction and Storage Temperature
T
J
, T
stg
- 55 to
175
C
Source Current (Body Diode)
I
S
78
A
Single Pulse Drain-to-Source Avalanche
Energy (V
DD
= 24 V, V
GS
= 10 V,
L = 5.0 mH, I
L
(pk) = 17 A, R
G
= 25
W
)
E
AS
722.5
mJ
Lead Temperature for Soldering Purposes
(1/8
from case for 10 s)
T
L
260
C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface-mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size
(Cu area = TBD in sq).
CASE 369C
DPAK
(Bend Lead)
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Y
= Year
WW
= Work Week
78N03 = Device Code
3
Source
2
Drain
4
Drain
1
Gate
3
Source
2
Drain
4
Drain
CASE 369D
DPAK
(Straight Lead)
STYLE 2
1
Gate
YWW
78
N03
YWW
78
N03
25 V
4.6 @ 10 V
R
DS(on)
TYP
78 A
I
D
MAX
V
(BR)DSS
6.5 @ 4.5 V
http://onsemi.com
1 2
3
4
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
1
2
3
4
CASE 369AC
3 IPAK
(Straight Lead)
1
2
3
4
N-Channel
D
S
G
NTD78N03
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2
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Junction-to-Case (Drain)
R
q
JC
1.95
C/W
Junction-to-Ambient - Steady State (Note 3)
R
q
JA
65
C/
Junction-to-Ambient - Steady State (Note 4)
R
q
JA
110
ELECTRICAL CHARACTERISTICS
(T
J
= 25
C unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage
V
(BR)DSS
V
GS
= 0 V, I
D
= 250
m
A
25
V
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V
(BR)DSS
/T
J
24
mV/
C
Zero Gate Voltage Drain Current
I
DSS
V
GS
= 0 V,
T
J
= 25
C
1.5
m
A
V
GS
0 V,
V
DS
= 20 V
T
J
= 125
C
10
Gate-to-Source Leakage Current
I
GSS
V
DS
= 0 V, V
GS
=
"
20 V
"
100
nA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= 250
m
A
1.0
1.6
3.0
V
Negative Threshold Temperature Coefficient
V
GS(TH)
/T
J
-5.0
mV/
C
Drain-to-Source On Resistance
R
DS(on)
V
GS
= 10 V, I
D
= 78 A
4.6
6.0
m
W
(
)
V
GS
= 4.5 V, I
D
= 36 A
6.5
7.8
Forward Transconductance
gFS
V
DS
= 10 V, I
D
= 15 A
22
S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
C
iss
V
0 V f
1 0 MH
1920
pF
Output Capacitance
C
oss
V
GS
= 0 V, f = 1.0 MHz,
V
DS
= 12 V
960
Reverse Transfer Capacitance
C
rss
V
DS
= 12 V
420
Total Gate Charge
Q
G(TOT)
25.5
35
nC
Threshold Gate Charge
Q
G(TH)
V
GS
= 4.5 V, V
DS
= 20 V,
2.4
Gate-to-Source Charge
Q
GS
V
GS
4.5 V, V
DS
20 V,
I
D
= 20 A
5.3
Gate-to-Drain Charge
Q
GD
18.2
SWITCHING CHARACTERISTICS (Note 6)
Turn-On Delay Time
t
d(on)
11
ns
Rise Time
t
r
V
GS
= 4.5 V, V
DS
= 20 V,
68
Turn-Off Delay Time
t
d(off)
V
GS
4.5 V, V
DS
20 V,
I
D
= 20 A, R
G
= 3.0
W
23
Fall Time
t
f
42
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
V
GS
= 0 V,
T
J
= 25
C
0.83
1.0
V
V
GS
0 V,
I
S
= 20 A
T
J
= 125
C
0.7
Reverse Recovery Time
t
RR
39
ns
Charge Time
ta
V
GS
= 0 V, dIs/d
t
= 100 A/
m
s,
17.8
Discharge Time
tb
V
GS
0 V, dIs/d
t
100 A/
m
s,
I
S
= 20 A
21
Reverse Recovery Time
Q
RR
33
nC
3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
4. Surface-mounted on FR4 board using the minimum recommended pad size (Cu area = TBD in sq).
5. Pulse Test: Pulse Width
300
m
s, Duty Cycle
2%.
6. Switching characteristics are independent of operating junction temperatures.
NTD78N03
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3
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
3
2
1.5
0.5
0
1000
10000
100000
0.005
0
30
8
6
4
I
D
, DRAIN CURRENT (AMPS)
0
V
GS
, GATE-TO-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
I
D
, DRAIN CURRENT (AMPS)
10
0.01
0.005
0.002
0.001
40
0
20
60
70
80
Figure 3. On-Resistance versus
Drain Current and Temperature
I
D
, DRAIN CURRENT (A)
Figure 4. On-Resistance versus Drain Current
and Gate Voltage
I
D
, DRAIN CURRENT (A)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
)
Figure 5. On-Resistance Variation with
Temperature
T
J
, JUNCTION TEMPERATURE (
C)
Figure 6. Drain-To-Source Leakage
Current versus Voltage
V
DS
, DRAIN-TO-SOURCE VOLTAGE (V)
I
DSS
, LEAKAGE (nA)
50
-50
100
75
0
-25
125
175
0
3
6
55
0
0.01
0.015
5
20
15
10
25
V
DS
, DRAIN-TO-SOURCE VOLTAGE (V)
10
20
40
10
V
GS
= 0 V
T
J
= 125
C
T
J
= 150
C
V
GS
= 4.5 V
V
GS
= 10 V
T
J
= 25
C
V
GS
= 10 V
V
DS
10 V
T
J
= 25
C
T
J
= -55
C
T
J
= 125
C
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE
(NORMALIZED)
T
J
= 25
C
50
25
4
5
2
V
GS
= 4 V
2.6 V
3.2 V
3.4 V
3.6 V
3.8 V
3 V
4.5 V
5 V
0.004
0.003
0.006
60
65
70
75
80
60
90
80
100
70
9 V
0
2.5
1
I
D
= 78 A
V
DS
= 4.5 V
100
10
2
1
50
30
T
J
= 25
C
0.007
0.008
0.009
T
J
= -55
C
T
J
= 125
C
150
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4
10
20
30
40
50
60
70
80
0.5
0.6
0.7
0.8
0.9
1.1
1.2
10
5
0
5
10
15
20
25
V
GS
V
DS
4
8
6
0
2000
C, CAP
ACIT
ANCE (pF)
0
Q
g
, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and
Drain-to-Source Voltage versus Total Charge
V
GS
, GA
TE-T
O-SOURCE VOL
T
AGE (V)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
V
SD
, SOURCE-TO-DRAIN VOLTAGE (V)
I
S
, SOURCE CURRENT (AMPS)
6000
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (V)
1000
4000
2
I
D
= 20 A
T
J
= 25
C
Q
1
V
GS
= 0 V
T
J
= 25
C
V
GS
= 0 V
T
J
= 25
C
C
rss
C
iss
C
oss
3000
0
5
10
15
20
25
30
35
Q
2
Q
T
Figure 10. Diode Forward Voltage versus Current
R
G
, GATE RESISTANCE (OHMS)
1
10
100
1000
1
t, TIME
(ns)
100
t
r
t
d(off)
t
d(on)
t
f
10
V
DS
= 20 V
I
D
= 20 A
V
GS
= 4.5 V
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.1
1
100
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.1
1000
I D
, DRAIN CURRENT
(AMPS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
10
V
GS
= 20 V
SINGLE PULSE
T
C
= 25
C
1 ms
100
m
s
10 ms
dc
10
m
s
100
200
300
400
500
600
700
800
25
50
75
100
125
150
175
T
J
, STARTING JUNCTION TEMPERATURE (
C)
EAS, SINGLE PULSE DRAIN-T
O-
SOURCE A
V
ALANCHE ENERGY (mJ)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
I
D
= 78 A
5000
C
rss
C
iss
V
DS
= 0 V
V
GS
V
DS
V
DS
, DRAIN-T
O-SOURCE VOL
T
AGE (V)
0
5
10
15
20
0
1.0
1
100
0
NTD78N03
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5
di/dt
t
rr
t
a
t
p
I
S
0.25 I
S
TIME
I
S
t
b
Figure 13. Diode Reverse Recovery Waveform
R
JA
(t) = r(t) R
JA
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
- T
A
= P
(pk)
R
JA
(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t
1
/t
2
Figure 14. Thermal Response - Various Duty Cycles
t, TIME (seconds)
Rthja(t)
, EFFECTIVE
TRANSIENT
THERMAL
RESIST
ANCE
1000
1
D = 0.5
1E-05
1E-03
1E-02
1E-01
0.2
0.01
0.01
0.02
0.05
0.1
1E+00
1E+01
1E+03
SINGLE PULSE
1E-04
1E+02
MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT
DUTY CYCLE
100
10
0.1
ORDERING INFORMATION
Order Number
Package
Shipping
NTD78N03
DPAK
75 Units/Rail
NTD78N03T4
DPAK
2500 Tape & Reel
NTD78N03T4G
DPAK
(Pb-Free)
2500 Tape & Reel
NTD78N03-1
DPAK Straight Lead
75 Units/Rail
NTD78N03-1G
DPAK Straight Lead
(Pb-Free)
75 Units/Rail
NTD78N03-35
DPAK-3 Straight Lead
(3.5
"
0.15 mm)
75 Units/Rail
NTD78N03-35G
DPAK-3 Straight Lead
(3.5
"
0.15 mm)
(Pb-Free)
75 Units/Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NTD78N03
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6
PACKAGE DIMENSIONS
DPAK
CASE 369C-01
ISSUE O
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
D
A
K
B
R
V
S
F
L
G
2 PL
M
0.13 (0.005)
T
E
C
U
J
H
-T-
SEATING
PLANE
Z
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.22
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.180 BSC
4.58 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.102
0.114
2.60
2.89
L
0.090 BSC
2.29 BSC
R
0.180
0.215
4.57
5.45
S
0.025
0.040
0.63
1.01
U
0.020
---
0.51
---
V
0.035
0.050
0.89
1.27
Z
0.155
---
3.93
---
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
1
2
3
4
NTD78N03
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7
PACKAGE DIMENSIONS
DPAK
CASE 369D-01
ISSUE B
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
1
2
3
4
V
S
A
K
-T-
SEATING
PLANE
R
B
F
G
D
3 PL
M
0.13 (0.005)
T
C
E
J
H
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.35
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.090 BSC
2.29 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.350
0.380
8.89
9.65
R
0.180
0.215
4.45
5.45
S
0.025
0.040
0.63
1.01
V
0.035
0.050
0.89
1.27
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
Z
0.155
---
3.93
---
NTD78N03
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8
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC-01
ISSUE O
D
A
K
B
R
V
F
G
3 PL
E
C
J
H
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.22
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.043
0.94
1.09
G
0.090 BSC
2.29 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.134
0.142
3.40
3.60
R
0.180
0.215
4.57
5.46
V
0.035
0.050
0.89
1.27
W
0.000
0.010
0.000
0.25
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
W
SEATING PLANE
0.13 (0.005) W
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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NTD78N03/D
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