Semiconductor Components Industries, LLC, 2004
September, 2004 - Rev. 6
1
Publication Order Number:
NTD85N02R/D
NTD85N02R
Power MOSFET
85 Amps, 24 Volts
N-Channel DPAK
Features
Pb-Free Packages are Available
Planar HD3e Process for Fast Switching Performance
Low R
DS(on)
to Minimize Conduction Loss
Low C
iss
to Minimize Driver Loss
Low Gate Charge
MAXIMUM RATINGS
(T
J
= 25
C Unless otherwise specified)
Parameter
Symbol
Value
Unit
Drain-to-Source Voltage
V
DSS
24
V
dc
Gate-to-Source Voltage - Continuous
V
GS
20
V
dc
Thermal Resistance - Junction-to-Case
Total Power Dissipation @ T
C
= 25
C
Drain Current
Continuous @ T
C
= 25
C, Limited by Package
Continuous @ T
A
= 25
C, Limited by Wires
Single Pulse (t
p
10
m
s)
R
q
JC
P
D
I
D
I
D
I
DM
1.6
78.1
85
32
96
C/W
W
A
A
A
Thermal Resistance, Junction-to-Ambient
(Note 1)
Total Power Dissipation @ T
A
= 25
C
Drain Current - Continuous @ T
A
= 25
C
R
q
JA
P
D
I
D
52
2.4
16
C/W
W
A
Thermal Resistance, Junction-to-Ambient
(Note 2)
Total Power Dissipation @ T
A
= 25
C
Drain Current - Continuous @ T
A
= 25
C
R
q
JA
P
D
I
D
100
1.25
12
C/W
W
A
Operating and Storage Temperature Range
T
J
, T
stg
-55 to
150
C
Single Pulse Drain-to-Source Avalanche
Energy - Starting T
J
= 25
C
(V
DD
= 30 V
dc
, V
GS
= 10 V
dc
, I
L
= 13 A
pk
,
L = 1 mH, R
G
= 25
W
)
E
AS
85
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8
from Case for 10 Seconds
T
L
260
C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in
2
).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in
2
).
D
S
G
N-Channel
V
DSS
R
DS(ON)
TYP
I
D
MAX
24 V
4.8 m
W
85 A
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
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MARKING DIAGRAM
& PIN ASSIGNMENTS
DPAK
CASE 369C
STYLE2
DPAK-3
CASE 369D
STYLE 2
1 2
3
4
1
2
3
4
Y
= Year
WW
= Work Week
85N02R = Specific Device Code
YWW
85
N02
4
1 Gate
2 Drain
3 Source
4 Drain
1
3
2
1
3
2
4
YWW
85
N02
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2
ELECTRICAL CHARACTERISTICS
(T
J
= 25
C Unless otherwise specified)
Characteristics
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage (Note 3)
(V
GS
= 0 V
dc
, I
D
= 250
m
A
dc
)
Temperature Coefficient (Positive)
V
(br)DSS
24
-
28
20.5
-
-
V
dc
mV/
C
Zero Gate Voltage Drain Current
(V
DS
= 20 V
dc
, V
GS
= 0 V
dc
)
(V
DS
= 20 V
dc
, V
GS
= 0 V
dc
, T
J
= 150
C)
I
DSS
-
-
-
-
1.5
10
m
A
dc
Gate-Body Leakage Current
(V
GS
=
20 V
dc
, V
DS
= 0 V
dc
)
I
GSS
-
-
100
nA
dc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(V
DS
= V
GS
, I
D
= 250
m
A
dc
)
Threshold Temperature Coefficient (Negative)
V
GS(th)
1.0
-
1.5
4.0
2.0
-
V
dc
mV/
C
Static Drain-to-Source On-Resistance (Note 3)
(V
GS
= 4.5 V
dc
, I
D
= 20 A
dc
)
(V
GS
= 10 V
dc
, I
D
= 20 A
dc
)
R
DS(on)
-
-
6.5
4.8
-
5.2
m
W
Forward Transconductance (Note 3)
(V
DS
= 10 V
dc
, I
D
= 15 A
dc
)
g
FS
-
38
-
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
-
2050
-
pF
Output Capacitance
(V
DS
= 20 V
dc
, V
GS
= 0 V,
f = 1 MHz)
C
oss
-
871
-
Transfer Capacitance
f = 1 MHz)
C
rss
-
359
-
SWITCHING CHARACTERISTICS (Note 4)
Turn-On Delay Time
t
d(on)
-
6.3
-
ns
Rise Time
(V
GS
= 10 V
dc
, V
DD
= 10 V
dc
,
t
r
-
77
-
Turn-Off Delay Time
(V
GS
= 10 V
dc
, V
DD
= 10 V
dc
,
I
D
= 30 A
dc
, R
G
= 3
W
)
t
d(off)
-
25
-
Fall Time
t
f
-
12
-
Gate Charge
Q
T
-
17.7
-
nC
(V
GS
= 5 V
dc
, I
D
= 10 A
dc
,
V
DS
= 10 V
dc
) (Note 3)
Q
1
-
2.6
-
V
DS
= 10 V
dc
) (Note 3)
Q
2
-
7.1
-
SOURCE-DRAIN DIODE CHARACTERISTICS
Forward On-Voltage
V
SD
V
dc
Forward On-Voltage
(I
S
= 10 A
dc
, V
GS
= 0 V
dc
) (Note 3)
(I
10 A
V
0 V
T
125
C)
V
SD
-
0.78
0 63
1.0
V
dc
(
S
dc
,
GS
dc
) (
)
(I
S
= 10 A
dc
, V
GS
= 0 V
dc
, T
J
= 125
C)
-
0.63
-
Reverse Recovery Time
t
rr
-
37.5
-
ns
(I
S
= 20 A
dc
, V
GS
= 0 V
dc
,
t
a
-
16.8
-
(I
S
= 20 A
dc
, V
GS
= 0 V
dc
,
dI
S
/dt = 100 A/
m
s) (Note 3)
t
b
-
20.7
-
Reverse Recovery Stored Charge
Q
RR
-
0.027
-
m
C
3. Pulse Test: Pulse Width
300
m
s, Duty Cycle
2%.
4. Switching characteristics are independent of operating junction temperatures.
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3
3 V
10 V
0
0.018
40
0.014
0.006
0.002
160
1.6
1.2
1.4
1.0
0.8
0.6
10,000
100,000
0
10
40
4
2
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
0
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
I
D
, DRAIN CURRENT (AMPS)
0
0.018
40
0.010
0.006
0.002
80
Figure 3. On-Resistance versus Drain Current
and Temperature
I
D
, DRAIN CURRENT (AMPS)
Figure 4. On-Resistance versus Drain Current
and Temperature
I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
W
)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
W
)
Figure 5. On-Resistance Variation with
Temperature
T
J
, JUNCTION TEMPERATURE (
C)
Figure 6. Drain-to-Source Leakage Current
versus Voltage
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE
(NORMALIZED)
I
DSS
, LEAKAGE (nA)
-50
50
25
0
-25
75
125
100
2
3
0
15
10
25
5
6
V
DS
10 V
T
J
= 25
C
T
J
= -55
C
T
J
= 125
C
V
GS
= 10 V
V
GS
= 4.5 V
150
V
GS
= 0 V
I
D
= 40 A
V
GS
= 10 V
80
V
GS
= 4 V
T
J
= 25
C
T
J
= -55
C
T
J
= 125
C
T
J
= 150
C
T
J
= 125
C
40
0
160
80
4
5
T
J
= 25
C
T
J
= -55
C
20
100
6 V
3.2 V
5 V
1.8
6
1000
8
120
1
0
120
120
160
0.014
T
J
= 125
C
80
0.010
120
2.8 V
2.6 V
2.4 V
4.4 V
3.4 V
3.6 V
3.8 V
160
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4
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain-gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
- V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn-on and turn-off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
- V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off-state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on-state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
C
rss
10
0
10
15
20
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
Figure 7. Capacitance Variation
4800
1600
0
V
GS
V
DS
2400
800
5
5
V
GS
= 0 V
V
DS
= 0 V
T
J
= 25
C
C
iss
C
oss
C
rss
C
iss
3200
4000
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5
V
GS
80
0
0
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
V
SD
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 8. Gate-To-Source and Drain-To-Source
Voltage versus Total Charge
I S
, SOURCE CURRENT
(AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
R
G
, GATE RESISTANCE (OHMS)
1
10
100
1000
1
t, TIME
(ns)
V
GS
= 0 V
Figure 10. Diode Forward Voltage versus Current
V
GS
, GA
TE-T
O-SOURCE VOL
T
AGE (VOL
TS)
0
2
0
Q
G
, TOTAL GATE CHARGE (nC)
6
4
12
100
4
8
0.2
0.4
1.0
10
20
30
I
D
= 10 A
T
J
= 25
C
Q
2
Q
1
Q
T
t
r
t
d(off)
t
d(on)
t
f
10
V
DS
= 10 V
I
D
= 40 A
V
GS
= 10 V
0.6
0.8
20
40
60
50
T
J
= 25
C
16
70
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain-to-source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25
C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal Resistance -
General Data and Its Use."
Switching between the off-state and the on-state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
ms. In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
- T
C
)/(R
qJC
).
A Power MOSFET designated E-FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non-linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E-FETs can withstand the stress of
drain-to-source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous I
D
can safely be assumed to
equal the values indicated.
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6
SAFE OPERATING AREA
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.1
1
100
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
1
100
I D
, DRAIN CURRENT
(AMPS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
10
V
GS
= 20 V
SINGLE PULSE
T
C
= 25
C
1 ms
100
m
s
10 ms
dc
10
m
s
Figure 12. Thermal Response
10
0.1
0.01
0.00001
0.0001
r(t)
, EFFECTIVE TRANSIENT THERMAL RESIST
ANCE
(NORMALIZED)
t, TIME (s)
1
0.001
0.01
0.1
1
10
Normalized to R
q
JC
at Steady State
NTD85N02R
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7
10
0.1
0.01
0.00001
0.0001
r(t)
, EFFECTIVE TRANSIENT THERMAL RESPONSE
(NORMALIZED)
t, TIME (s)
1
0.001
0.01
0.1
1
10
100
1000
Figure 13. Thermal Response
Normalized to R
q
JA
at Steady State,
1
square Cu Pad, Cu Area 1.127 in
2
,
3 x 3 inch FR4 board
ORDERING INFORMATION
Device
Package
Shipping
NTD85N02R
DPAK
NTD85N02RG
DPAK
(Pb-Free)
75 Units / Rail
NTD85N02R-001
DPAK-3
800 Tape & Reel
NTD85N02R-1G
DPAK-3
(Pb-Free)
800 Tape & Reel
NTD85N02RT4
DPAK
2500 Tape & Reel
NTD85N02RT4G
DPAK
(Pb-Free)
2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE O
D
A
K
B
R
V
S
F
L
G
2 PL
M
0.13 (0.005)
T
E
C
U
J
H
-T-
SEATING
PLANE
Z
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.22
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.180 BSC
4.58 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.102
0.114
2.60
2.89
L
0.090 BSC
2.29 BSC
R
0.180
0.215
4.57
5.45
S
0.025
0.040
0.63
1.01
U
0.020
---
0.51
---
V
0.035
0.050
0.89
1.27
Z
0.155
---
3.93
---
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
1
2
3
4
5.80
0.228
2.58
0.101
1.6
0.063
6.20
0.244
3.0
0.118
6.172
0.243
mm
inches
SCALE 3:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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9
PACKAGE DIMENSIONS
DPAK-3
CASE 369D-01
ISSUE B
1
2
3
4
V
S
A
K
-T-
SEATING
PLANE
R
B
F
G
D
3 PL
M
0.13 (0.005)
T
C
E
J
H
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.235
0.245
5.97
6.35
B
0.250
0.265
6.35
6.73
C
0.086
0.094
2.19
2.38
D
0.027
0.035
0.69
0.88
E
0.018
0.023
0.46
0.58
F
0.037
0.045
0.94
1.14
G
0.090 BSC
2.29 BSC
H
0.034
0.040
0.87
1.01
J
0.018
0.023
0.46
0.58
K
0.350
0.380
8.89
9.65
R
0.180
0.215
4.45
5.45
S
0.025
0.040
0.63
1.01
V
0.035
0.050
0.89
1.27
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
Z
0.155
---
3.93
---
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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P.O. Box 61312, Phoenix, Arizona 85082-1312 USA
Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada
Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
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