Semiconductor Components Industries, LLC, 2004
October, 2004 - Rev. 1
1
Publication Order Number:
NTHS4101P/D
NTHS4101P
Power MOSFET
-20 V, 6.7 A, P-Channel ChipFET
t
Features
Offers an Ultra Low R
DS(on)
Solution in the ChipFET Package
Miniature ChipFET Package 40% Smaller Footprint than TSOP-6
making it an Ideal Device for Applications where Board Space is at a
Premium
Low Profile (<1.1 mm) Allows it to Fit Easily into Extremely Thin
Environments such as Portable Electronics
Designed to Provide Low R
DS(on)
at Gate Voltage as Low as 1.8 V, the
Operating Voltage used in many Logic ICs in Portable Electronics
Simplifies Circuit Design since Additional Boost Circuits for Gate
Voltages are not Required
Operated at Standard Logic Level Gate Drive, Facilitating Future
Migration to Lower Levels using the same Basic Topology
Pb-Free Package is Available
Applications
Optimized for Battery and Load Management Applications in
Portable Equipment such as MP3 Players, Cell Phones, Digital
Cameras, Personal Digital Assistant and other Portable Applications
Charge Control in Battery Chargers
Buck and Boost Converters
MAXIMUM RATINGS
(T
J
= 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain-to-Source Voltage
V
DSS
-20
Vdc
Gate-to-Source Voltage - Continuous
V
GS
"
8.0
Vdc
Drain Current - Continuous
- 5 seconds
I
D
I
D
-4.8
-6.7
A
Total Power Dissipation
Continuous @ T
A
= 25
C
(5 sec) @ T
A
= 25
C
Continuous @ 85
C
(5 sec) @ 85
C
P
D
1.3
2.5
0.7
1.3
W
Continuous Source Current
Is
-4.8
A
Thermal Resistance (Note 1)
Junction-to-Ambient, 5 sec
Junction-to-Ambient, Continuous
R
q
JA
R
q
JA
50
95
C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8
from case for 10 seconds
T
L
260
C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq
[1 oz] including traces).
G
S
D
P-Channel MOSFET
Device
Package
Shipping
ORDERING INFORMATION
NTHS4101PT1
ChipFET
3000 Tape / Reel
http://onsemi.com
-20 V
30 m
W
@ -2.5 V
21 m
W
@ -4.5 V
R
DS(on)
TYP
-6.7 A
I
D
MAX
V
(BR)DSS
42 m
W
@ -1.8 V
NTHS4101PT1G
ChipFET
(Pb-free)
3000 Tape / Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
S
D
G
D
D
D
D
D
1
2
3
4
5
6
7
8
PIN
CONNECTIONS
ChipFET
CASE 1206A
STYLE 1
MARKING
DIAGRAM
C6
M
C6 = Specific Device Code
M = Month Code
1
2
3
4
8
7
6
5
NTHS4101P
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2
ELECTRICAL CHARACTERISTICS
(T
J
= 25
C unless otherwise noted)
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage (Note 2)
Temperature Coefficient (Positive)
V
(Br)DSS
V
GS
= 0 V
dc
, I
D
= -250
m
A
dc
-20
V
dc
Gate-Body Leakage Current Zero
I
GSS
V
DS
= 0 V
dc
, V
GS
=
"
8.0 V
dc
"
100
nA
dc
Zero Gate Voltage Drain Current
I
DSS
V
DS
= -16 V
dc
, V
GS
= 0 V
dc
V
DS
= -16 V
dc
, V
GS
= 0 V
dc
,
T
J
= 85
C
-1.0
-5.0
m
A
dc
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
V
GS(th)
V
DS
= V
GS
, I
D
= -250
m
A
dc
-0.45
-1.5
V
dc
Static Drain-to-Source On-Resistance
R
DS(on)
V
GS
= -4.5 V
dc
, I
D
= -4.8 A
dc
V
GS
= -2.5 V
dc
, I
D
= -4.2 A
dc
V
GS
= -1.8 V
dc
, I
D
= -1.0 A
dc
21
30
42
34
40
52
m
W
Forward Transconductance
g
FS
V
DS
= -5.0 V
dc
, I
D
= -4.8 A
dc
15
S
Diode Forward Voltage
V
SD
I
S
= -4.8 A
dc
, V
GS
= 0 V
dc
-0.8
-1.2
V
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
V
DS
= -16 V
dc
V
V
2100
pF
Output Capacitance
C
oss
V
GS
= 0 V
f = 1 0 MHz
290
Transfer Capacitance
C
rss
f = 1.0 MHz
200
SWITCHING CHARACTERISTICS (Note 3)
Turn-On Delay Time
t
d(on)
V
DD
= -16 V
dc
8.0
ns
Rise Time
t
r
V
GS
= -4.5 V
dc
28
Turn-Off Delay Time
t
d(off)
I
D
= -4.5 A
dc
75
Fall Time
t
f
R
G
= 2.5
W
60
Gate Charge
Q
g
V
GS
= -4.5 V
dc
25
35
nC
Q
gs
I
D
= -4.5 A
dc
4.0
Q
gd
V
DS
= -16 V
dc
(Note 3)
7.0
2. Pulse Test: Pulse Width = 250
m
s, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperatures.
NTHS4101P
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3
TYPICAL PERFORMANCE CURVES
(T
J
= 25
C unless otherwise noted)
125
C
0
10
5
8
6
3
2
-V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
-I
D,
DRAIN CURRENT (AMPS)
6
2
0
1
Figure 1. On-Region Characteristics
0
10
1.5
1
2
6
4
2
0.5
0
2.5
Figure 2. Transfer Characteristics
-V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
0.02
8
10
0.04
0
Figure 3. On-Resistance vs. Drain Current and
Gate Voltage
-I
D,
DRAIN CURRENT (AMPS)
R
DS(on),
DRAIN-T
O-SOURCE
RESIST
ANCE (
W
)
-I
D,
DRAIN CURRENT (AMPS)
Figure 4. On-Resistance Variation with
Temperature
T
J
, JUNCTION TEMPERATURE (
C)
Figure 5. Drain-to-Source Leakage Current
vs. Voltage
T
J
= 25
C
0.1
2
4
T
J
= -55
C
T
J
= 25
C
V
GS
= -4.5 V
4
25
C
-1.2 V
16
-1.4 V
-1.6 V
-1.8 V
7
8
0.06
V
GS
= -10 V to -2.4 V
0
8
10
-V
DS,
DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10000
0.1
-I
DSS
, LEAKAGE (nA)
V
GS
= -4.5 V
1000
1
100
V
GS
= -2.5 V
4
6
4
8
0.08
6
T
J
= 100
C
T
J
= 125
C
2
9
7
5
1
3
3
9
5
3
1
7
14
12
V
GS
= -1.8 V
-50
0
-25
25
1.3
1.1
0.9
0.7
0.5
50
125
100
75
150
R
DS(on),
DRAIN-T
O-SOURCE
RESIST
ANCE (NORMALIZED)
1.5
V
GS
= 0 V
NTHS4101P
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4
TYPICAL PERFORMANCE CURVES
(T
J
= 25
C unless otherwise noted)
V
DS
= 0 V
V
GS
= 0 V
0
10
4
3000
2000
1000
0
8
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
0
9
6
4
1
0
Q
g
, TOTAL GATE CHARGE (nC)
-V
GS
,
GA
TE-T
O-SOURCE
VOL
T
AGE (VOL
TS)
T
J
= 25
C
C
oss
C
iss
C
rss
I
D
= -4.5 A
T
J
= 25
C
5000
18
15
2
3
Q2
Q1
10
1
10
1
100
R
G
, GATE RESISTANCE (OHMS)
t, TIME (ns)
V
DD
= -16 V
I
D
= -4.5 A
V
GS
= -4.5 V
1000
-6
-2
4000
5
t
d(off)
t
d(on)
t
f
t
r
-V
GS
-V
DS
6
12
3
27
0.9
0
-V
SD
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
-I
S
, SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25
C
1.0
0.5
0.4
1
5
Figure 6. Capacitance Variation
Figure 7. Gate-to-Source and Drain-to-Source
Voltage vs. Total Gate Charge
Figure 8. Resistive Switching Time Variation
vs. Gate Resistance
Figure 9. Diode Forward Voltage vs. Current
Figure 10. Maximum Rated Forward Biased
Safe Operating Area
0.1
1
100
-V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.01
100
-I
D
, DRAIN CURRENT
(AMPS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
10
10
V
GS
= -8 V
SINGLE PULSE
T
C
= 25
C
1 ms
100
m
s
dc
10
m
s
2
-4
3500
2500
1500
500
4500
24
21
QT
100
0.6
0.8
0.7
0.1
1
12 14 16 18 20
2
3
4
NTHS4101P
http://onsemi.com
5
PACKAGE DIMENSIONS
ChipFET
CASE 1206A-03
ISSUE E
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
B
S
C
D
G
L
A
1
2
3
4
8
7
6
5
M
J
K
1
2
3
4
8
7
6
5
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
2.95
3.10
0.116
0.122
B
1.55
1.70
0.061
0.067
C
1.00
1.10
0.039
0.043
D
0.25
0.35
0.010
0.014
G
0.65 BSC
0.025 BSC
J
0.10
0.20
0.004
0.008
K
0.28
0.42
0.011
0.017
L
0.55 BSC
0.022 BSC
M
5 NOM
S
1.80
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A-01 AND 1206A-02 OBSOLETE. NEW
STANDARD IS 1206A-03.
0.05 (0.002)
5 NOM
2.00
0.072
0.080
Basic
Style 1
mm
inches
0.178
0.007
2.032
0.08
1.727
0.068
0.66
0.026
0.711
0.028
0.457
0.018
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028
mm
inches
SCALE 20:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINTS*
NTHS4101P
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6
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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NTHS4101P/D
ChipFET is a trademark of Vishay Siliconix.
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