Semiconductor Components Industries, LLC, 2004
April, 2004 - Rev. 0
1
Publication Order Number:
NTHS4111P/D
NTHS4111P
Power MOSFET
-30 V, -6.1 A, Single P-Channel, ChipFET
t
Features
Offers an Ultra Low R
DS(on)
Solution in the ChipFET Package
ChipFET Package 40% Smaller Footprint than TSOP-6
Low Profile (<1.1 mm) for Extremely Thin Environments
Standard Logic Level Gate Drive
Applications
Notebook Computer Load Switch
Battery and Load Management Applications in Portable Equipment
Charge Control in Battery Chargers
Buck and Boost Converters
MAXIMUM RATINGS
(T
J
= 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain-to-Source Voltage
V
DSS
-30
V
Gate-to-Source Voltage
V
GS
20
V
Continuous Drain
Current (Note 1)
Steady
State
T
A
= 25
C
I
D
-4.4
A
Current (Note 1)
State
T
A
= 85
C
-3.2
t
10 s
T
A
= 25
C
-6.1
Power Dissipation
(Note 1)
Steady
State
T
A
= 25
C
P
D
1.3
W
t
10 s
2.5
Continuous Drain
Current (Note 2)
Steady
State
T
A
= 25
C
I
D
-3.3
A
Current (Note 2)
State
T
A
= 85
C
-2.3
Power Dissipation
(Note 2)
T
A
= 25
C
P
D
0.7
W
Pulsed Drain Current
tp
= 10
m
s
I
DM
-30
A
Operating Junction and Storage Temperature
T
J
,
T
STG
-55 to
150
C
Source Current (Body Diode)
I
S
-2.1
A
Lead Temperature for Soldering Purposes
(1/8
from case for 10 s)
T
L
260
C
THERMAL RESISTANCE RATINGS
Rating
Symbol
Max
Unit
Junction-to-Ambient Steady State (Note 1)
R
JA
95
C/W
Junction-to-Ambient t
10 s (Note 1)
R
JA
50
Junction-to-Ambient Steady State (Note 2)
R
JA
175
1. Surface-mounted on FR4 board using 1 inch sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.045 in sq).
G
S
D
P-Channel MOSFET
S
D
G
D
D
D
D
D
1
2
3
4
5
6
7
8
Device
Package
Shipping
ORDERING INFORMATION
NTHS4111PT1
ChipFET
3000 Tape / Reel
PIN
CONNECTIONS
ChipFET
CASE 1206A
Style 1
MARKING
DIAGRAM
TH d
1
2
3
4
8
7
6
5
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NTHS4111PT1G
ChipFET
(Pb-free)
3000 Tape / Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
TH = Specific Device Code
d
= Date Code
-30 V
52 m
W
@ -4.5 V
33 m
W
@ -10 V
R
DS(on)
TYP
-6.1 A
I
D
MAX
V
(BR)DSS
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2
ELECTRICAL CHARACTERISTICS
(T
J
= 25
C unless otherwise noted)
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage
V
(BR)DSS
V
GS
= 0 V, I
D
= -250
m
A
-30
V
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V
(BR)DSS
/T
J
-19
mV/
C
Zero Gate Voltage Drain Current
I
DSS
V
GS
= 0 V,
T
J
= 25
C
-1.0
m
A
V
GS
= 0 V,
V
DS
= -24 V
T
J
= 125
C
-100
Gate-to-Source Leakage Current
I
GSS
V
DS
= 0 V, V
GS
=
20 V
100
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
V
GS(TH)
V
GS
= V
DS
, I
D
= -250
m
A
-1.0
-1.7
-3.0
V
Negative Threshold Temperature Coefficient
V
GS(TH)
/T
J
5.0
mV/
C
Drain-to-Source On Resistance
R
DS(on)
V
GS
= -10 V, I
D
= -4.4 A
33
45
m
W
(
)
V
GS
= -4.5 V, I
D
= -3.4 A
52
75
Forward Transconductance
g
FS
V
DS
= -15 V, I
D
= -4.4 A
7.7
S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
C
ISS
V
0 V f
1 0 MH
882
1500
pF
Output Capacitance
C
OSS
V
GS
= 0 V, f = 1.0 MHz,
V
DS
= -24 V
143
Reverse Transfer Capacitance
C
RSS
V
DS
= -24 V
105
Total Gate Charge
Q
G(TOT)
V
10 V V
15 V
18.2
28
nC
Gate-to-Source Charge
Q
GS
V
GS
= -10 V, V
DD
= -15 V,
I
D
= -4.4 A
2.95
Gate-to-Drain Charge
Q
GD
I
D
= -4.4 A
4.25
SWITCHING CHARACTERISTICS, V
GS
= -10 V (Note 4)
Turn-On Delay Time
t
d(ON)
9.0
18
ns
Rise Time
t
r
V
GS
= -10 V, V
DD
= -15 V,
8.0
16
Turn-Off Delay Time
t
d(OFF)
V
GS
= -10 V, V
DD
= -15 V,
I
D
= -1.0 A, R
G
= 6.0
W
45
90
Fall Time
t
f
26
52
SWITCHING CHARACTERISTICS, V
GS
= -4.5 V (Note 4)
Turn-On Delay Time
t
d(ON)
11
ns
Rise Time
t
r
V
GS
= -4.5 V, V
DD
= -15 V,
14
Turn-Off Delay Time
t
d(OFF)
V
GS
= -4.5 V, V
DD
= -15 V,
I
D
= -1.0 A, R
G
= 6.0
W
32
Fall Time
t
f
23
DRAIN - SOURCE DIODE CHARACTERISTICS
Characteristic
Symbol
Test Condition
Min
Typ
Max
Unit
Forward Diode Voltage
V
SD
V
GS
= 0 V,
T
J
= 25
C
-0.76
-1.2
V
V
GS
= 0 V,
I
S
= -1.1 A
T
J
= 125
C
-0.60
Reverse Recovery Time
t
RR
27
54
ns
Charge Time
t
a
V
GS
= 0
V
10
Discharge Time
t
b
V
GS
= 0
V
dI
S
/dt = 100 A/
m
s, I
S
= -1.1 A
17
Reverse Recovery Charge
Q
RR
12
nC
3. Pulse Test: pulse width
v
300
m
s, duty cycle
v
2%.
4. Switching characteristics are independent of operating junction temperatures.
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TYPICAL PERFORMANCE CURVES
(T
J
= 25
C unless otherwise noted)
0
0.050
0.100
1
2
3
4
5
6
7
8
9
10
11
12
0.075
0.025
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
GS
= -10 V to -5.0 V
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
11
12
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-55
C
-V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
-I
D,
DRAIN CURRENT (AMPS)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
-V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 3. R
DS(on)
vs. V
GS
-I
D,
DRAIN CURRENT (AMPS)
Figure 4. On-Resistance vs. Drain Current and
Gate Voltage
-50
0
-25
25
50
125
100
Figure 5. On-Resistance Variation with
Temperature
T
J
, JUNCTION TEMPERATURE (
C)
T
J
= 25
C
T
J
= 100
C
75
150
I
D
= -4.4 A
V
GS
= -10 V
R
DS(on),
DRAIN-T
O-SOURCE
RESIST
ANCE (NORMALIZED)
25
C
-3.4 V
Figure 6. Drain-to-Source Leakage Current
vs. Voltage
-V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
-I
DSS
, LEAKAGE (nA)
-3.2 V
V
DS
= -15 V
-3.0 V
-3.6 V
-V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
R
DS(on),
DRAIN-T
O-SOURCE
RESIST
ANCE (
W
)
-I
D,
DRAIN CURRENT (AMPS)
I
D
= -4.4 A
T
J
= 25
C
R
DS(on),
DRAIN-T
O-SOURCE
RESIST
ANCE (
W
)
T
J
= 25
C
V
GS
= -4.5 V
V
GS
= -10 V
-3.8 V
-4.0 V
-4.2 V
-4.5 V
1.0
0.25
0.20
0.15
0.10
0.05
0
2
3
4
5
6
7
8
9
10
1.5
0.5
1.25
1.00
0.75
100
1000
10000
100000
10
20
30
V
GS
= 0 V
T
J
= 100
C
T
J
= 150
C
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TYPICAL PERFORMANCE CURVES
(T
J
= 25
C unless otherwise noted)
-V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and
Drain-to-Source Voltage vs. Total Charge
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
1
0.1
-V
SD
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
-I
S
, SOURCE CURRENT (AMPS)
V
GS
= 0 V
T
J
= 25
C
10
-I
D
, DRAIN CURRENT (AMPS)
0.1
1.0
10
100
1
10
100
V
GS
= -20 V
Single Pulse T
C
= 25
C
RDS(on) Limit
Thermal Limit
Package Limit
10 ms
1 ms
dc
0.01
100
m
s
10
m
s
0.1
25
C
-55
C
100
C
150
C
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
-50
-25
0
25
50
75
100
125
150
Figure 11. V
GS(TH)
Variation with Temperature
T
J
, JUNCTION TEMPERATURE (
C)
-V
GS
(TH)
, GA
TE-T
O-SOURCE THRESHOLD
VOL
T
AGE (NORMALIZED)
I
D
= -250
m
A
V
GS
= V
DS
0.4
0.5
0.6
0.7
0.8
0.9
1.0
V
DS
= 0 V
V
GS
= 0 V
0
10
10
1600
600
400
200
0
30
-GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
0
8
2
0
Q
g
, TOTAL GATE CHARGE (nC)
-V
GS
,
GA
TE-T
O-SOURCE
VOL
T
AGE (VOL
TS)
T
J
= 25
C
C
oss
C
iss
C
rss
I
D
= -4.4 A
T
J
= 25
C
1000
12
8
4
6
Q
GS
5
800
-V
GS
-V
DS
15
4
5
1200
2
20
QT
1300
500
300
100
900
700
1100
20
25
C
iss
C
rss
10
0
20
10
-V
DS,
DRAIN-T
O-SOURCE
VOL
T
AGE (VOL
TS)
6
10
14
1
13
9
5
3
7
11
15
Q
GD
V
GS
V
DS
1400
1500
16 17 18 19
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5
1
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
0.1
R
thja(t)
, EFFECTIVE TRANSIENT THERMAL RESPONSE
Figure 12. FET Thermal Response
t, TIME (s)
0.01
0.001
1E-06
1E-05
1E-04
Duty Cycle = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
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6
PACKAGE DIMENSIONS
ChipFET
CASE 1206A-03
ISSUE E
B
S
C
D
G
L
A
1
2
3
4
8
7
6
5
M
J
K
1
2
3
4
8
7
6
5
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
2.95
3.10
0.116
0.122
B
1.55
1.70
0.061
0.067
C
1.00
1.10
0.039
0.043
D
0.25
0.35
0.010
0.014
G
0.65 BSC
0.025 BSC
J
0.10
0.20
0.004
0.008
K
0.28
0.42
0.011
0.017
L
0.55 BSC
0.022 BSC
M
5 NOM
S
1.80
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM
PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN
HORIZONTAL AND VERTICAL SHALL NOT EXCEED
0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE
BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND
BOTTOM LEAD SURFACE.
7. 1206A-01 AND 1206A-02 OBSOLETE. NEW
STANDARD IS 1206A-03.
0.05 (0.002)
5 NOM
2.00
0.072
0.080
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
Figure 13. Basic
Figure 14. Style 1
0.457
0.018
2.032
0.08
0.635
0.025
0.66
0.026
0.711
0.028
0.178
0.007
2.032
0.08
1.727
0.068
0.66
0.026
0.711
0.028
mm
inches
SCALE 20:1
0.457
0.018
SOLDER FOOTPRINT*
*For information on soldering specifications, please refer to
our Soldering Reference Manual, SOLDERRM/D.
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7
Notes
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8
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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NTHS4111P/D
ChipFET is a trademark of Vishay Siliconix
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