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Электронный компонент: NTQS6463R2

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Semiconductor Components Industries, LLC, 2004
May, 2004 - Rev. 1
1
Publication Order Number:
NTMD3P03R2/D
NTMD3P03R2
Power MOSFET
-3.05 Amps, -30 Volts
Dual P-Channel SO-8
Features
High Efficiency Components in a Dual SO-8 Package
High Density Power MOSFET with Low R
DS(on)
Miniature SO-8 Surface Mount Package - Saves Board Space
Diode Exhibits High Speed with Soft Recovery
I
DSS
Specified at Elevated Temperature
Avalanche Energy Specified
Mounting Information for the SO-8 Package is Provided
Applications
DC-DC Converters
Low Voltage Motor Control
Power Management in Portable and Battery-Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MOSFET MAXIMUM RATINGS
(T
J
= 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain-to-Source Voltage
V
DSS
-30
V
Gate-to-Source Voltage - Continuous
V
GS
20
V
Thermal Resistance -
Junction-to-Ambient (Note 1)
Total Power Dissipation @ T
A
= 25
C
Continuous Drain Current @ 25
C
Continuous Drain Current @ 70
C
Pulsed Drain Current (Note 4)
R
JA
P
D
I
D
I
D
I
DM
171
0.73
-2.34
-1.87
-8.0
C/W
W
A
A
A
Thermal Resistance -
Junction-to-Ambient (Note 2)
Total Power Dissipation @ T
A
= 25
C
Continuous Drain Current @ 25
C
Continuous Drain Current @ 70
C
Pulsed Drain Current (Note 4)
R
JA
P
D
I
D
I
D
I
DM
100
1.25
-3.05
-2.44
-12
C/W
W
A
A
A
Thermal Resistance -
Junction-to-Ambient (Note 3)
Total Power Dissipation @ T
A
= 25
C
Continuous Drain Current @ 25
C
Continuous Drain Current @ 70
C
Pulsed Drain Current (Note 4)
R
JA
P
D
I
D
I
D
I
DM
62.5
2.0
-3.86
-3.1
-15
C/W
W
A
A
A
Operating and Storage
Temperature Range
T
J
, T
stg
- 55 to
+150
C
Single Pulse Drain-to-Source Avalanche
Energy - Starting T
J
= 25
C
(V
DD
= -30 Vdc, V
GS
= -4.5 Vdc, Peak
I
L
= -7.5 Apk, L = 5 mH, R
G
= 25
)
E
AS
140
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8
from case for 10 seconds
T
L
260
C
1. Minimum FR-4 or G-10 PCB, t = Steady State.
2. Mounted onto a 2
square FR-4 Board (1
sq. 2 oz Cu 0.06
thick single
sided), t = steady state.
3. Mounted onto a 2
square FR-4 Board (1
sq. 2 oz Cu 0.06
thick single
sided), t
10 seconds.
4. Pulse Test: Pulse Width = 300
m
s, Duty Cycle = 2%.
Device
Package
Shipping
ORDERING INFORMATION
NTMD3P03R2
SO-8
2500/Tape & Reel
P-Channel
D
S
G
2
Source-1
Gate-1
Source-2
Gate-2
3
4
1
7
6
5
8
Drain-1
Drain-1
Drain-2
Drain-2
Top View
PIN ASSIGNMENT
SO-8
CASE 751
STYLE 11
ED3P03
LYWW
ED3P03
= Device Code
L
= Assembly Location
Y
= Year
WW
= Work Week
MARKING
DIAGRAM
1
8
http://onsemi.com
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
V
DSS
R
DS(ON)
TYP
I
D
MAX
-30 V
85 m
@ -10 V
-3.05 A
NTMD3P03R2
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS
(T
J
= 25
C unless otherwise noted) (Note 5)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= -250
Adc)
Temperature Coefficient (Positive)
V
(BR)DSS
-30
-
-
-30
-
-
Vdc
mV/
C
Zero Gate Voltage Drain Current
(V
DS
= -24 Vdc, V
GS
= 0 Vdc, T
J
= 25
C)
(V
DS
= -24 Vdc, V
GS
= 0 Vdc, T
J
= 125
C)
(V
DS
= -30 Vdc, V
GS
= 0 Vdc, T
J
= 25
C)
I
DSS
-
-
-
-
-
-
-1.0
-20
-2.0
Adc
Gate-Body Leakage Current
(V
GS
= -20 Vdc, V
DS
= 0 Vdc)
I
GSS
-
-
-100
nAdc
Gate-Body Leakage Current
(V
GS
= +20 Vdc, V
DS
= 0 Vdc)
I
GSS
-
-
100
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= -250
Adc)
Temperature Coefficient (Negative)
V
GS(th)
-1.0
-
-1.7
3.6
-2.5
-
Vdc
Static Drain-to-Source On-State Resistance
(V
GS
= -10 Vdc, I
D
= -3.05 Adc)
(V
GS
= -4.5 Vdc, I
D
= -1.5 Adc)
R
DS(on)
-
-
0.063
0.090
0.085
0.125
Forward Transconductance (V
DS
= -15 Vdc, I
D
= -3.05 Adc)
g
FS
-
5.0
-
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
24 Vd
V
0 Vd
C
iss
-
520
750
pF
Output Capacitance
(V
DS
= -24 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
oss
-
170
325
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
-
70
135
SWITCHING CHARACTERISTICS (Notes 6 and 7)
Turn-On Delay Time
t
d(on)
-
12
22
ns
Rise Time
(V
DD
= -24
Vdc, I
D
= -3.05 Adc,
V
GS
= 10 Vdc
t
r
-
16
30
Turn-Off Delay Time
V
GS
= -10 Vdc,
R
G
= 6.0
)
t
d(off)
-
45
80
Fall Time
R
G
6.0
)
t
f
-
45
80
Turn-On Delay Time
t
d(on)
-
16
-
ns
Rise Time
(V
DD
= -24
Vdc, I
D
= -1.5 Adc,
V
GS
= 4 5 Vdc
t
r
-
42
-
Turn-Off Delay Time
V
GS
= -4.5 Vdc,
R
G
= 6.0
)
t
d(off)
-
32
-
Fall Time
R
G
6.0
)
t
f
-
35
-
Total Gate Charge
(V
DS
= -24 Vdc,
Q
tot
-
16
25
nC
Gate-Source Charge
(V
DS
= -24
Vdc,
V
GS
= -10 Vdc,
I
3 05 Ad )
Q
gs
-
2.0
-
Gate-Drain Charge
GS
I
D
= -3.05 Adc)
Q
gd
-
4.5
-
BODY-DRAIN DIODE RATINGS (Note 6)
Diode Forward On-Voltage
(I
S
= -3.05 Adc, V
GS
= 0 V)
(I
S
= -3.05 Adc, V
GS
= 0 V, T
J
= 125
C)
V
SD
-
-
-0.96
-0.78
-1.25
-
Vdc
Reverse Recovery Time
(I
3 05 Ad
V
0 Vd
t
rr
-
34
-
ns
(I
S
= -3.05 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/
s)
t
a
-
18
-
dI
S
/dt = 100 A/
s)
t
b
-
16
-
Reverse Recovery Stored Charge
Q
RR
-
0.03
-
C
5. Handling precautions to protect against electrostatic discharge is mandatory.
6. Indicates Pulse Test: Pulse Width = 300
s max, Duty Cycle = 2%.
7. Switching characteristics are independent of operating junction temperature.
NTMD3P03R2
http://onsemi.com
3
TYPICAL ELECTRICAL CHARACTERISTICS
0.25
0.2
0.1
0.15
0.05
1
0.6
1.2
1.6
0
5
2
2
0.5
0.25
-V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
-I
D
, DRAIN CURRENT (AMPS)
0
-V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
-I
D
, DRAIN CURRENT (AMPS)
3
0.5
0.4
0.3
7
6
5
0.2
0.1
0
4
8
Figure 3. On-Resistance vs. Gate-to-Source
Voltage
-V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 4. On-Resistance vs. Gate-to-Source
Voltage
-V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
)
Figure 5. On-Resistance vs. Drain Current and
Gate Voltage
-I
D
, DRAIN CURRENT (AMPS)
Figure 6. On Resistance Variation with
Temperature
T
J
, JUNCTION TEMPERATURE (
C)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE (
)
R
DS(on)
, DRAIN-T
O-SOURCE RESIST
ANCE
(NORMALIZED)
1
3
2
5
4
1
4
3
2
5
-50
50
75
25
0
150
-25
0.75
1
3
4
V
GS
= -8 V
V
GS
= -6 V
V
GS
= -4.8 V
V
GS
= -5 V
V
GS
= -4.4 V
V
GS
= -3.6 V
V
DS
> = -10 V
T
J
= 25
C
T
J
= -55
C
T
J
= 100
C
V
GS
= -10 V
V
GS
= -4.5 V
6
I
D
= -3.05 A
V
GS
= -10 V
6
0.6
0.7
V
GS
= -4.6 V
V
GS
= -10 V
I
D
= -3.05 A
T
J
= 25
C
T
J
= 25
C
1
1.25
1.5
1.75
5
2
0
1
3
4
6
2
0.5
0.4
0.3
6
5
4
0.2
0.1
0
3
7
0.6
0.7
1.4
0.8
V
GS
= -3.2 V
V
GS
= -3 V
V
GS
= -2.6 V
I
D
= -1.5 A
T
J
= 25
C
100
125
V
GS
= -4 V
T
J
= 25
C
V
GS
= -2.8 V
NTMD3P03R2
http://onsemi.com
4
30
15
0
25
20
10
5
6
18
22
14
26
10
30
I
D
= -3.05 A
T
J
= 25
C
V
GS
Q
2
Q
1
Q
T
1000
100
10
12
6
0
1200
1000
800
600
400
200
0
3
2
0.5
0
1000
100
1
10000
1000
-V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
I
DSS
, LEAKAGE (nA)
100
10
GATE-TO-SOURCE OR DRAIN-TO-SOURCE
VOLTAGE (VOLTS)
Figure 7. Drain-to-Source Leakage Current
vs. Voltage
Figure 8. Capacitance Variation
C, CAP
ACIT
ANCE (pF)
Figure 9. Gate-to-Source and
Drain-to-Source Voltage vs. Total Charge
Q
g
, TOTAL GATE CHARGE (nC)
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
R
G
, GATE RESISTANCE (
)
t, TIME (ns)
-V
GS
, GA
TE-T
O-SOURCE VOL
T
AGE (VOL
TS)
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
R
G
, GATE RESISTANCE (
)
Figure 12. Diode Forward Voltage vs. Current
-V
SD
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
t, TIME (ns)
I
S
, SOURCE CURRENT (AMPS)
0
8
16
1
100
1
100
10
0.2
1
1.2
0.8
0.6
0.4
V
GS
= 0 V
T
J
= 125
C
C
rss
C
iss
C
oss
C
rss
10
10
C
iss
V
DS
= -24 V
I
D
= -3.05 A
V
GS
= -10 V
t
r
t
d(off)
t
d(on)
t
f
1
1.5
2.5
10
8
4
2
2
4
6
10
12
14
T
J
= 150
C
T
J
= 25
C
V
DS
= -24 V
I
D
= -1.5 A
V
GS
= -4.5 V
t
r
t
d(off)
t
d(on)
t
f
V
GS
= 0 V
T
J
= 25
C
10
15
20
10
5
5
30
0
25
V
DS
V
DS
= 0 V
V
GS
= 0 V
-V
GS
-V
DS
NTMD3P03R2
http://onsemi.com
5
R
thja(t)
, EFFECTIVE TRANSIENT
THERMAL RESPONSE
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
di/dt
t
rr
t
a
t
p
I
S
0.25 I
S
TIME
I
S
t
b
Figure 14. Diode Reverse Recovery Waveform
100
1.0
0.01
Figure 15. FET Thermal Response
-V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
1
100
10
-I
D
, DRAIN CURRENT (AMPS)
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
V
GS
= 12 V
SINGLE PULSE
T
C
= 25
C
10 ms
dc
1.0 ms
1.0
0.1
10
1.0
0.1
0.01
1E-03
1E-02
1E-01
1E+00
1E+01
1E+02
1E+03
D = 0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
0.0014 F
0.0073 F
0.022 F
0.105 F
0.484 F
Ambient
Chip
Junction 2.32
18.5
50.9
37.1
56.8
Normalized to R
JA
at Steady State (1
pad)
3.68 F
24.4
t, TIME (s)
NTMD3P03R2
http://onsemi.com
6
PACKAGE DIMENSIONS
SO-8
CASE 751-07
ISSUE AB
SEATING
PLANE
1
4
5
8
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN
MAX
MIN
MAX
INCHES
4.80
5.00
0.189
0.197
MILLIMETERS
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.053
0.069
D
0.33
0.51
0.013
0.020
G
1.27 BSC
0.050 BSC
H
0.10
0.25
0.004
0.010
J
0.19
0.25
0.007
0.010
K
0.40
1.27
0.016
0.050
M
0
8
0
8
N
0.25
0.50
0.010
0.020
S
5.80
6.20
0.228
0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010)
Z
S
X
S
M
_
_
_
_
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
mm
inches
SCALE 6:1
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
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USA/Canada
Japan: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
NTMD3P03R2/D
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