Semiconductor Components Industries, LLC, 2001
October, 2001 Rev. 7
1
Publication Order Number:
SN74LS166/D
SN74LS166
8-Bit Shift Registers
The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 74LS standard
load. By utilizing input clamping diodes, switching transients are
minimized and system design simplified.
The LS166 is a parallel-in or serial-in, serial-out shift register and
has a complexity of 77 equivalent gates with gated clock inputs and an
overriding clear input. The shift/load input establishes the parallel-in
or serial-in mode. When high, this input enables the serial data input
and couples the eight flip-flops for serial shifting with each clock
pulse. Synchronous loading occurs on the next clock pulse when this is
low and the parallel data inputs are enabled. Serial data flow is
inhibited during parallel loading. Clocking is done on the low-to-high
level edge of the clock pulse via a two input positive NOR gate, which
permits one input to be used as a clock enable or clock inhibit function.
Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow
the system clock to be free running and the register stopped on
command with the other clock input. A change from low-to-high on
the clock inhibit input should only be done when the clock input is
high. A buffered direct clear input overrides all other inputs, including
the clock, and sets all flip-flops to zero.
Synchronous Load
Direct Overriding Clear
Parallel to Serial Conversion
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
4.75
5.0
5.25
V
TA
Operating Ambient
Temperature Range
0
25
70
C
IOH
Output Current High
0.4
mA
IOL
Output Current Low
8.0
mA
LOW
POWER
SCHOTTKY
SOIC
D SUFFIX
CASE 751B
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SOEIAJ
M SUFFIX
CASE 966
16
1
Device
Package
Shipping
ORDERING INFORMATION
SN74LS166N
16 Pin DIP
2000 Units/Box
SN74LS166D
SOIC16
38 Units/Rail
SN74LS166DR2
SOIC16
2500/Tape & Reel
SN74LS166M
SOEIAJ16
See Note 1
SN74LS166MEL
SOEIAJ16
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
See Note 1
http://onsemi.com
SN74LS166
http://onsemi.com
2
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
SERIAL
INPUT
SHIFT/
LOAD
H
QH
G
E
F
CLEAR
A
B
C
D
CLOCK
INHIBIT
CLOCK GND
PARALLEL
PARALLEL INPUTS
INPUT OUTPUT
PARALLEL INPUTS
SHIFT/
LOAD
SERIAL INPUT
CLOCK
INHIBIT
H
QH
G
F
E
A
B
C
D
CK
CLEAR
FUNCTION TABLE
INPUTS
INTERNAL
CLEAR
SHIFT/
CLOCK
CLOCK
SERIAL
PARALLEL
INTERNAL
OUTPUTS
OUTPUT
QH
CLEAR
SHIFT/
LOAD
CLOCK
INHIBIT
CLOCK
SERIAL
A . . . H
QA
QB
QH
L
X
X
X
X
X
L
L
L
H
X
L
L
X
X
QA0
QB0
QH0
H
L
L
X
a . . . h
a
b
h
H
H
L
H
X
H
QAn
QGn
H
H
L
L
X
L
QAn
QGn
H
X
H
X
X
QA0
QB0
QH0
SN74LS166
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3
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
PARALLEL
INPUTS
A
B
C
D
CLOCK INIHIBIT
CLOCK
SHIFT/LOAD
H
OUTPUT QH
G
F
E
CLEAR
SERIAL INPUT
H
H
H
H
H
L
L
L
H H
H
H
H
L
L
L
CLEAR
SERIAL SHIFT
LOAD
INHIBIT
SERIAL SHIFT
CLEAR
SERIAL INPUT
SHIFT/LOAD
A
B
C
D
H
G
F
E
(9)
(1)
(15)
(2)
(3)
(4)
(5)
(10)
(11)
(12)
(14)
(7)
(6)
CLOCK INHIBIT
CLOCK
(13)
R
CK
S
QA
R
CK
S
QB
R
CK
S
QC
R
CK
S
QD
R
CK
S
QE
R
CK
S
QF
R
CK
S
QG
R
CK
S
QH
SN74LS166
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4
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN VIL or VIH
VOL
Output LOW Voltage
0.35
0.5
V
IOL = 8.0 mA
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 2)
20
100
mA
VCC = MAX
ICC
Power Supply Current
38
mA
VCC = MAX
2. Not more than one output should be shorted at a time, nor for more than 1 second.
SN74LS166
http://onsemi.com
5
TEST TABLE FOR SYNCHRONOUS INPUTS
DATA INPUT
FOR TEST
SHIFT/LOAD
OUTPUT TESTED
H
0 V
QH at tn+1
Serial
Input
4.5 V
QH at tn+8
AC WAVEFORMS
NOTE 1. tn = bit time before clocking transition
NOTE 1.
tn+1 = bit time after one clocking transition
NOTE 1.
tn+8 = bit time after eight clocking transition
NOTE 1.
LS166 Vref = 1.3 V.
CLEAR INPUT
CLOCK INPUT
DATA
INPUT
(SEE TEST
TABLE)
OUTPUT Q
Vref
tw(clear)
tPHL
(clear Q)
(SEE NOTE 1)
tn + 1
tn
tsu
th
tPLH
(CLK Q)
3 V
0 V
VOH
VOL
3 V
3 V
0 V
0 V
Vref
Vref
Vref
Vref
Vref
Vref
Vref
Vref
tn
tn + 1
tsu
th
tPHL
tw(clock)
(CLK Q)
Vref
Vref
Vref
AC CHARACTERISTICS
(TA = 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Clock Frequency
25
35
MHz
tPHL
Clear to Output
19
30
ns
VCC = 5.0 V
C
15 F
tPLH
tPHL
Clock to Output
23
24
35
35
ns
CC
CL = 15 pF
AC SETUP REQUIREMENTS
(TA = 25
C)
Limits
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
Clock Clear Pulse Width
30
ns
ts
Mode Control Setup Time
30
ns
VCC = 5 0 V
ts
Data Setup Time
20
ns
VCC = 5.0 V
th
Hold Time, Any Input
15
ns
SN74LS166
http://onsemi.com
6
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1
8
9
16
K
PLANE
T
M
A
M
0.25 (0.010)
T
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.740
0.770
18.80
19.55
B
0.250
0.270
6.35
6.85
C
0.145
0.175
3.69
4.44
D
0.015
0.021
0.39
0.53
F
0.040
0.70
1.02
1.77
G
0.100 BSC
2.54 BSC
H
0.050 BSC
1.27 BSC
J
0.008
0.015
0.21
0.38
K
0.110
0.130
2.80
3.30
L
0.295
0.305
7.50
7.74
M
0
10
0
10
S
0.020
0.040
0.51
1.01
_
_
_
_
SN74LS166
http://onsemi.com
7
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
8
16
9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PL
P
B
A
M
0.25 (0.010)
B
S
T
D
K
C
16 PL
S
B
M
0.25 (0.010)
A
S
T
DIM
MIN
MAX
MIN
MAX
INCHES
MILLIMETERS
A
9.80
10.00
0.386
0.393
B
3.80
4.00
0.150
0.157
C
1.35
1.75
0.054
0.068
D
0.35
0.49
0.014
0.019
F
0.40
1.25
0.016
0.049
G
1.27 BSC
0.050 BSC
J
0.19
0.25
0.008
0.009
K
0.10
0.25
0.004
0.009
M
0
7
0
7
P
5.80
6.20
0.229
0.244
R
0.25
0.50
0.010
0.019
_
_
_
_
SN74LS166
http://onsemi.com
8
PACKAGE DIMENSIONS
HE
A1
DIM
MIN
MAX
MIN
MAX
INCHES
---
2.05
---
0.081
MILLIMETERS
0.05
0.20
0.002
0.008
0.35
0.50
0.014
0.020
0.18
0.27
0.007
0.011
9.90
10.50
0.390
0.413
5.10
5.45
0.201
0.215
1.27 BSC
0.050 BSC
7.40
8.20
0.291
0.323
0.50
0.85
0.020
0.033
1.10
1.50
0.043
0.059
0
0.70
0.90
0.028
0.035
---
0.78
---
0.031
A1
HE
Q1
LE
_
10
_
0
_
10
_
LE
Q1
_
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
L
DETAIL P
VIEW P
c
A
b
e
M
0.13 (0.005)
0.10 (0.004)
1
16
9
8
D
Z
E
A
b
c
D
E
e
L
M
Z
M SUFFIX
SOEIAJ PACKAGE
CASE 96601
ISSUE O
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For additional information, please contact your local
Sales Representative.
SN74LS166/D
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