Page 1 of 7
Document No. 70-0037-05
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Parameter Conditions
Minimum
Typical
Maximum
Units
Operating Frequency
1
DC
3000
MHz
Insertion Loss
1000 MHz
2000 MHz
0.30
0.45
0.40
0.60
dB
dB
Isolation RFC to RF1/RF2
1000 MHz
2000 MHz
34.5
24.5
35.5
25
dB
dB
Isolation RF1 to RF2
1000 MHz
2000 MHz
36.5
25.5
37.5
26.5
dB
dB
Return Loss
1000 MHz
2000 MHz
22.5
15
24.5
16
dB
dB
`ON' Switching Time
CTRL to 0.1 dB final value, 2 GHz
200
ns
`OFF' Switching Time
CTRL to 25 dB isolation, 2 GHz
90
ns
Video Feedthrough
2
2.5
mV
pp
Input 1 dB Compression
2000 MHz
13
14.5
dBm
Input IP3
2000 MHz, 5 dBm
30
33.5
dBm
8-lead MSOP
RFC
RF1
RF2
CMOS
Control
Driver
CTRL
The PE4210 UltraCMOSTM RF Switch is designed to cover a
broad range of applications from near DC to 3000 MHz. This
single-supply switch integrates on-board CMOS control logic
driven by a simple, single-pin CMOS or TTL compatible control
input. Using a nominal +3-volt power supply, a typical input
1 dB compression point of +14 dBm can be achieved. The
PE4210 also exhibits input-output isolation of better than 35 dB
at 1000 MHz and is offered in a small 8-lead MSOP package.
The PE4210 UltraCMOSTM RF Switch is manufactured in
Peregrine's patented Ultra Thin Silicon (UTSi) CMOS
process, offering the performance of GaAs with the economy
and integration of conventional CMOS.
Product Specification
SPDT UltraCMOSTM RF Switch
DC - 3000 MHz
Product Description
Figure 1. Functional Diagram
PE4210
Features
Single 3-volt power supply
Low Insertion loss: 0.30 dB at 1000 MHz,
0.45 dB at 2000 MHz
High isolation of 35 dB at 1000 MHz,
25 dB at 2000 MHz
Typical input 1 dB compression point of
+14.5 dBm
Single-pin CMOS or TTL logic control
Packaged in a small 8-lead MSOP
Notes:
1. Device linearity will begin to degrade below 10 MHz.
2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low
in a 50
test set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.
Table 1. Electrical Specifications @ +25 C, V
DD
= 3 V (Z
S
= Z
L
= 50
)
Figure 2. Package Type
Product Specification
PE4210
Page 2 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0037-05
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 V
DC
.
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 3. DC Electrical Specifications
4210
1
2
3
4
8
7
6
5
CTRL
RFC
GND
RF1
GND
V
DD
GND
RF2
Table 5. Control Logic Truth Table
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Pin
No.
Pin
Name
Description
1 V
DD
Nominal 3 V supply connection. A by-
pass capacitor (100 pF) to the ground
plane should be placed as close as pos-
sible to the pin
2
CTRL
CMOS or TTL logic level:
High = RFC to RF1 signal path
Low = RFC to RF2 signal path
3
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
4
RFC
Common RF port for switch (Note 1)
5
RF2
RF2 port (Note 1)
6
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
7
GND
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
8
RF1
RF1 port (Note 1)
Symbol Parameter/Conditions Min
Max Units
V
DD
Power
Supply
Voltage -0.3 4.0
V
V
I
Voltage on any input
-0.3
V
DD
+ 0.3
V
T
ST
Storage temperature
range
-65 150 C
T
OP
Operating temperature
range
-40 85 C
P
IN
Input power (50
)
18
dBm
V
ESD
ESD Voltage (Human
Body Model)
200
V
Parameter Min
Typ
Max
Units
V
DD
Power Supply
Voltage
2.7 3.0 3.3 V
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3)
250 500 nA
Control Voltage High
0.7x V
DD
V
Control Voltage Low
0.3x V
DD
V
Control Voltage
Signal Path
CTRL = CMOS or TTL High
RFC to RF1
CTRL = CMOS or TTL Low
RFC to RF2
Control Logic
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
Product Specification
PE4210
Page 3 of 7
Document No. 70-0037-05
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4210 SPDT switch. The RF common port is
connected through a 50
transmission line to the
top left SMA connector, J1. Port 1 and Port 2 are
connected through 50
transmission lines to the top
two SMA connectors on the right side of the board,
J3 and J4. A through transmission line connects
SMA connectors J6 and J8. This transmission line
can be used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031". The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide model with a trace width of
0.030", trace gaps of 0.007", dielectric thickness of
0.028", metal thickness of 0.0014" and
r
of 4.4. Note
that the predominate mode for these transmission
lines is coplanar waveguide with a ground plane.
J2 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left pin,
the second pin to the right (J2-3) is connected to the
device CTRL input. The fourth pin to the right (J2-7)
is connected to the device V
DD
input. A decoupling
capacitor (100 pF) is provided on both CTRL and
V
DD
traces. It is the responsibility of the customer to
determine proper supply decoupling for their design
application. Removing these components from the
evaluation board has not been shown to degrade RF
performance.
Figure 4. Evaluation Board Layout
Figure 5. Evaluation Board Schematic
Peregrine specification 101/0037
Peregrine specification 102/0035
Product Specification
PE4210
Page 4 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0037-05
UltraCMOSTM RFIC Solutions
Typical Performance Data @ -40 C to 85 C (Unless otherwise noted)
Figure 7. Input 1 dB Compression Point & IIP3
Figure 9. Isolation RFC to RF1
Figure 8. Insertion Loss RFC to RF2
Figure 6. Insertion Loss RFC to RF1
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0
500
1000
1500
2000
2500
3000
I
n
s
e
rti
o
n
L
o
s
s
(d
B
)
Frequency (MHz)
-40 C
85 C
25 C
0
10
20
30
40
0
10
20
30
40
500
1000
1500
2000
2500
II
P
3
(
d
B
m
)
1
d
B
C
o
mpr
e
s
s
i
on P
o
i
n
t
(
d
B
m
)
Frequency (MHz)
IIP3
1dB Compression
-40 C
25 C
-40 C
85 C
25 C
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0
500
1000
1500
2000
2500
3000
I
n
s
e
rti
o
n
L
o
s
s
(d
B
)
Frequency (MHz)
-40 C
85 C
25 C
-100
-80
-60
-40
-20
0
0
500
1000
1500
2000
2500
3000
Is
o
l
a
t
i
o
n
(
d
B)
Frequency (MHz)
T = 25 C
Product Specification
PE4210
Page 5 of 7
Document No. 70-0037-05
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
Figure 11. Isolation RF1 to RF2, RF2 to RF1
Figure 13. Return Loss RF1, RF2
Figure 12. Return Loss RFC to RF1, RF2
Figure 10. Isolation RFC to RF2
Typical Performance Data @ 25 C
-100
-80
-60
-40
-20
0
0
500
1000
1500
2000
2500
3000
Is
o
l
a
t
i
o
n
(
d
B
)
Frequency (MHz)
-100
-80
-60
-40
-20
0
0
500
1000
1500
2000
2500
3000
Is
o
l
a
t
i
o
n
(
d
B
)
Frequency (MHz)
RF1
RF2
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
Re
t
u
r
n
L
o
s
s
(
d
B)
Frequency (MHz)
-40
-30
-20
-10
0
0
500
1000
1500
2000
2500
3000
Re
t
u
r
n
L
o
s
s
(
d
B
)
Frequency (MHz)
RF1
RF2
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