Page 1 of 7
Document No. 70-0097-01
www.psemi.com
2005 Peregrine Semiconductor Corp. All rights reserved.
RFCommon
RF1
RF2
CMOS
Control
Driver
CTRL
The PE4231 SPDT High Power
UltraCMOSTM
RF Switch is
designed to cover a broad range of applications from DC to 1.3
GHz. This single-supply reflective switch integrates on-board
CMOS control logic driven by a simple, single-pin CMOS or
TTL compatible control input. Using a nominal +3-volt power
supply, a typical input 1 dB compression point of +32 dBm can
be achieved. The PE4231 also exhibits input-output isolation of
better than 42 dB at 1.0 GHz and is offered in a small 8-lead
MSOP package.
The PE4231 SPDT High Power
UltraCMOSTM
RF Switch is
manufactured in Peregrine's patented Ultra Thin Silicon
(UTSi
) CMOS process, offering the performance of GaAs with
the economy and integration of conventional CMOS.
Product Specification
SPDT High Power UltraCMOSTM
DC 1.3 GHz RF Switch
Product Description
Figure 1. Functional Diagram
PE4231
Features
Optimized for 75
systems
Single +3-volt power supply
Low insertion loss: 0.80 dB at 1.0 GHz
High isolation: 42 dB at 1.0 GHz
Typical input 1 dB compression point of
+32 dBm
Single-pin CMOS or TTL logic control
Low cost
Notes:
1. Device linearity will begin to degrade below 1 MHz.
2. Measured with a 1 ns risetime, 0/3 V pulse and 500 MHz bandwidth.
3. Measured in a 50
system.
Figure 2. Package Type
Table 1. Electrical Specifications @ +25 C, V
DD
= 3 V (Z
S
= Z
L
= 75
)
Parameter Conditions
Minimum
Typical
Maximum
Units
Operation Frequency
1
DC
1300
MHz
Insertion Loss
50 MHz
1000 MHz
0.50
0.80
0.60
0.90
dB
Isolation RFCommon to
RF1/RF2
50 MHz
1000 MHz
73
40
75
42
dB
Isolation RF1 to RF2
50 MHz
1000 MHz
58
33
60
35
dB
Return Loss
1000 MHz
16
17
dB
`ON' Switching Time
CTRL to 0.1 dB final value, 2 GHz
2000
ns
`OFF' Switching Time
CTRL to 25 dB isolation, 2 GHz
900
ns
Video Feedthrough
2
15
mV
pp
Input 1 dB Compression
3
1000 MHz
30
32
dBm
Input IP3
3
1000 MHz, 17 dBm
50
dBm
8-lead MSOP
Product Specification
PE4231
Page 2 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0097-01
UltraCMOSTM RFIC Solutions
Table 2. Pin Descriptions
Table 3. Absolute Maximum Ratings
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOSTM device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOSTM
devices are immune to latch-up.
Table 4. DC Electrical Specifications
Note 1: All RF pins must be DC blocked with an external
series capacitor or held at 0 V
DC
.
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
Figure 3. Pin Configuration (Top View)
4231
1
2
3
4
8
7
6
5
V
DD
CTRL
GND
RFCommon
RF1
GND
GND
RF2
Pin
No.
Pin Name
Description
1 V
DD
Nominal +3 V supply connection.
2
CTRL
CMOS or TTL logic level:
High = RFCommon to RF1 signal path
Low = RFCommon to RF2 signal path
3
GND
Ground connection. Traces should be
physically short and connected to ground
4
RF Common
Common RF port for switch.
1
5 RF2
RF2
port.
1
6
GND
Ground Connection. Traces should be
physically short and connected to ground
7
GND
Ground Connection. Traces should be
physically short and connected to ground
8 RF1
RF1
port.
1
Symbol Parameter/
Conditions
Min Max Units
V
DD
Power
supply
voltage -0.3
4.0 V
V
I
Voltage on any input ex-
cept for the CTRL input
-0.3
V
DD
+
0.3
V
V
CTRL
Voltage on CTRL input
5.0
V
T
ST
Storage temperature
range
-65 150 C
T
OP
Operating temperature
range
-40 85 C
P
IN
Input power (50
)
33
dBm
V
ESD
ESD voltage (Human
Body Model)
200
V
Parameter Min
Typ
Max
Units
V
DD
Power Supply
Voltage
2.7 3.0 3.3 V
I
DD
Power Supply Current
(V
DD
= 3V, V
CNTL
= 3V)
29
35
A
Control Voltage High
0.7xV
DD
V
Control Voltage Low
0.3xV
DD
V
Table 5. Truth Table
Control Voltage
Signal Path
CTRL = CMOS or TTL High
RFCommon to RF1
CTRL = CMOS or TTL Low
RFCommon to RF2
Product Specification
PE4231
Page 3 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0097-01
www.psemi.com
-100
-80
-60
-40
-20
0
0
200
400
600
800
1000
1200
Is
o
l
a
t
i
o
n
(d
B)
Frequency (MHz)
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0
200
400
600
800
1000
1200
I
n
s
e
r
t
i
o
n
L
o
ss (
d
B
)
Frequency (MHz)
-40
8C
85
8
C
25
8C
0
10
20
30
40
0
200
400
600
800
1000
1200
1dB
Com
p
r
e
s
s
i
o
n
P
o
i
n
t
(
d
B
m
)
Frequency (MHz)
-40
8C
85
8
C
25
8C
-1.5
-1.25
-1
-0.75
-0.5
-0.25
0
0
200
400
600
800
1000
1200
I
n
s
e
r
t
i
o
n
L
o
ss (
d
B
)
Frequency (MHz)
-40
8C
85
8
C
25
8C
Typical Performance Data @ -40 C to 85 C (Unless Otherwise Noted)
Figure 4. Insertion Loss RFC to RF1
Figure 5. Input 1dB Compression Point
Figure 6. Insertion Loss RFC to RF2
Figure 7. Isolation RFC to RF1
Product Specification
PE4231
Page 4 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0097-01
UltraCMOSTM RFIC Solutions
-100
-80
-60
-40
-20
0
0
200
400
600
800
1000
1200
Is
o
l
a
t
i
o
n
(
d
B)
Frequency (MHz)
-100
-80
-60
-40
-20
0
0
200
400
600
800
1000
1200
Is
o
l
a
t
i
o
n
(
d
B
)
Frequency (MHz)
RF1
RF2
-40
-30
-20
-10
0
0
200
400
600
800
1000
1200
Re
t
u
r
n
L
o
s
s
(
d
B)
Frequency (MHz)
-40
-30
-20
-10
0
0
200
400
600
800
1000
1200
Re
t
u
r
n
L
o
s
s
(
d
B
)
Frequency (MHz)
RF1
RF2
Typical Performance Data @ -40 C to 85 C (Unless Otherwise Noted)
Figure 8. Isolation RFC to RF2
Figure 9. Isolation RF1 to RF2, RF2 to RF1
Figure 10. Return Loss RFC
Figure 11. Return Loss RF1, RF2
Product Specification
PE4231
Page 5 of 7
2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0097-01
www.psemi.com
Evaluation Kit
The SPDT Switch Evaluation Kit board was
designed to ease customer evaluation of the
PE4231 SPDT switch. The RF common port is
connected through a 75
transmission line to the
top left BNC connector, J1. Port 1 and Port 2 are
connected through 75
transmission lines to the
top two BNC connectors on the right side of the
board, J2 and J3. A through transmission line
connects BNC connectors J4 and J5. This
transmission line can be used to estimate the loss
of the PCB over the environmental conditions
being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031". The
bottom layer provides ground for the RF
transmission lines. The transmission lines were
designed using a coplanar waveguide with ground
plane model using a trace width of 0.021", trace
gaps of 0.030", dielectric thickness of 0.028",
metal thickness of 0.0014" and
r
of 4.4.
J6 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left
pin, the second pin to the right (J6-3) is connected
to the device CNTL input. The fourth pin to the
right (J6-7) is connected to the device VDD input.
A decoupling capacitor (100 pF) is provided on
both CNTL and VDD traces. It is the responsibility
of the customer to determine proper supply
decoupling for their design application. Removing
these components from the evaluation board has
not been shown to degrade RF performance.
Figure 8. Evaluation Board Layouts
Figure 9. Evaluation Board Schematic
VDD
CNTL
GND
RFC
RF1
GND
GND
RF2
100 pF
Optional
100 pF
Optional
J6-7
J6-3
J1
J2
J3
J5
J4
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